sam4e_eth_driver.h
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1 /**
2  * @file sam4e_eth_driver.h
3  * @brief SAM4E Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _SAM4E_ETH_DRIVER_H
32 #define _SAM4E_ETH_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef SAM4E_ETH_TX_BUFFER_COUNT
36  #define SAM4E_ETH_TX_BUFFER_COUNT 2
37 #elif (SAM4E_ETH_TX_BUFFER_COUNT < 1)
38  #error SAM4E_ETH_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef SAM4E_ETH_TX_BUFFER_SIZE
43  #define SAM4E_ETH_TX_BUFFER_SIZE 1536
44 #elif (SAM4E_ETH_TX_BUFFER_SIZE != 1536)
45  #error SAM4E_ETH_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef SAM4E_ETH_RX_BUFFER_COUNT
50  #define SAM4E_ETH_RX_BUFFER_COUNT 48
51 #elif (SAM4E_ETH_RX_BUFFER_COUNT < 12)
52  #error SAM4E_ETH_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef SAM4E_ETH_RX_BUFFER_SIZE
57  #define SAM4E_ETH_RX_BUFFER_SIZE 128
58 #elif (SAM4E_ETH_RX_BUFFER_SIZE != 128)
59  #error SAM4E_ETH_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Interrupt priority grouping
63 #ifndef SAM4E_ETH_IRQ_PRIORITY_GROUPING
64  #define SAM4E_ETH_IRQ_PRIORITY_GROUPING 3
65 #elif (SAM4E_ETH_IRQ_PRIORITY_GROUPING < 0)
66  #error SAM4E_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
67 #endif
68 
69 //Ethernet interrupt group priority
70 #ifndef SAM4E_ETH_IRQ_GROUP_PRIORITY
71  #define SAM4E_ETH_IRQ_GROUP_PRIORITY 12
72 #elif (SAM4E_ETH_IRQ_GROUP_PRIORITY < 0)
73  #error SAM4E_ETH_IRQ_GROUP_PRIORITY parameter is not valid
74 #endif
75 
76 //Ethernet interrupt subpriority
77 #ifndef SAM4E_ETH_IRQ_SUB_PRIORITY
78  #define SAM4E_ETH_IRQ_SUB_PRIORITY 0
79 #elif (SAM4E_ETH_IRQ_SUB_PRIORITY < 0)
80  #error SAM4E_ETH_IRQ_SUB_PRIORITY parameter is not valid
81 #endif
82 
83 //Legacy definitions
84 #ifndef PIO_PD6A_GRX1
85  #define PIO_PD6A_GRX1 PIO_PD6A_GRX0
86 #endif
87 
88 //MII signals
89 #define GMAC_MII_MASK (PIO_PD16A_GTX3 | \
90  PIO_PD15A_GTX2 | PIO_PD14A_GRXCK | PIO_PD13A_GCOL | PIO_PD12A_GRX3 | \
91  PIO_PD11A_GRX2 | PIO_PD10A_GCRS | PIO_PD9A_GMDIO | PIO_PD8A_GMDC | \
92  PIO_PD7A_GRXER | PIO_PD6A_GRX1 | PIO_PD5A_GRX0 | PIO_PD4A_GRXDV | \
93  PIO_PD3A_GTX1 | PIO_PD2A_GTX0 | PIO_PD1A_GTXEN | PIO_PD0A_GTXCK)
94 
95 //TX buffer descriptor flags
96 #define GMAC_TX_USED 0x80000000
97 #define GMAC_TX_WRAP 0x40000000
98 #define GMAC_TX_RLE_ERROR 0x20000000
99 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
100 #define GMAC_TX_AHB_ERROR 0x08000000
101 #define GMAC_TX_LATE_COL_ERROR 0x04000000
102 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
103 #define GMAC_TX_NO_CRC 0x00010000
104 #define GMAC_TX_LAST 0x00008000
105 #define GMAC_TX_LENGTH 0x00003FFF
106 
107 //RX buffer descriptor flags
108 #define GMAC_RX_ADDRESS 0xFFFFFFFC
109 #define GMAC_RX_WRAP 0x00000002
110 #define GMAC_RX_OWNERSHIP 0x00000001
111 #define GMAC_RX_BROADCAST 0x80000000
112 #define GMAC_RX_MULTICAST_HASH 0x40000000
113 #define GMAC_RX_UNICAST_HASH 0x20000000
114 #define GMAC_RX_SAR 0x08000000
115 #define GMAC_RX_SAR_MASK 0x06000000
116 #define GMAC_RX_TYPE_ID 0x01000000
117 #define GMAC_RX_SNAP 0x01000000
118 #define GMAC_RX_TYPE_ID_MASK 0x00C00000
119 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
120 #define GMAC_RX_VLAN_TAG 0x00200000
121 #define GMAC_RX_PRIORITY_TAG 0x00100000
122 #define GMAC_RX_VLAN_PRIORITY 0x000E0000
123 #define GMAC_RX_CFI 0x00010000
124 #define GMAC_RX_EOF 0x00008000
125 #define GMAC_RX_SOF 0x00004000
126 #define GMAC_RX_LENGTH_MSB 0x00002000
127 #define GMAC_RX_BAD_FCS 0x00002000
128 #define GMAC_RX_LENGTH 0x00001FFF
129 
130 //C++ guard
131 #ifdef __cplusplus
132 extern "C" {
133 #endif
134 
135 
136 /**
137  * @brief Transmit buffer descriptor
138  **/
139 
140 typedef struct
141 {
142  uint32_t address;
143  uint32_t status;
145 
146 
147 /**
148  * @brief Receive buffer descriptor
149  **/
150 
151 typedef struct
152 {
153  uint32_t address;
154  uint32_t status;
156 
157 
158 //SAM4E Ethernet MAC driver
159 extern const NicDriver sam4eEthDriver;
160 
161 //SAM4E Ethernet MAC related functions
162 error_t sam4eEthInit(NetInterface *interface);
163 void sam4eEthInitGpio(NetInterface *interface);
164 void sam4eEthInitBufferDesc(NetInterface *interface);
165 
166 void sam4eEthTick(NetInterface *interface);
167 
168 void sam4eEthEnableIrq(NetInterface *interface);
169 void sam4eEthDisableIrq(NetInterface *interface);
170 void sam4eEthEventHandler(NetInterface *interface);
171 
173  const NetBuffer *buffer, size_t offset);
174 
176 
179 
180 void sam4eEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
181  uint8_t regAddr, uint16_t data);
182 
183 uint16_t sam4eEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
184  uint8_t regAddr);
185 
186 //C++ guard
187 #ifdef __cplusplus
188 }
189 #endif
190 
191 #endif
void sam4eEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t opcode
Definition: dns_common.h:172
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void sam4eEthTick(NetInterface *interface)
SAM4E Ethernet MAC timer handler.
void sam4eEthInitGpio(NetInterface *interface)
Transmit buffer descriptor.
error_t sam4eEthInit(NetInterface *interface)
SAM4E Ethernet MAC initialization.
Receive buffer descriptor.
void sam4eEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t sam4eEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sam4eEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void sam4eEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint16_t regAddr
const NicDriver sam4eEthDriver
SAM4E Ethernet MAC driver.
void sam4eEthEnableIrq(NetInterface *interface)
Enable interrupts.
void sam4eEthEventHandler(NetInterface *interface)
SAM4E Ethernet MAC event handler.
error_t sam4eEthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
error_t sam4eEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t sam4eEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.