sam4e_eth_driver.c
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1 /**
2  * @file sam4e_eth_driver.c
3  * @brief SAM4E Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "sam4e.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
48 //RX buffer
49 #pragma data_alignment = 8
51 //TX buffer descriptors
52 #pragma data_alignment = 4
53 static Sam4eTxBufferDesc txBufferDesc[SAM4E_ETH_TX_BUFFER_COUNT];
54 //RX buffer descriptors
55 #pragma data_alignment = 4
56 static Sam4eRxBufferDesc rxBufferDesc[SAM4E_ETH_RX_BUFFER_COUNT];
57 
58 //Keil MDK-ARM or GCC compiler?
59 #else
60 
61 //TX buffer
63  __attribute__((aligned(8)));
64 //RX buffer
66  __attribute__((aligned(8)));
67 //TX buffer descriptors
69  __attribute__((aligned(4)));
70 //RX buffer descriptors
72  __attribute__((aligned(4)));
73 
74 #endif
75 
76 //TX buffer index
77 static uint_t txBufferIndex;
78 //RX buffer index
79 static uint_t rxBufferIndex;
80 
81 
82 /**
83  * @brief SAM4E Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  FALSE
104 };
105 
106 
107 /**
108  * @brief SAM4E Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116  volatile uint32_t status;
117 
118  //Debug message
119  TRACE_INFO("Initializing SAM4E Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable GMAC peripheral clock
125  PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
126 
127  //GPIO configuration
128  sam4eEthInitGpio(interface);
129 
130  //Configure MDC clock speed
131  GMAC->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
132  //Enable management port (MDC and MDIO)
133  GMAC->GMAC_NCR |= GMAC_NCR_MPE;
134 
135  //PHY transceiver initialization
136  error = interface->phyDriver->init(interface);
137  //Failed to initialize PHY transceiver?
138  if(error)
139  return error;
140 
141  //Set the MAC address
142  GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
143  GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
144 
145  //Configure the receive filter
146  GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
147 
148  //Initialize hash table
149  GMAC->GMAC_HRB = 0;
150  GMAC->GMAC_HRT = 0;
151 
152  //Initialize buffer descriptors
153  sam4eEthInitBufferDesc(interface);
154 
155  //Clear transmit status register
156  GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
157  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
158  //Clear receive status register
159  GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
160 
161  //First disable all GMAC interrupts
162  GMAC->GMAC_IDR = 0xFFFFFFFF;
163  //Only the desired ones are enabled
164  GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
165  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
166 
167  //Read GMAC ISR register to clear any pending interrupt
168  status = GMAC->GMAC_ISR;
169 
170  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
171  NVIC_SetPriorityGrouping(SAM4E_ETH_IRQ_PRIORITY_GROUPING);
172 
173  //Configure GMAC interrupt priority
174  NVIC_SetPriority(GMAC_IRQn, NVIC_EncodePriority(SAM4E_ETH_IRQ_PRIORITY_GROUPING,
176 
177  //Enable the GMAC to transmit and receive data
178  GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
179 
180  //Accept any packets from the upper layer
181  osSetEvent(&interface->nicTxEvent);
182 
183  //Successful initialization
184  return NO_ERROR;
185 }
186 
187 
188 //SAM4E-EK or SAM4E-Xplained-Pro evaluation board?
189 #if defined(USE_SAM4E_EK) || defined(USE_SAM4E_XPLAINED_PRO)
190 
191 /**
192  * @brief GPIO configuration
193  * @param[in] interface Underlying network interface
194  **/
195 
196 void sam4eEthInitGpio(NetInterface *interface)
197 {
198  //Enable PIO peripheral clock
199  PMC->PMC_PCER0 = (1 << ID_PIOD);
200 
201  //Disable pull-up resistors on MII pins
202  PIOD->PIO_PUDR = GMAC_MII_MASK;
203  //Disable interrupts-on-change
204  PIOD->PIO_IDR = GMAC_MII_MASK;
205  //Assign MII pins to peripheral A function
206  PIOD->PIO_ABCDSR[0] &= ~GMAC_MII_MASK;
207  PIOD->PIO_ABCDSR[1] &= ~GMAC_MII_MASK;
208  //Disable the PIO from controlling the corresponding pins
209  PIOD->PIO_PDR = GMAC_MII_MASK;
210 
211  //Select MII operation mode
212  GMAC->GMAC_UR = GMAC_UR_RMIIMII;
213 }
214 
215 #endif
216 
217 
218 /**
219  * @brief Initialize buffer descriptors
220  * @param[in] interface Underlying network interface
221  **/
222 
224 {
225  uint_t i;
226  uint32_t address;
227 
228  //Initialize TX buffer descriptors
229  for(i = 0; i < SAM4E_ETH_TX_BUFFER_COUNT; i++)
230  {
231  //Calculate the address of the current TX buffer
232  address = (uint32_t) txBuffer[i];
233  //Write the address to the descriptor entry
234  txBufferDesc[i].address = address;
235  //Initialize status field
236  txBufferDesc[i].status = GMAC_TX_USED;
237  }
238 
239  //Mark the last descriptor entry with the wrap flag
240  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
241  //Initialize TX buffer index
242  txBufferIndex = 0;
243 
244  //Initialize RX buffer descriptors
245  for(i = 0; i < SAM4E_ETH_RX_BUFFER_COUNT; i++)
246  {
247  //Calculate the address of the current RX buffer
248  address = (uint32_t) rxBuffer[i];
249  //Write the address to the descriptor entry
250  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
251  //Clear status field
252  rxBufferDesc[i].status = 0;
253  }
254 
255  //Mark the last descriptor entry with the wrap flag
256  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
257  //Initialize RX buffer index
258  rxBufferIndex = 0;
259 
260  //Start location of the TX descriptor list
261  GMAC->GMAC_TBQB = (uint32_t) txBufferDesc;
262  //Start location of the RX descriptor list
263  GMAC->GMAC_RBQB = (uint32_t) rxBufferDesc;
264 }
265 
266 
267 /**
268  * @brief SAM4E Ethernet MAC timer handler
269  *
270  * This routine is periodically called by the TCP/IP stack to
271  * handle periodic operations such as polling the link state
272  *
273  * @param[in] interface Underlying network interface
274  **/
275 
276 void sam4eEthTick(NetInterface *interface)
277 {
278  //Handle periodic operations
279  interface->phyDriver->tick(interface);
280 }
281 
282 
283 /**
284  * @brief Enable interrupts
285  * @param[in] interface Underlying network interface
286  **/
287 
289 {
290  //Enable Ethernet MAC interrupts
291  NVIC_EnableIRQ(GMAC_IRQn);
292  //Enable Ethernet PHY interrupts
293  interface->phyDriver->enableIrq(interface);
294 }
295 
296 
297 /**
298  * @brief Disable interrupts
299  * @param[in] interface Underlying network interface
300  **/
301 
303 {
304  //Disable Ethernet MAC interrupts
305  NVIC_DisableIRQ(GMAC_IRQn);
306  //Disable Ethernet PHY interrupts
307  interface->phyDriver->disableIrq(interface);
308 }
309 
310 
311 /**
312  * @brief SAM4E Ethernet MAC interrupt service routine
313  **/
314 
315 void GMAC_Handler(void)
316 {
317  bool_t flag;
318  volatile uint32_t isr;
319  volatile uint32_t tsr;
320  volatile uint32_t rsr;
321 
322  //Enter interrupt service routine
323  osEnterIsr();
324 
325  //This flag will be set if a higher priority task must be woken
326  flag = FALSE;
327 
328  //Each time the software reads GMAC_ISR, it has to check the
329  //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
330  isr = GMAC->GMAC_ISR;
331  tsr = GMAC->GMAC_TSR;
332  rsr = GMAC->GMAC_RSR;
333 
334  //A packet has been transmitted?
335  if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
336  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
337  {
338  //Only clear TSR flags that are currently set
339  GMAC->GMAC_TSR = tsr;
340 
341  //Check whether the TX buffer is available for writing
342  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
343  {
344  //Notify the TCP/IP stack that the transmitter is ready to send
345  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
346  }
347  }
348 
349  //A packet has been received?
350  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
351  {
352  //Set event flag
353  nicDriverInterface->nicEvent = TRUE;
354  //Notify the TCP/IP stack of the event
355  flag |= osSetEventFromIsr(&netEvent);
356  }
357 
358  //Leave interrupt service routine
359  osExitIsr(flag);
360 }
361 
362 
363 /**
364  * @brief SAM4E Ethernet MAC event handler
365  * @param[in] interface Underlying network interface
366  **/
367 
369 {
370  error_t error;
371  uint32_t rsr;
372 
373  //Read receive status
374  rsr = GMAC->GMAC_RSR;
375 
376  //Packet received?
377  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
378  {
379  //Only clear RSR flags that are currently set
380  GMAC->GMAC_RSR = rsr;
381 
382  //Process all pending packets
383  do
384  {
385  //Read incoming packet
386  error = sam4eEthReceivePacket(interface);
387 
388  //No more data in the receive buffer?
389  } while(error != ERROR_BUFFER_EMPTY);
390  }
391 }
392 
393 
394 /**
395  * @brief Send a packet
396  * @param[in] interface Underlying network interface
397  * @param[in] buffer Multi-part buffer containing the data to send
398  * @param[in] offset Offset to the first data byte
399  * @return Error code
400  **/
401 
403  const NetBuffer *buffer, size_t offset)
404 {
405  size_t length;
406 
407  //Retrieve the length of the packet
408  length = netBufferGetLength(buffer) - offset;
409 
410  //Check the frame length
412  {
413  //The transmitter can accept another packet
414  osSetEvent(&interface->nicTxEvent);
415  //Report an error
416  return ERROR_INVALID_LENGTH;
417  }
418 
419  //Make sure the current buffer is available for writing
420  if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
421  return ERROR_FAILURE;
422 
423  //Copy user data to the transmit buffer
424  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
425 
426  //Set the necessary flags in the descriptor entry
427  if(txBufferIndex < (SAM4E_ETH_TX_BUFFER_COUNT - 1))
428  {
429  //Write the status word
430  txBufferDesc[txBufferIndex].status =
432 
433  //Point to the next buffer
434  txBufferIndex++;
435  }
436  else
437  {
438  //Write the status word
439  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
441 
442  //Wrap around
443  txBufferIndex = 0;
444  }
445 
446  //Set the TSTART bit to initiate transmission
447  GMAC->GMAC_NCR |= GMAC_NCR_TSTART;
448 
449  //Check whether the next buffer is available for writing
450  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
451  {
452  //The transmitter can accept another packet
453  osSetEvent(&interface->nicTxEvent);
454  }
455 
456  //Successful processing
457  return NO_ERROR;
458 }
459 
460 
461 /**
462  * @brief Receive a packet
463  * @param[in] interface Underlying network interface
464  * @return Error code
465  **/
466 
468 {
469  static uint8_t temp[ETH_MAX_FRAME_SIZE];
470  error_t error;
471  uint_t i;
472  uint_t j;
473  uint_t sofIndex;
474  uint_t eofIndex;
475  size_t n;
476  size_t size;
477  size_t length;
478 
479  //Initialize SOF and EOF indices
480  sofIndex = UINT_MAX;
481  eofIndex = UINT_MAX;
482 
483  //Search for SOF and EOF flags
484  for(i = 0; i < SAM4E_ETH_RX_BUFFER_COUNT; i++)
485  {
486  //Point to the current entry
487  j = rxBufferIndex + i;
488 
489  //Wrap around to the beginning of the buffer if necessary
492 
493  //No more entries to process?
494  if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
495  {
496  //Stop processing
497  break;
498  }
499  //A valid SOF has been found?
500  if(rxBufferDesc[j].status & GMAC_RX_SOF)
501  {
502  //Save the position of the SOF
503  sofIndex = i;
504  }
505  //A valid EOF has been found?
506  if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
507  {
508  //Save the position of the EOF
509  eofIndex = i;
510  //Retrieve the length of the frame
511  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
512  //Limit the number of data to read
513  size = MIN(size, ETH_MAX_FRAME_SIZE);
514  //Stop processing since we have reached the end of the frame
515  break;
516  }
517  }
518 
519  //Determine the number of entries to process
520  if(eofIndex != UINT_MAX)
521  j = eofIndex + 1;
522  else if(sofIndex != UINT_MAX)
523  j = sofIndex;
524  else
525  j = i;
526 
527  //Total number of bytes that have been copied from the receive buffer
528  length = 0;
529 
530  //Process incoming frame
531  for(i = 0; i < j; i++)
532  {
533  //Any data to copy from current buffer?
534  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
535  {
536  //Calculate the number of bytes to read at a time
537  n = MIN(size, SAM4E_ETH_RX_BUFFER_SIZE);
538  //Copy data from receive buffer
539  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
540  //Update byte counters
541  length += n;
542  size -= n;
543  }
544 
545  //Mark the current buffer as free
546  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
547 
548  //Point to the following entry
549  rxBufferIndex++;
550 
551  //Wrap around to the beginning of the buffer if necessary
552  if(rxBufferIndex >= SAM4E_ETH_RX_BUFFER_COUNT)
553  rxBufferIndex = 0;
554  }
555 
556  //Any packet to process?
557  if(length > 0)
558  {
559  //Pass the packet to the upper layer
560  nicProcessPacket(interface, temp, length);
561  //Valid packet received
562  error = NO_ERROR;
563  }
564  else
565  {
566  //No more data in the receive buffer
567  error = ERROR_BUFFER_EMPTY;
568  }
569 
570  //Return status code
571  return error;
572 }
573 
574 
575 /**
576  * @brief Configure MAC address filtering
577  * @param[in] interface Underlying network interface
578  * @return Error code
579  **/
580 
582 {
583  uint_t i;
584  uint_t k;
585  uint8_t *p;
586  uint32_t hashTable[2];
587  MacFilterEntry *entry;
588 
589  //Debug message
590  TRACE_DEBUG("Updating SAM4E hash table...\r\n");
591 
592  //Clear hash table
593  hashTable[0] = 0;
594  hashTable[1] = 0;
595 
596  //The MAC address filter contains the list of MAC addresses to accept
597  //when receiving an Ethernet frame
598  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
599  {
600  //Point to the current entry
601  entry = &interface->macAddrFilter[i];
602 
603  //Valid entry?
604  if(entry->refCount > 0)
605  {
606  //Point to the MAC address
607  p = entry->addr.b;
608 
609  //Apply the hash function
610  k = (p[0] >> 6) ^ p[0];
611  k ^= (p[1] >> 4) ^ (p[1] << 2);
612  k ^= (p[2] >> 2) ^ (p[2] << 4);
613  k ^= (p[3] >> 6) ^ p[3];
614  k ^= (p[4] >> 4) ^ (p[4] << 2);
615  k ^= (p[5] >> 2) ^ (p[5] << 4);
616 
617  //The hash value is reduced to a 6-bit index
618  k &= 0x3F;
619 
620  //Update hash table contents
621  hashTable[k / 32] |= (1 << (k % 32));
622  }
623  }
624 
625  //Write the hash table
626  GMAC->GMAC_HRB = hashTable[0];
627  GMAC->GMAC_HRT = hashTable[1];
628 
629  //Debug message
630  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC->GMAC_HRB);
631  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC->GMAC_HRT);
632 
633  //Successful processing
634  return NO_ERROR;
635 }
636 
637 
638 /**
639  * @brief Adjust MAC configuration parameters for proper operation
640  * @param[in] interface Underlying network interface
641  * @return Error code
642  **/
643 
645 {
646  uint32_t config;
647 
648  //Read network configuration register
649  config = GMAC->GMAC_NCFGR;
650 
651  //10BASE-T or 100BASE-TX operation mode?
652  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
653  config |= GMAC_NCFGR_SPD;
654  else
655  config &= ~GMAC_NCFGR_SPD;
656 
657  //Half-duplex or full-duplex mode?
658  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
659  config |= GMAC_NCFGR_FD;
660  else
661  config &= ~GMAC_NCFGR_FD;
662 
663  //Write configuration value back to NCFGR register
664  GMAC->GMAC_NCFGR = config;
665 
666  //Successful processing
667  return NO_ERROR;
668 }
669 
670 
671 /**
672  * @brief Write PHY register
673  * @param[in] phyAddr PHY address
674  * @param[in] regAddr Register address
675  * @param[in] data Register value
676  **/
677 
678 void sam4eEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
679 {
680  uint32_t value;
681 
682  //Set up a write operation
683  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
684  //PHY address
685  value |= GMAC_MAN_PHYA(phyAddr);
686  //Register address
687  value |= GMAC_MAN_REGA(regAddr);
688  //Register value
689  value |= GMAC_MAN_DATA(data);
690 
691  //Start a write operation
692  GMAC->GMAC_MAN = value;
693  //Wait for the write to complete
694  while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
695 }
696 
697 
698 /**
699  * @brief Read PHY register
700  * @param[in] phyAddr PHY address
701  * @param[in] regAddr Register address
702  * @return Register value
703  **/
704 
705 uint16_t sam4eEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
706 {
707  uint32_t value;
708 
709  //Set up a read operation
710  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
711  //PHY address
712  value |= GMAC_MAN_PHYA(phyAddr);
713  //Register address
714  value |= GMAC_MAN_REGA(regAddr);
715 
716  //Start a read operation
717  GMAC->GMAC_MAN = value;
718  //Wait for the read to complete
719  while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
720 
721  //Return PHY register contents
722  return GMAC->GMAC_MAN & GMAC_MAN_DATA_Msk;
723 }
#define GMAC_RX_SOF
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
void sam4eEthEventHandler(NetInterface *interface)
SAM4E Ethernet MAC event handler.
void sam4eEthDisableIrq(NetInterface *interface)
Disable interrupts.
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define GMAC_RX_EOF
Generic error code.
Definition: error.h:43
#define SAM4E_ETH_IRQ_SUB_PRIORITY
#define txBuffer
#define GMAC_TX_USED
#define SAM4E_ETH_RX_BUFFER_COUNT
void GMAC_Handler(void)
SAM4E Ethernet MAC interrupt service routine.
void sam4eEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define GMAC_TX_WRAP
#define SAM4E_ETH_IRQ_GROUP_PRIORITY
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
error_t sam4eEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define GMAC_MII_MASK
#define GMAC_TX_LAST
#define SAM4E_ETH_RX_BUFFER_SIZE
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
void sam4eEthInitGpio(NetInterface *interface)
SAM4E Ethernet MAC controller.
error_t sam4eEthReceivePacket(NetInterface *interface)
Receive a packet.
const NicDriver sam4eEthDriver
SAM4E Ethernet MAC driver.
NIC driver.
Definition: nic.h:161
error_t sam4eEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void sam4eEthTick(NetInterface *interface)
SAM4E Ethernet MAC timer handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
#define GMAC_RX_OWNERSHIP
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void sam4eEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define SAM4E_ETH_TX_BUFFER_COUNT
#define GMAC_RX_ADDRESS
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define GMAC_RX_WRAP
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
Transmit buffer descriptor.
unsigned int uint_t
Definition: compiler_port.h:43
#define SAM4E_ETH_IRQ_PRIORITY_GROUPING
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
error_t sam4eEthInit(NetInterface *interface)
SAM4E Ethernet MAC initialization.
Receive buffer descriptor.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define osExitIsr(flag)
#define osEnterIsr()
#define GMAC_RX_LENGTH
#define GMAC_TX_LENGTH
void sam4eEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
uint16_t sam4eEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sam4eEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define SAM4E_ETH_TX_BUFFER_SIZE
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98