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31 #ifndef _SAME54_ETH_DRIVER_H
32 #define _SAME54_ETH_DRIVER_H
38 #ifndef SAME54_ETH_TX_BUFFER_COUNT
39 #define SAME54_ETH_TX_BUFFER_COUNT 3
40 #elif (SAME54_ETH_TX_BUFFER_COUNT < 1)
41 #error SAME54_ETH_TX_BUFFER_COUNT parameter is not valid
45 #ifndef SAME54_ETH_TX_BUFFER_SIZE
46 #define SAME54_ETH_TX_BUFFER_SIZE 1536
47 #elif (SAME54_ETH_TX_BUFFER_SIZE != 1536)
48 #error SAME54_ETH_TX_BUFFER_SIZE parameter is not valid
52 #ifndef SAME54_ETH_RX_BUFFER_COUNT
53 #define SAME54_ETH_RX_BUFFER_COUNT 72
54 #elif (SAME54_ETH_RX_BUFFER_COUNT < 12)
55 #error SAME54_ETH_RX_BUFFER_COUNT parameter is not valid
59 #ifndef SAME54_ETH_RX_BUFFER_SIZE
60 #define SAME54_ETH_RX_BUFFER_SIZE 128
61 #elif (SAME54_ETH_RX_BUFFER_SIZE != 128)
62 #error SAME54_ETH_RX_BUFFER_SIZE parameter is not valid
66 #ifndef SAME54_ETH_IRQ_PRIORITY_GROUPING
67 #define SAME54_ETH_IRQ_PRIORITY_GROUPING 4
68 #elif (SAME54_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error SAME54_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73 #ifndef SAME54_ETH_IRQ_GROUP_PRIORITY
74 #define SAME54_ETH_IRQ_GROUP_PRIORITY 6
75 #elif (SAME54_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error SAME54_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80 #ifndef SAME54_ETH_IRQ_SUB_PRIORITY
81 #define SAME54_ETH_IRQ_SUB_PRIORITY 0
82 #elif (SAME54_ETH_IRQ_SUB_PRIORITY < 0)
83 #error SAME54_ETH_IRQ_SUB_PRIORITY parameter is not valid
87 #define GMAC_TX_USED 0x80000000
88 #define GMAC_TX_WRAP 0x40000000
89 #define GMAC_TX_RLE_ERROR 0x20000000
90 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
91 #define GMAC_TX_AHB_ERROR 0x08000000
92 #define GMAC_TX_LATE_COL_ERROR 0x04000000
93 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
94 #define GMAC_TX_NO_CRC 0x00010000
95 #define GMAC_TX_LAST 0x00008000
96 #define GMAC_TX_LENGTH 0x00003FFF
99 #define GMAC_RX_ADDRESS 0xFFFFFFFC
100 #define GMAC_RX_WRAP 0x00000002
101 #define GMAC_RX_OWNERSHIP 0x00000001
102 #define GMAC_RX_BROADCAST 0x80000000
103 #define GMAC_RX_MULTICAST_HASH 0x40000000
104 #define GMAC_RX_UNICAST_HASH 0x20000000
105 #define GMAC_RX_SAR 0x08000000
106 #define GMAC_RX_SAR_MASK 0x06000000
107 #define GMAC_RX_TYPE_ID 0x01000000
108 #define GMAC_RX_SNAP 0x01000000
109 #define GMAC_RX_TYPE_ID_MASK 0x00C00000
110 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
111 #define GMAC_RX_VLAN_TAG 0x00200000
112 #define GMAC_RX_PRIORITY_TAG 0x00100000
113 #define GMAC_RX_VLAN_PRIORITY 0x000E0000
114 #define GMAC_RX_CFI 0x00010000
115 #define GMAC_RX_EOF 0x00008000
116 #define GMAC_RX_SOF 0x00004000
117 #define GMAC_RX_LENGTH_MSB 0x00002000
118 #define GMAC_RX_BAD_FCS 0x00002000
119 #define GMAC_RX_LENGTH 0x00001FFF
void same54EthTick(NetInterface *interface)
SAME54 Ethernet MAC timer handler.
Transmit buffer descriptor.
Structure describing a buffer that spans multiple chunks.
void same54EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint16_t same54EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Receive buffer descriptor.
error_t same54EthReceivePacket(NetInterface *interface)
Receive a packet.
void same54EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t same54EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void same54EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void same54EthEventHandler(NetInterface *interface)
SAME54 Ethernet MAC event handler.
void same54EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t same54EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Network interface controller abstraction layer.
error_t same54EthInit(NetInterface *interface)
SAME54 Ethernet MAC initialization.
error_t same54EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void same54EthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver same54EthDriver
SAME54 Ethernet MAC driver.