same54_eth_driver.c
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1 /**
2  * @file same54_eth_driver.c
3  * @brief SAME54 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "same54.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
48 //RX buffer
49 #pragma data_alignment = 8
51 //TX buffer descriptors
52 #pragma data_alignment = 4
54 //RX buffer descriptors
55 #pragma data_alignment = 4
57 
58 //Keil MDK-ARM or GCC compiler?
59 #else
60 
61 //TX buffer
63  __attribute__((aligned(8)));
64 //RX buffer
66  __attribute__((aligned(8)));
67 //TX buffer descriptors
69  __attribute__((aligned(4)));
70 //RX buffer descriptors
72  __attribute__((aligned(4)));
73 
74 #endif
75 
76 //TX buffer index
77 static uint_t txBufferIndex;
78 //RX buffer index
79 static uint_t rxBufferIndex;
80 
81 
82 /**
83  * @brief SAME54 Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  FALSE
104 };
105 
106 
107 /**
108  * @brief SAME54 Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116  volatile uint32_t status;
117 
118  //Debug message
119  TRACE_INFO("Initializing SAME54 Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable GMAC bus clocks (CLK_GMAC_APB and CLK_GMAC_AHB)
125  MCLK->APBCMASK.bit.GMAC_ = 1;
126  MCLK->AHBMASK.bit.GMAC_ = 1;
127 
128  //GPIO configuration
129  same54EthInitGpio(interface);
130 
131  //Configure MDC clock speed
132  GMAC->NCFGR.reg = GMAC_NCFGR_CLK(5);
133  //Enable management port (MDC and MDIO)
134  GMAC->NCR.reg |= GMAC_NCR_MPE;
135 
136  //PHY transceiver initialization
137  error = interface->phyDriver->init(interface);
138  //Failed to initialize PHY transceiver?
139  if(error)
140  return error;
141 
142  //Set the MAC address
143  GMAC->Sa[0].SAB.reg = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
144  GMAC->Sa[0].SAT.reg = interface->macAddr.w[2];
145 
146  //Configure the receive filter
147  GMAC->NCFGR.reg |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
148 
149  //Initialize hash table
150  GMAC->HRB.reg = 0;
151  GMAC->HRT.reg = 0;
152 
153  //Initialize buffer descriptors
154  same54EthInitBufferDesc(interface);
155 
156  //Clear transmit status register
157  GMAC->TSR.reg = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
158  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
159  //Clear receive status register
160  GMAC->RSR.reg = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
161 
162  //First disable all GMAC interrupts
163  GMAC->IDR.reg = 0xFFFFFFFF;
164  //Only the desired ones are enabled
165  GMAC->IER.reg = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
166  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
167 
168  //Read GMAC ISR register to clear any pending interrupt
169  status = GMAC->ISR.reg;
170 
171  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
172  NVIC_SetPriorityGrouping(SAME54_ETH_IRQ_PRIORITY_GROUPING);
173 
174  //Configure GMAC interrupt priority
175  NVIC_SetPriority(GMAC_IRQn, NVIC_EncodePriority(SAME54_ETH_IRQ_PRIORITY_GROUPING,
177 
178  //Enable the GMAC to transmit and receive data
179  GMAC->NCR.reg |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
180 
181  //Accept any packets from the upper layer
182  osSetEvent(&interface->nicTxEvent);
183 
184  //Successful initialization
185  return NO_ERROR;
186 }
187 
188 
189 //SAME54-Xplained-Pro evaluation board?
190 #if defined(USE_SAME54_XPLAINED_PRO)
191 
192 /**
193  * @brief GPIO configuration
194  * @param[in] interface Underlying network interface
195  **/
196 
197 void same54EthInitGpio(NetInterface *interface)
198 {
199  //Enable PORT bus clock (CLK_PORT_APB)
200  MCLK->APBBMASK.bit.PORT_ = 1;
201 
202  //Configure GRX1 (PA12)
203  PORT->Group[0].PINCFG[12].bit.PMUXEN = 1;
204  PORT->Group[0].PMUX[6].bit.PMUXE = MUX_PA12L_GMAC_GRX1;
205 
206  //Configure GRX0 (PA13)
207  PORT->Group[0].PINCFG[13].bit.PMUXEN = 1;
208  PORT->Group[0].PMUX[6].bit.PMUXO = MUX_PA13L_GMAC_GRX0;
209 
210  //Configure GTXCK (PA14)
211  PORT->Group[0].PINCFG[14].bit.PMUXEN = 1;
212  PORT->Group[0].PMUX[7].bit.PMUXE = MUX_PA14L_GMAC_GTXCK;
213 
214  //Configure GRXER (PA15)
215  PORT->Group[0].PINCFG[15].bit.PMUXEN = 1;
216  PORT->Group[0].PMUX[7].bit.PMUXO = MUX_PA15L_GMAC_GRXER;
217 
218  //Configure GTXEN (PA17)
219  PORT->Group[0].PINCFG[17].bit.DRVSTR = 1;
220  PORT->Group[0].PINCFG[17].bit.PMUXEN = 1;
221  PORT->Group[0].PMUX[8].bit.PMUXO = MUX_PA17L_GMAC_GTXEN;
222 
223  //Configure GTX0 (PA18)
224  PORT->Group[0].PINCFG[18].bit.DRVSTR = 1;
225  PORT->Group[0].PINCFG[18].bit.PMUXEN = 1;
226  PORT->Group[0].PMUX[9].bit.PMUXE = MUX_PA18L_GMAC_GTX0;
227 
228  //Configure GTX1 (PA19)
229  PORT->Group[0].PINCFG[19].bit.DRVSTR = 1;
230  PORT->Group[0].PINCFG[19].bit.PMUXEN = 1;
231  PORT->Group[0].PMUX[9].bit.PMUXO = MUX_PA19L_GMAC_GTX1;
232 
233  //Configure GMDC (PC11)
234  PORT->Group[2].PINCFG[11].bit.PMUXEN = 1;
235  PORT->Group[2].PMUX[5].bit.PMUXO = MUX_PC11L_GMAC_GMDC;
236 
237  //Configure GMDIO (PC12)
238  PORT->Group[2].PINCFG[12].bit.PMUXEN = 1;
239  PORT->Group[2].PMUX[6].bit.PMUXE = MUX_PC12L_GMAC_GMDIO;
240 
241  //Configure GRXDV (PC20)
242  PORT->Group[2].PINCFG[20].bit.PMUXEN = 1;
243  PORT->Group[2].PMUX[10].bit.PMUXE = MUX_PC20L_GMAC_GRXDV;
244 
245  //Select RMII operation mode
246  GMAC->UR.bit.MII = 0;
247 
248  //Configure PHY_RESET (PC21) as an output
249  PORT->Group[2].DIRSET.reg = PORT_PC21;
250 
251  //Reset PHY transceiver
252  PORT->Group[2].OUTCLR.reg = PORT_PC21;
253  sleep(10);
254 
255  //Take the PHY transceiver out of reset
256  PORT->Group[2].OUTSET.reg = PORT_PC21;
257  sleep(10);
258 }
259 
260 #endif
261 
262 
263 /**
264  * @brief Initialize buffer descriptors
265  * @param[in] interface Underlying network interface
266  **/
267 
269 {
270  uint_t i;
271  uint32_t address;
272 
273  //Initialize TX buffer descriptors
274  for(i = 0; i < SAME54_ETH_TX_BUFFER_COUNT; i++)
275  {
276  //Calculate the address of the current TX buffer
277  address = (uint32_t) txBuffer[i];
278  //Write the address to the descriptor entry
279  txBufferDesc[i].address = address;
280  //Initialize status field
281  txBufferDesc[i].status = GMAC_TX_USED;
282  }
283 
284  //Mark the last descriptor entry with the wrap flag
285  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
286  //Initialize TX buffer index
287  txBufferIndex = 0;
288 
289  //Initialize RX buffer descriptors
290  for(i = 0; i < SAME54_ETH_RX_BUFFER_COUNT; i++)
291  {
292  //Calculate the address of the current RX buffer
293  address = (uint32_t) rxBuffer[i];
294  //Write the address to the descriptor entry
295  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
296  //Clear status field
297  rxBufferDesc[i].status = 0;
298  }
299 
300  //Mark the last descriptor entry with the wrap flag
301  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
302  //Initialize RX buffer index
303  rxBufferIndex = 0;
304 
305  //Start location of the TX descriptor list
306  GMAC->TBQB.reg = (uint32_t) txBufferDesc;
307  //Start location of the RX descriptor list
308  GMAC->RBQB.reg = (uint32_t) rxBufferDesc;
309 }
310 
311 
312 /**
313  * @brief SAME54 Ethernet MAC timer handler
314  *
315  * This routine is periodically called by the TCP/IP stack to
316  * handle periodic operations such as polling the link state
317  *
318  * @param[in] interface Underlying network interface
319  **/
320 
321 void same54EthTick(NetInterface *interface)
322 {
323  //Handle periodic operations
324  interface->phyDriver->tick(interface);
325 }
326 
327 
328 /**
329  * @brief Enable interrupts
330  * @param[in] interface Underlying network interface
331  **/
332 
334 {
335  //Enable Ethernet MAC interrupts
336  NVIC_EnableIRQ(GMAC_IRQn);
337  //Enable Ethernet PHY interrupts
338  interface->phyDriver->enableIrq(interface);
339 }
340 
341 
342 /**
343  * @brief Disable interrupts
344  * @param[in] interface Underlying network interface
345  **/
346 
348 {
349  //Disable Ethernet MAC interrupts
350  NVIC_DisableIRQ(GMAC_IRQn);
351  //Disable Ethernet PHY interrupts
352  interface->phyDriver->disableIrq(interface);
353 }
354 
355 
356 /**
357  * @brief SAME54 Ethernet MAC interrupt service routine
358  **/
359 
360 void GMAC_Handler(void)
361 {
362  bool_t flag;
363  volatile uint32_t isr;
364  volatile uint32_t tsr;
365  volatile uint32_t rsr;
366 
367  //Enter interrupt service routine
368  osEnterIsr();
369 
370  //This flag will be set if a higher priority task must be woken
371  flag = FALSE;
372 
373  //Each time the software reads GMAC_ISR, it has to check the
374  //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
375  isr = GMAC->ISR.reg;
376  tsr = GMAC->TSR.reg;
377  rsr = GMAC->RSR.reg;
378 
379  //A packet has been transmitted?
380  if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
381  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
382  {
383  //Only clear TSR flags that are currently set
384  GMAC->TSR.reg = tsr;
385 
386  //Check whether the TX buffer is available for writing
387  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
388  {
389  //Notify the TCP/IP stack that the transmitter is ready to send
390  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
391  }
392  }
393 
394  //A packet has been received?
395  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
396  {
397  //Set event flag
398  nicDriverInterface->nicEvent = TRUE;
399  //Notify the TCP/IP stack of the event
400  flag |= osSetEventFromIsr(&netEvent);
401  }
402 
403  //Leave interrupt service routine
404  osExitIsr(flag);
405 }
406 
407 
408 /**
409  * @brief SAME54 Ethernet MAC event handler
410  * @param[in] interface Underlying network interface
411  **/
412 
414 {
415  error_t error;
416  uint32_t rsr;
417 
418  //Read receive status
419  rsr = GMAC->RSR.reg;
420 
421  //Packet received?
422  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
423  {
424  //Only clear RSR flags that are currently set
425  GMAC->RSR.reg = rsr;
426 
427  //Process all pending packets
428  do
429  {
430  //Read incoming packet
431  error = same54EthReceivePacket(interface);
432 
433  //No more data in the receive buffer?
434  } while(error != ERROR_BUFFER_EMPTY);
435  }
436 }
437 
438 
439 /**
440  * @brief Send a packet
441  * @param[in] interface Underlying network interface
442  * @param[in] buffer Multi-part buffer containing the data to send
443  * @param[in] offset Offset to the first data byte
444  * @return Error code
445  **/
446 
448  const NetBuffer *buffer, size_t offset)
449 {
450  size_t length;
451 
452  //Retrieve the length of the packet
453  length = netBufferGetLength(buffer) - offset;
454 
455  //Check the frame length
457  {
458  //The transmitter can accept another packet
459  osSetEvent(&interface->nicTxEvent);
460  //Report an error
461  return ERROR_INVALID_LENGTH;
462  }
463 
464  //Make sure the current buffer is available for writing
465  if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
466  return ERROR_FAILURE;
467 
468  //Copy user data to the transmit buffer
469  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
470 
471  //Set the necessary flags in the descriptor entry
472  if(txBufferIndex < (SAME54_ETH_TX_BUFFER_COUNT - 1))
473  {
474  //Write the status word
475  txBufferDesc[txBufferIndex].status =
477 
478  //Point to the next buffer
479  txBufferIndex++;
480  }
481  else
482  {
483  //Write the status word
484  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
486 
487  //Wrap around
488  txBufferIndex = 0;
489  }
490 
491  //Set the TSTART bit to initiate transmission
492  GMAC->NCR.reg |= GMAC_NCR_TSTART;
493 
494  //Check whether the next buffer is available for writing
495  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
496  {
497  //The transmitter can accept another packet
498  osSetEvent(&interface->nicTxEvent);
499  }
500 
501  //Successful processing
502  return NO_ERROR;
503 }
504 
505 
506 /**
507  * @brief Receive a packet
508  * @param[in] interface Underlying network interface
509  * @return Error code
510  **/
511 
513 {
514  static uint8_t temp[ETH_MAX_FRAME_SIZE];
515  error_t error;
516  uint_t i;
517  uint_t j;
518  uint_t sofIndex;
519  uint_t eofIndex;
520  size_t n;
521  size_t size;
522  size_t length;
523 
524  //Initialize SOF and EOF indices
525  sofIndex = UINT_MAX;
526  eofIndex = UINT_MAX;
527 
528  //Search for SOF and EOF flags
529  for(i = 0; i < SAME54_ETH_RX_BUFFER_COUNT; i++)
530  {
531  //Point to the current entry
532  j = rxBufferIndex + i;
533 
534  //Wrap around to the beginning of the buffer if necessary
537 
538  //No more entries to process?
539  if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
540  {
541  //Stop processing
542  break;
543  }
544  //A valid SOF has been found?
545  if(rxBufferDesc[j].status & GMAC_RX_SOF)
546  {
547  //Save the position of the SOF
548  sofIndex = i;
549  }
550  //A valid EOF has been found?
551  if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
552  {
553  //Save the position of the EOF
554  eofIndex = i;
555  //Retrieve the length of the frame
556  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
557  //Limit the number of data to read
558  size = MIN(size, ETH_MAX_FRAME_SIZE);
559  //Stop processing since we have reached the end of the frame
560  break;
561  }
562  }
563 
564  //Determine the number of entries to process
565  if(eofIndex != UINT_MAX)
566  j = eofIndex + 1;
567  else if(sofIndex != UINT_MAX)
568  j = sofIndex;
569  else
570  j = i;
571 
572  //Total number of bytes that have been copied from the receive buffer
573  length = 0;
574 
575  //Process incoming frame
576  for(i = 0; i < j; i++)
577  {
578  //Any data to copy from current buffer?
579  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
580  {
581  //Calculate the number of bytes to read at a time
583  //Copy data from receive buffer
584  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
585  //Update byte counters
586  length += n;
587  size -= n;
588  }
589 
590  //Mark the current buffer as free
591  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
592 
593  //Point to the following entry
594  rxBufferIndex++;
595 
596  //Wrap around to the beginning of the buffer if necessary
597  if(rxBufferIndex >= SAME54_ETH_RX_BUFFER_COUNT)
598  rxBufferIndex = 0;
599  }
600 
601  //Any packet to process?
602  if(length > 0)
603  {
604  //Pass the packet to the upper layer
605  nicProcessPacket(interface, temp, length);
606  //Valid packet received
607  error = NO_ERROR;
608  }
609  else
610  {
611  //No more data in the receive buffer
612  error = ERROR_BUFFER_EMPTY;
613  }
614 
615  //Return status code
616  return error;
617 }
618 
619 
620 /**
621  * @brief Configure MAC address filtering
622  * @param[in] interface Underlying network interface
623  * @return Error code
624  **/
625 
627 {
628  uint_t i;
629  uint_t k;
630  uint8_t *p;
631  uint32_t hashTable[2];
632  MacFilterEntry *entry;
633 
634  //Debug message
635  TRACE_DEBUG("Updating SAME54 hash table...\r\n");
636 
637  //Clear hash table
638  hashTable[0] = 0;
639  hashTable[1] = 0;
640 
641  //The MAC address filter contains the list of MAC addresses to accept
642  //when receiving an Ethernet frame
643  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
644  {
645  //Point to the current entry
646  entry = &interface->macAddrFilter[i];
647 
648  //Valid entry?
649  if(entry->refCount > 0)
650  {
651  //Point to the MAC address
652  p = entry->addr.b;
653 
654  //Apply the hash function
655  k = (p[0] >> 6) ^ p[0];
656  k ^= (p[1] >> 4) ^ (p[1] << 2);
657  k ^= (p[2] >> 2) ^ (p[2] << 4);
658  k ^= (p[3] >> 6) ^ p[3];
659  k ^= (p[4] >> 4) ^ (p[4] << 2);
660  k ^= (p[5] >> 2) ^ (p[5] << 4);
661 
662  //The hash value is reduced to a 6-bit index
663  k &= 0x3F;
664 
665  //Update hash table contents
666  hashTable[k / 32] |= (1 << (k % 32));
667  }
668  }
669 
670  //Write the hash table
671  GMAC->HRB.reg = hashTable[0];
672  GMAC->HRT.reg = hashTable[1];
673 
674  //Debug message
675  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC->HRB.reg);
676  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC->HRT.reg);
677 
678  //Successful processing
679  return NO_ERROR;
680 }
681 
682 
683 /**
684  * @brief Adjust MAC configuration parameters for proper operation
685  * @param[in] interface Underlying network interface
686  * @return Error code
687  **/
688 
690 {
691  uint32_t config;
692 
693  //Read network configuration register
694  config = GMAC->NCFGR.reg;
695 
696  //10BASE-T or 100BASE-TX operation mode?
697  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
698  config |= GMAC_NCFGR_SPD;
699  else
700  config &= ~GMAC_NCFGR_SPD;
701 
702  //Half-duplex or full-duplex mode?
703  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
704  config |= GMAC_NCFGR_FD;
705  else
706  config &= ~GMAC_NCFGR_FD;
707 
708  //Write configuration value back to NCFGR register
709  GMAC->NCFGR.reg = config;
710 
711  //Successful processing
712  return NO_ERROR;
713 }
714 
715 
716 /**
717  * @brief Write PHY register
718  * @param[in] phyAddr PHY address
719  * @param[in] regAddr Register address
720  * @param[in] data Register value
721  **/
722 
723 void same54EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
724 {
725  uint32_t value;
726 
727  //Set up a write operation
728  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
729  //PHY address
730  value |= GMAC_MAN_PHYA(phyAddr);
731  //Register address
732  value |= GMAC_MAN_REGA(regAddr);
733  //Register value
734  value |= GMAC_MAN_DATA(data);
735 
736  //Start a write operation
737  GMAC->MAN.reg = value;
738  //Wait for the write to complete
739  while(!(GMAC->NSR.reg & GMAC_NSR_IDLE));
740 }
741 
742 
743 /**
744  * @brief Read PHY register
745  * @param[in] phyAddr PHY address
746  * @param[in] regAddr Register address
747  * @return Register value
748  **/
749 
750 uint16_t same54EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
751 {
752  uint32_t value;
753 
754  //Set up a read operation
755  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
756  //PHY address
757  value |= GMAC_MAN_PHYA(phyAddr);
758  //Register address
759  value |= GMAC_MAN_REGA(regAddr);
760 
761  //Start a read operation
762  GMAC->MAN.reg = value;
763  //Wait for the read to complete
764  while(!(GMAC->NSR.reg & GMAC_NSR_IDLE));
765 
766  //Return PHY register contents
767  return GMAC->MAN.reg & GMAC_MAN_DATA_Msk;
768 }
#define SAME54_ETH_IRQ_PRIORITY_GROUPING
error_t same54EthReceivePacket(NetInterface *interface)
Receive a packet.
#define GMAC_RX_SOF
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
error_t same54EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define SAME54_ETH_RX_BUFFER_SIZE
uint16_t same54EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define SAME54_ETH_TX_BUFFER_SIZE
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define GMAC_RX_EOF
Generic error code.
Definition: error.h:43
#define txBuffer
void same54EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define GMAC_TX_USED
#define sleep(delay)
Definition: os_port.h:126
void same54EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define SAME54_ETH_IRQ_SUB_PRIORITY
#define GMAC_TX_WRAP
#define SAME54_ETH_IRQ_GROUP_PRIORITY
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
error_t same54EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void same54EthTick(NetInterface *interface)
SAME54 Ethernet MAC timer handler.
#define SAME54_ETH_RX_BUFFER_COUNT
void same54EthInitGpio(NetInterface *interface)
SAME54 Ethernet MAC controller.
void same54EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define GMAC_TX_LAST
const NicDriver same54EthDriver
SAME54 Ethernet MAC driver.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
#define GMAC_RX_OWNERSHIP
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void GMAC_Handler(void)
SAME54 Ethernet MAC interrupt service routine.
#define GMAC_RX_ADDRESS
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define GMAC_RX_WRAP
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
Transmit buffer descriptor.
unsigned int uint_t
Definition: compiler_port.h:43
error_t same54EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void same54EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
Receive buffer descriptor.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
error_t same54EthInit(NetInterface *interface)
SAME54 Ethernet MAC initialization.
#define osExitIsr(flag)
#define osEnterIsr()
#define GMAC_RX_LENGTH
#define GMAC_TX_LENGTH
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define SAME54_ETH_TX_BUFFER_COUNT
#define FALSE
Definition: os_port.h:44
void same54EthEventHandler(NetInterface *interface)
SAME54 Ethernet MAC event handler.
int bool_t
Definition: compiler_port.h:47
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98