stm32f1xx_eth_driver.h
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1 /**
2  * @file stm32f1xx_eth_driver.h
3  * @brief STM32F1 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _STM32F1XX_ETH_DRIVER_H
32 #define _STM32F1XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32F1XX_ETH_TX_BUFFER_COUNT
39  #define STM32F1XX_ETH_TX_BUFFER_COUNT 2
40 #elif (STM32F1XX_ETH_TX_BUFFER_COUNT < 1)
41  #error STM32F1XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32F1XX_ETH_TX_BUFFER_SIZE
46  #define STM32F1XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (STM32F1XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error STM32F1XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32F1XX_ETH_RX_BUFFER_COUNT
53  #define STM32F1XX_ETH_RX_BUFFER_COUNT 4
54 #elif (STM32F1XX_ETH_RX_BUFFER_COUNT < 1)
55  #error STM32F1XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32F1XX_ETH_RX_BUFFER_SIZE
60  #define STM32F1XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (STM32F1XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error STM32F1XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef STM32F1XX_ETH_IRQ_PRIORITY_GROUPING
67  #define STM32F1XX_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (STM32F1XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error STM32F1XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef STM32F1XX_ETH_IRQ_GROUP_PRIORITY
74  #define STM32F1XX_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (STM32F1XX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error STM32F1XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef STM32F1XX_ETH_IRQ_SUB_PRIORITY
81  #define STM32F1XX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (STM32F1XX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error STM32F1XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Transmit DMA descriptor flags
87 #define ETH_TDES0_OWN 0x80000000
88 #define ETH_TDES0_IC 0x40000000
89 #define ETH_TDES0_LS 0x20000000
90 #define ETH_TDES0_FS 0x10000000
91 #define ETH_TDES0_DC 0x08000000
92 #define ETH_TDES0_DP 0x04000000
93 #define ETH_TDES0_TTSE 0x02000000
94 #define ETH_TDES0_CIC 0x00C00000
95 #define ETH_TDES0_TER 0x00200000
96 #define ETH_TDES0_TCH 0x00100000
97 #define ETH_TDES0_TTSS 0x00020000
98 #define ETH_TDES0_IHE 0x00010000
99 #define ETH_TDES0_ES 0x00008000
100 #define ETH_TDES0_JT 0x00004000
101 #define ETH_TDES0_FF 0x00002000
102 #define ETH_TDES0_IPE 0x00001000
103 #define ETH_TDES0_LCA 0x00000800
104 #define ETH_TDES0_NC 0x00000400
105 #define ETH_TDES0_LCO 0x00000200
106 #define ETH_TDES0_EC 0x00000100
107 #define ETH_TDES0_VF 0x00000080
108 #define ETH_TDES0_CC 0x00000078
109 #define ETH_TDES0_ED 0x00000004
110 #define ETH_TDES0_UF 0x00000002
111 #define ETH_TDES0_DB 0x00000001
112 #define ETH_TDES1_TBS2 0x1FFF0000
113 #define ETH_TDES1_TBS1 0x00001FFF
114 #define ETH_TDES2_TBAP1 0xFFFFFFFF
115 #define ETH_TDES3_TBAP2 0xFFFFFFFF
116 
117 //Receive DMA descriptor flags
118 #define ETH_RDES0_OWN 0x80000000
119 #define ETH_RDES0_AFM 0x40000000
120 #define ETH_RDES0_FL 0x3FFF0000
121 #define ETH_RDES0_ES 0x00008000
122 #define ETH_RDES0_DE 0x00004000
123 #define ETH_RDES0_SAF 0x00002000
124 #define ETH_RDES0_LE 0x00001000
125 #define ETH_RDES0_OE 0x00000800
126 #define ETH_RDES0_VLAN 0x00000400
127 #define ETH_RDES0_FS 0x00000200
128 #define ETH_RDES0_LS 0x00000100
129 #define ETH_RDES0_IPHCE 0x00000080
130 #define ETH_RDES0_LCO 0x00000040
131 #define ETH_RDES0_FT 0x00000020
132 #define ETH_RDES0_RWT 0x00000010
133 #define ETH_RDES0_RE 0x00000008
134 #define ETH_RDES0_DBE 0x00000004
135 #define ETH_RDES0_CE 0x00000002
136 #define ETH_RDES0_PCE 0x00000001
137 #define ETH_RDES1_DIC 0x80000000
138 #define ETH_RDES1_RBS2 0x1FFF0000
139 #define ETH_RDES1_RER 0x00008000
140 #define ETH_RDES1_RCH 0x00004000
141 #define ETH_RDES1_RBS1 0x00001FFF
142 #define ETH_RDES2_RBAP1 0xFFFFFFFF
143 #define ETH_RDES3_RBAP2 0xFFFFFFFF
144 
145 //C++ guard
146 #ifdef __cplusplus
147  extern "C" {
148 #endif
149 
150 
151 /**
152  * @brief Transmit DMA descriptor
153  **/
154 
155 typedef struct
156 {
157  uint32_t tdes0;
158  uint32_t tdes1;
159  uint32_t tdes2;
160  uint32_t tdes3;
162 
163 
164 /**
165  * @brief Receive DMA descriptor
166  **/
167 
168 typedef struct
169 {
170  uint32_t rdes0;
171  uint32_t rdes1;
172  uint32_t rdes2;
173  uint32_t rdes3;
175 
176 
177 //STM32F1 Ethernet MAC driver
178 extern const NicDriver stm32f1xxEthDriver;
179 
180 //STM32F1 Ethernet MAC related functions
182 void stm32f1xxEthInitGpio(NetInterface *interface);
183 void stm32f1xxEthInitDmaDesc(NetInterface *interface);
184 
185 void stm32f1xxEthTick(NetInterface *interface);
186 
187 void stm32f1xxEthEnableIrq(NetInterface *interface);
188 void stm32f1xxEthDisableIrq(NetInterface *interface);
189 void stm32f1xxEthEventHandler(NetInterface *interface);
190 
192  const NetBuffer *buffer, size_t offset);
193 
195 
198 
199 void stm32f1xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
200  uint8_t regAddr, uint16_t data);
201 
202 uint16_t stm32f1xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
203  uint8_t regAddr);
204 
205 uint32_t stm32f1xxEthCalcCrc(const void *data, size_t length);
206 
207 //C++ guard
208 #ifdef __cplusplus
209  }
210 #endif
211 
212 #endif
error_t stm32f1xxEthReceivePacket(NetInterface *interface)
Receive a packet.
void stm32f1xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void stm32f1xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
const NicDriver stm32f1xxEthDriver
STM32F1 Ethernet MAC driver.
Transmit DMA descriptor.
uint16_t stm32f1xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint8_t opcode
Definition: dns_common.h:172
Receive DMA descriptor.
void stm32f1xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
NIC driver.
Definition: nic.h:179
void stm32f1xxEthTick(NetInterface *interface)
STM32F1 Ethernet MAC timer handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint16_t regAddr
error_t stm32f1xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t
Error codes.
Definition: error.h:42
void stm32f1xxEthInitGpio(NetInterface *interface)
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void stm32f1xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint32_t stm32f1xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t stm32f1xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void stm32f1xxEthEventHandler(NetInterface *interface)
STM32F1 Ethernet MAC event handler.
error_t stm32f1xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint8_t length
Definition: dtls_misc.h:142
Network interface controller abstraction layer.
error_t stm32f1xxEthInit(NetInterface *interface)
STM32F1 Ethernet MAC initialization.