stm32f7xx_eth_driver.h
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1 /**
2  * @file stm32f7xx_eth_driver.h
3  * @brief STM32F7 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _STM32F7XX_ETH_DRIVER_H
32 #define _STM32F7XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32F7XX_ETH_TX_BUFFER_COUNT
39  #define STM32F7XX_ETH_TX_BUFFER_COUNT 3
40 #elif (STM32F7XX_ETH_TX_BUFFER_COUNT < 1)
41  #error STM32F7XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32F7XX_ETH_TX_BUFFER_SIZE
46  #define STM32F7XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (STM32F7XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error STM32F7XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32F7XX_ETH_RX_BUFFER_COUNT
53  #define STM32F7XX_ETH_RX_BUFFER_COUNT 6
54 #elif (STM32F7XX_ETH_RX_BUFFER_COUNT < 1)
55  #error STM32F7XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32F7XX_ETH_RX_BUFFER_SIZE
60  #define STM32F7XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (STM32F7XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error STM32F7XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef STM32F7XX_ETH_IRQ_PRIORITY_GROUPING
67  #define STM32F7XX_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (STM32F7XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error STM32F7XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef STM32F7XX_ETH_IRQ_GROUP_PRIORITY
74  #define STM32F7XX_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (STM32F7XX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error STM32F7XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef STM32F7XX_ETH_IRQ_SUB_PRIORITY
81  #define STM32F7XX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (STM32F7XX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error STM32F7XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Name of the section where to place DMA buffers
87 #ifndef STM32F7XX_ETH_RAM_SECTION
88  #define STM32F7XX_ETH_RAM_SECTION ".ram_no_cache"
89 #endif
90 
91 //ETH_MACCR register
92 #define ETH_MACCR_RESERVED15 0x00008000
93 
94 //Transmit DMA descriptor flags
95 #define ETH_TDES0_OWN 0x80000000
96 #define ETH_TDES0_IC 0x40000000
97 #define ETH_TDES0_LS 0x20000000
98 #define ETH_TDES0_FS 0x10000000
99 #define ETH_TDES0_DC 0x08000000
100 #define ETH_TDES0_DP 0x04000000
101 #define ETH_TDES0_TTSE 0x02000000
102 #define ETH_TDES0_CIC 0x00C00000
103 #define ETH_TDES0_TER 0x00200000
104 #define ETH_TDES0_TCH 0x00100000
105 #define ETH_TDES0_TTSS 0x00020000
106 #define ETH_TDES0_IHE 0x00010000
107 #define ETH_TDES0_ES 0x00008000
108 #define ETH_TDES0_JT 0x00004000
109 #define ETH_TDES0_FF 0x00002000
110 #define ETH_TDES0_IPE 0x00001000
111 #define ETH_TDES0_LCA 0x00000800
112 #define ETH_TDES0_NC 0x00000400
113 #define ETH_TDES0_LCO 0x00000200
114 #define ETH_TDES0_EC 0x00000100
115 #define ETH_TDES0_VF 0x00000080
116 #define ETH_TDES0_CC 0x00000078
117 #define ETH_TDES0_ED 0x00000004
118 #define ETH_TDES0_UF 0x00000002
119 #define ETH_TDES0_DB 0x00000001
120 #define ETH_TDES1_TBS2 0x1FFF0000
121 #define ETH_TDES1_TBS1 0x00001FFF
122 #define ETH_TDES2_TBAP1 0xFFFFFFFF
123 #define ETH_TDES3_TBAP2 0xFFFFFFFF
124 #define ETH_TDES6_TTSL 0xFFFFFFFF
125 #define ETH_TDES7_TTSH 0xFFFFFFFF
126 
127 //Receive DMA descriptor flags
128 #define ETH_RDES0_OWN 0x80000000
129 #define ETH_RDES0_AFM 0x40000000
130 #define ETH_RDES0_FL 0x3FFF0000
131 #define ETH_RDES0_ES 0x00008000
132 #define ETH_RDES0_DE 0x00004000
133 #define ETH_RDES0_SAF 0x00002000
134 #define ETH_RDES0_LE 0x00001000
135 #define ETH_RDES0_OE 0x00000800
136 #define ETH_RDES0_VLAN 0x00000400
137 #define ETH_RDES0_FS 0x00000200
138 #define ETH_RDES0_LS 0x00000100
139 #define ETH_RDES0_IPHCE_TSV 0x00000080
140 #define ETH_RDES0_LCO 0x00000040
141 #define ETH_RDES0_FT 0x00000020
142 #define ETH_RDES0_RWT 0x00000010
143 #define ETH_RDES0_RE 0x00000008
144 #define ETH_RDES0_DBE 0x00000004
145 #define ETH_RDES0_CE 0x00000002
146 #define ETH_RDES0_PCE_ESA 0x00000001
147 #define ETH_RDES1_DIC 0x80000000
148 #define ETH_RDES1_RBS2 0x1FFF0000
149 #define ETH_RDES1_RER 0x00008000
150 #define ETH_RDES1_RCH 0x00004000
151 #define ETH_RDES1_RBS1 0x00001FFF
152 #define ETH_RDES2_RBAP1 0xFFFFFFFF
153 #define ETH_RDES3_RBAP2 0xFFFFFFFF
154 #define ETH_RDES4_PV 0x00002000
155 #define ETH_RDES4_PFT 0x00001000
156 #define ETH_RDES4_PMT 0x00000F00
157 #define ETH_RDES4_IPV6PR 0x00000080
158 #define ETH_RDES4_IPV4PR 0x00000040
159 #define ETH_RDES4_IPCB 0x00000020
160 #define ETH_RDES4_IPPE 0x00000010
161 #define ETH_RDES4_IPHE 0x00000008
162 #define ETH_RDES4_IPPT 0x00000007
163 #define ETH_RDES6_RTSL 0xFFFFFFFF
164 #define ETH_RDES7_RTSH 0xFFFFFFFF
165 
166 //C++ guard
167 #ifdef __cplusplus
168 extern "C" {
169 #endif
170 
171 
172 /**
173  * @brief Enhanced TX DMA descriptor
174  **/
175 
176 typedef struct
177 {
178  uint32_t tdes0;
179  uint32_t tdes1;
180  uint32_t tdes2;
181  uint32_t tdes3;
182  uint32_t tdes4;
183  uint32_t tdes5;
184  uint32_t tdes6;
185  uint32_t tdes7;
187 
188 
189 /**
190  * @brief Enhanced RX DMA descriptor
191  **/
192 
193 typedef struct
194 {
195  uint32_t rdes0;
196  uint32_t rdes1;
197  uint32_t rdes2;
198  uint32_t rdes3;
199  uint32_t rdes4;
200  uint32_t rdes5;
201  uint32_t rdes6;
202  uint32_t rdes7;
204 
205 
206 //STM32F7 Ethernet MAC driver
207 extern const NicDriver stm32f7xxEthDriver;
208 
209 //STM32F7 Ethernet MAC related functions
211 void stm32f7xxEthInitGpio(NetInterface *interface);
212 void stm32f7xxEthInitDmaDesc(NetInterface *interface);
213 
214 void stm32f7xxEthTick(NetInterface *interface);
215 
216 void stm32f7xxEthEnableIrq(NetInterface *interface);
217 void stm32f7xxEthDisableIrq(NetInterface *interface);
218 void stm32f7xxEthEventHandler(NetInterface *interface);
219 
221  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
222 
224 
227 
228 void stm32f7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
229  uint8_t regAddr, uint16_t data);
230 
231 uint16_t stm32f7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
232  uint8_t regAddr);
233 
234 uint32_t stm32f7xxEthCalcCrc(const void *data, size_t length);
235 
236 //C++ guard
237 #ifdef __cplusplus
238 }
239 #endif
240 
241 #endif
error_t stm32f7xxEthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t length
Definition: coap_common.h:190
error_t stm32f7xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint8_t opcode
Definition: dns_common.h:172
uint8_t data[]
Definition: ethernet.h:209
void stm32f7xxEthTick(NetInterface *interface)
STM32F7 Ethernet MAC timer handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void stm32f7xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void stm32f7xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
void stm32f7xxEthEventHandler(NetInterface *interface)
STM32F7 Ethernet MAC event handler.
error_t
Error codes.
Definition: error.h:42
error_t stm32f7xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
void stm32f7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t stm32f7xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
uint16_t stm32f7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
const NicDriver stm32f7xxEthDriver
STM32F7 Ethernet MAC driver.
Enhanced TX DMA descriptor.
uint16_t regAddr
error_t stm32f7xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Network interface controller abstraction layer.
error_t stm32f7xxEthInit(NetInterface *interface)
STM32F7 Ethernet MAC initialization.
void stm32f7xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
Enhanced RX DMA descriptor.
NIC driver.
Definition: nic.h:257
void stm32f7xxEthInitGpio(NetInterface *interface)