stm32h7xx_eth_driver.h
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1 /**
2  * @file stm32h7xx_eth_driver.h
3  * @brief STM32H7 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _STM32H7XX_ETH_DRIVER_H
32 #define _STM32H7XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32H7XX_ETH_TX_BUFFER_COUNT
39  #define STM32H7XX_ETH_TX_BUFFER_COUNT 8
40 #elif (STM32H7XX_ETH_TX_BUFFER_COUNT < 1)
41  #error STM32H7XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32H7XX_ETH_TX_BUFFER_SIZE
46  #define STM32H7XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (STM32H7XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error STM32H7XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32H7XX_ETH_RX_BUFFER_COUNT
53  #define STM32H7XX_ETH_RX_BUFFER_COUNT 8
54 #elif (STM32H7XX_ETH_RX_BUFFER_COUNT < 1)
55  #error STM32H7XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32H7XX_ETH_RX_BUFFER_SIZE
60  #define STM32H7XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (STM32H7XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error STM32H7XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef STM32H7XX_ETH_IRQ_PRIORITY_GROUPING
67  #define STM32H7XX_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (STM32H7XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error STM32H7XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef STM32H7XX_ETH_IRQ_GROUP_PRIORITY
74  #define STM32H7XX_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (STM32H7XX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error STM32H7XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef STM32H7XX_ETH_IRQ_SUB_PRIORITY
81  #define STM32H7XX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (STM32H7XX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error STM32H7XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //MMCRIMR register
87 #ifndef ETH_MMCRIMR_RXLPITRCIM
88  #define ETH_MMCRIMR_RXLPITRCIM 0x08000000
89  #define ETH_MMCRIMR_RXLPIUSCIM 0x04000000
90  #define ETH_MMCRIMR_RXUCGPIM 0x00020000
91  #define ETH_MMCRIMR_RXALGNERPIM 0x00000040
92  #define ETH_MMCRIMR_RXCRCERPIM 0x00000020
93 #endif
94 
95 //MMCTIMR register
96 #ifndef ETH_MMCTIMR_TXLPITRCIM
97  #define ETH_MMCTIMR_TXLPITRCIM 0x08000000
98  #define ETH_MMCTIMR_TXLPIUSCIM 0x04000000
99  #define ETH_MMCTIMR_TXGPKTIM 0x00200000
100  #define ETH_MMCTIMR_TXMCOLGPIM 0x00008000
101  #define ETH_MMCTIMR_TXSCOLGPIM 0x00004000
102 #endif
103 
104 //Transmit normal descriptor (read format)
105 #define ETH_TDES0_BUF1AP 0xFFFFFFFF
106 #define ETH_TDES1_BUF2AP 0xFFFFFFFF
107 #define ETH_TDES2_IOC 0x80000000
108 #define ETH_TDES2_TTSE 0x40000000
109 #define ETH_TDES2_B2L 0x3FFF0000
110 #define ETH_TDES2_VTIR 0x0000C000
111 #define ETH_TDES2_B1L 0x00003FFF
112 #define ETH_TDES3_OWN 0x80000000
113 #define ETH_TDES3_CTXT 0x40000000
114 #define ETH_TDES3_FD 0x20000000
115 #define ETH_TDES3_LD 0x10000000
116 #define ETH_TDES3_CPC 0x0C000000
117 #define ETH_TDES3_SAIC 0x03800000
118 #define ETH_TDES3_THL 0x00780000
119 #define ETH_TDES3_TSE 0x00040000
120 #define ETH_TDES3_CIC 0x00030000
121 #define ETH_TDES3_FL 0x00007FFF
122 
123 //Transmit normal descriptor (write-back format)
124 #define ETH_TDES0_TTSL 0xFFFFFFFF
125 #define ETH_TDES1_TTSH 0xFFFFFFFF
126 #define ETH_TDES3_OWN 0x80000000
127 #define ETH_TDES3_CTXT 0x40000000
128 #define ETH_TDES3_FD 0x20000000
129 #define ETH_TDES3_LD 0x10000000
130 #define ETH_TDES3_TTSS 0x00020000
131 #define ETH_TDES3_ES 0x00008000
132 #define ETH_TDES3_JT 0x00004000
133 #define ETH_TDES3_FF 0x00002000
134 #define ETH_TDES3_PCE 0x00001000
135 #define ETH_TDES3_LOC 0x00000800
136 #define ETH_TDES3_NC 0x00000400
137 #define ETH_TDES3_LC 0x00000200
138 #define ETH_TDES3_EC 0x00000100
139 #define ETH_TDES3_CC 0x000000F0
140 #define ETH_TDES3_ED 0x00000008
141 #define ETH_TDES3_UF 0x00000004
142 #define ETH_TDES3_DB 0x00000002
143 #define ETH_TDES3_IHE 0x00000001
144 
145 //Transmit context descriptor
146 #define ETH_TDES0_TTSL 0xFFFFFFFF
147 #define ETH_TDES1_TTSH 0xFFFFFFFF
148 #define ETH_TDES2_IVT 0xFFFF0000
149 #define ETH_TDES2_MSS 0x00003FFF
150 #define ETH_TDES3_OWN 0x80000000
151 #define ETH_TDES3_CTXT 0x40000000
152 #define ETH_TDES3_OSTC 0x08000000
153 #define ETH_TDES3_TCMSSV 0x04000000
154 #define ETH_TDES3_CDE 0x00800000
155 #define ETH_TDES3_IVLTV 0x00020000
156 #define ETH_TDES3_VLTV 0x00010000
157 #define ETH_TDES3_VT 0x0000FFFF
158 
159 //Receive normal descriptor (read format)
160 #define ETH_RDES0_BUF1AP 0xFFFFFFFF
161 #define ETH_RDES2_BUF2AP 0xFFFFFFFF
162 #define ETH_RDES3_OWN 0x80000000
163 #define ETH_RDES3_IOC 0x40000000
164 #define ETH_RDES3_BUF2V 0x02000000
165 #define ETH_RDES3_BUF1V 0x01000000
166 
167 //Receive normal descriptor (write-back format)
168 #define ETH_RDES0_IVT 0xFFFF0000
169 #define ETH_RDES0_OVT 0x0000FFFF
170 #define ETH_RDES1_OPC 0xFFFF0000
171 #define ETH_RDES1_TD 0x00008000
172 #define ETH_RDES1_TSA 0x00004000
173 #define ETH_RDES1_PV 0x00002000
174 #define ETH_RDES1_PFT 0x00001000
175 #define ETH_RDES1_PMT 0x00000F00
176 #define ETH_RDES1_IPCE 0x00000080
177 #define ETH_RDES1_IPCB 0x00000040
178 #define ETH_RDES1_IPV6 0x00000020
179 #define ETH_RDES1_IPV4 0x00000010
180 #define ETH_RDES1_IPHE 0x00000008
181 #define ETH_RDES1_PT 0x00000007
182 #define ETH_RDES2_L3L4FM 0xE0000000
183 #define ETH_RDES2_L4FM 0x10000000
184 #define ETH_RDES2_L3FM 0x08000000
185 #define ETH_RDES2_MADRM 0x07F80000
186 #define ETH_RDES2_HF 0x00040000
187 #define ETH_RDES2_DAF 0x00020000
188 #define ETH_RDES2_SAF 0x00010000
189 #define ETH_RDES2_VF 0x00008000
190 #define ETH_RDES2_ARPRN 0x00000400
191 #define ETH_RDES3_OWN 0x80000000
192 #define ETH_RDES3_CTXT 0x40000000
193 #define ETH_RDES3_FD 0x20000000
194 #define ETH_RDES3_LD 0x10000000
195 #define ETH_RDES3_RS2V 0x08000000
196 #define ETH_RDES3_RS1V 0x04000000
197 #define ETH_RDES3_RS0V 0x02000000
198 #define ETH_RDES3_CE 0x01000000
199 #define ETH_RDES3_GP 0x00800000
200 #define ETH_RDES3_RWT 0x00400000
201 #define ETH_RDES3_OE 0x00200000
202 #define ETH_RDES3_RE 0x00100000
203 #define ETH_RDES3_DE 0x00080000
204 #define ETH_RDES3_LT 0x00070000
205 #define ETH_RDES3_ES 0x00008000
206 #define ETH_RDES3_PL 0x00007FFF
207 
208 //Receive context descriptor
209 #define ETH_RDES0_RTSL 0xFFFFFFFF
210 #define ETH_RDES1_RTSH 0xFFFFFFFF
211 #define ETH_RDES3_OWN 0x80000000
212 #define ETH_RDES3_CTXT 0x40000000
213 
214 //C++ guard
215 #ifdef __cplusplus
216 extern "C" {
217 #endif
218 
219 
220 /**
221  * @brief Transmit descriptor
222  **/
223 
224 typedef struct
225 {
226  uint32_t tdes0;
227  uint32_t tdes1;
228  uint32_t tdes2;
229  uint32_t tdes3;
231 
232 
233 /**
234  * @brief Receive descriptor
235  **/
236 
237 typedef struct
238 {
239  uint32_t rdes0;
240  uint32_t rdes1;
241  uint32_t rdes2;
242  uint32_t rdes3;
244 
245 
246 //STM32H7 Ethernet MAC driver
247 extern const NicDriver stm32h7xxEthDriver;
248 
249 //STM32H7 Ethernet MAC related functions
251 void stm32h7xxEthInitGpio(NetInterface *interface);
252 void stm32h7xxEthInitDmaDesc(NetInterface *interface);
253 
254 void stm32h7xxEthTick(NetInterface *interface);
255 
256 void stm32h7xxEthEnableIrq(NetInterface *interface);
257 void stm32h7xxEthDisableIrq(NetInterface *interface);
258 void stm32h7xxEthEventHandler(NetInterface *interface);
259 
261  const NetBuffer *buffer, size_t offset);
262 
264 
267 
268 void stm32h7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
269  uint8_t regAddr, uint16_t data);
270 
271 uint16_t stm32h7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
272  uint8_t regAddr);
273 
274 uint32_t stm32h7xxEthCalcCrc(const void *data, size_t length);
275 
276 //C++ guard
277 #ifdef __cplusplus
278 }
279 #endif
280 
281 #endif
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void stm32h7xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void stm32h7xxEthTick(NetInterface *interface)
STM32H7 Ethernet MAC timer handler.
error_t stm32h7xxEthInit(NetInterface *interface)
STM32H7 Ethernet MAC initialization.
error_t stm32h7xxEthReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t stm32h7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32h7xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t
Error codes.
Definition: error.h:42
error_t stm32h7xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t stm32h7xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define NetInterface
Definition: net.h:36
const NicDriver stm32h7xxEthDriver
STM32H7 Ethernet MAC driver.
uint32_t stm32h7xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
void stm32h7xxEthInitGpio(NetInterface *interface)
void stm32h7xxEthEventHandler(NetInterface *interface)
STM32H7 Ethernet MAC event handler.
error_t stm32h7xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t regAddr
Transmit descriptor.
Network interface controller abstraction layer.
uint8_t data[]
Definition: dtls_misc.h:176
Receive descriptor.
NIC driver.
Definition: nic.h:179
void stm32h7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void stm32h7xxEthDisableIrq(NetInterface *interface)
Disable interrupts.