stm32h7xx_eth_driver.h
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1 /**
2  * @file stm32h7xx_eth_driver.h
3  * @brief STM32H743/753 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _STM32H7XX_ETH_DRIVER_H
30 #define _STM32H7XX_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef STM32H7XX_ETH_TX_BUFFER_COUNT
37  #define STM32H7XX_ETH_TX_BUFFER_COUNT 8
38 #elif (STM32H7XX_ETH_TX_BUFFER_COUNT < 1)
39  #error STM32H7XX_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef STM32H7XX_ETH_TX_BUFFER_SIZE
44  #define STM32H7XX_ETH_TX_BUFFER_SIZE 1536
45 #elif (STM32H7XX_ETH_TX_BUFFER_SIZE != 1536)
46  #error STM32H7XX_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef STM32H7XX_ETH_RX_BUFFER_COUNT
51  #define STM32H7XX_ETH_RX_BUFFER_COUNT 8
52 #elif (STM32H7XX_ETH_RX_BUFFER_COUNT < 1)
53  #error STM32H7XX_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef STM32H7XX_ETH_RX_BUFFER_SIZE
58  #define STM32H7XX_ETH_RX_BUFFER_SIZE 1536
59 #elif (STM32H7XX_ETH_RX_BUFFER_SIZE != 1536)
60  #error STM32H7XX_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef STM32H7XX_ETH_IRQ_PRIORITY_GROUPING
65  #define STM32H7XX_ETH_IRQ_PRIORITY_GROUPING 3
66 #elif (STM32H7XX_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error STM32H7XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef STM32H7XX_ETH_IRQ_GROUP_PRIORITY
72  #define STM32H7XX_ETH_IRQ_GROUP_PRIORITY 12
73 #elif (STM32H7XX_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error STM32H7XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef STM32H7XX_ETH_IRQ_SUB_PRIORITY
79  #define STM32H7XX_ETH_IRQ_SUB_PRIORITY 0
80 #elif (STM32H7XX_ETH_IRQ_SUB_PRIORITY < 0)
81  #error STM32H7XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //MMCRIMR register
85 #define ETH_MMCRIMR_RXLPITRCIM 0x08000000
86 #define ETH_MMCRIMR_RXLPIUSCIM 0x04000000
87 #define ETH_MMCRIMR_RXUCGPIM 0x00020000
88 #define ETH_MMCRIMR_RXALGNERPIM 0x00000040
89 #define ETH_MMCRIMR_RXCRCERPIM 0x00000020
90 
91 //MMCTIMR register
92 #define ETH_MMCTIMR_TXLPITRCIM 0x08000000
93 #define ETH_MMCTIMR_TXLPIUSCIM 0x04000000
94 #define ETH_MMCTIMR_TXGPKTIM 0x00200000
95 #define ETH_MMCTIMR_TXMCOLGPIM 0x00008000
96 #define ETH_MMCTIMR_TXSCOLGPIM 0x00004000
97 
98 //Transmit normal descriptor (read format)
99 #define ETH_TDES0_BUF1AP 0xFFFFFFFF
100 #define ETH_TDES1_BUF2AP 0xFFFFFFFF
101 #define ETH_TDES2_IOC 0x80000000
102 #define ETH_TDES2_TTSE 0x40000000
103 #define ETH_TDES2_B2L 0x3FFF0000
104 #define ETH_TDES2_VTIR 0x0000C000
105 #define ETH_TDES2_B1L 0x00003FFF
106 #define ETH_TDES3_OWN 0x80000000
107 #define ETH_TDES3_CTXT 0x40000000
108 #define ETH_TDES3_FD 0x20000000
109 #define ETH_TDES3_LD 0x10000000
110 #define ETH_TDES3_CPC 0x0C000000
111 #define ETH_TDES3_SAIC 0x03800000
112 #define ETH_TDES3_THL 0x00780000
113 #define ETH_TDES3_TSE 0x00040000
114 #define ETH_TDES3_CIC 0x00030000
115 #define ETH_TDES3_FL 0x00007FFF
116 
117 //Transmit normal descriptor (write-back format)
118 #define ETH_TDES0_TTSL 0xFFFFFFFF
119 #define ETH_TDES1_TTSH 0xFFFFFFFF
120 #define ETH_TDES3_OWN 0x80000000
121 #define ETH_TDES3_CTXT 0x40000000
122 #define ETH_TDES3_FD 0x20000000
123 #define ETH_TDES3_LD 0x10000000
124 #define ETH_TDES3_TTSS 0x00020000
125 #define ETH_TDES3_ES 0x00008000
126 #define ETH_TDES3_JT 0x00004000
127 #define ETH_TDES3_FF 0x00002000
128 #define ETH_TDES3_PCE 0x00001000
129 #define ETH_TDES3_LOC 0x00000800
130 #define ETH_TDES3_NC 0x00000400
131 #define ETH_TDES3_LC 0x00000200
132 #define ETH_TDES3_EC 0x00000100
133 #define ETH_TDES3_CC 0x000000F0
134 #define ETH_TDES3_ED 0x00000008
135 #define ETH_TDES3_UF 0x00000004
136 #define ETH_TDES3_DB 0x00000002
137 #define ETH_TDES3_IHE 0x00000001
138 
139 //Transmit context descriptor
140 #define ETH_TDES0_TTSL 0xFFFFFFFF
141 #define ETH_TDES1_TTSH 0xFFFFFFFF
142 #define ETH_TDES2_IVT 0xFFFF0000
143 #define ETH_TDES2_MSS 0x00003FFF
144 #define ETH_TDES3_OWN 0x80000000
145 #define ETH_TDES3_CTXT 0x40000000
146 #define ETH_TDES3_OSTC 0x08000000
147 #define ETH_TDES3_TCMSSV 0x04000000
148 #define ETH_TDES3_CDE 0x00800000
149 #define ETH_TDES3_IVLTV 0x00020000
150 #define ETH_TDES3_VLTV 0x00010000
151 #define ETH_TDES3_VT 0x0000FFFF
152 
153 //Receive normal descriptor (read format)
154 #define ETH_RDES0_BUF1AP 0xFFFFFFFF
155 #define ETH_RDES2_BUF2AP 0xFFFFFFFF
156 #define ETH_RDES3_OWN 0x80000000
157 #define ETH_RDES3_IOC 0x40000000
158 #define ETH_RDES3_BUF2V 0x02000000
159 #define ETH_RDES3_BUF1V 0x01000000
160 
161 //Receive normal descriptor (write-back format)
162 #define ETH_RDES0_IVT 0xFFFF0000
163 #define ETH_RDES0_OVT 0x0000FFFF
164 #define ETH_RDES1_OPC 0xFFFF0000
165 #define ETH_RDES1_TD 0x00008000
166 #define ETH_RDES1_TSA 0x00004000
167 #define ETH_RDES1_PV 0x00002000
168 #define ETH_RDES1_PFT 0x00001000
169 #define ETH_RDES1_PMT 0x00000F00
170 #define ETH_RDES1_IPCE 0x00000080
171 #define ETH_RDES1_IPCB 0x00000040
172 #define ETH_RDES1_IPV6 0x00000020
173 #define ETH_RDES1_IPV4 0x00000010
174 #define ETH_RDES1_IPHE 0x00000008
175 #define ETH_RDES1_PT 0x00000007
176 #define ETH_RDES2_L3L4FM 0xE0000000
177 #define ETH_RDES2_L4FM 0x10000000
178 #define ETH_RDES2_L3FM 0x08000000
179 #define ETH_RDES2_MADRM 0x07F80000
180 #define ETH_RDES2_HF 0x00040000
181 #define ETH_RDES2_DAF 0x00020000
182 #define ETH_RDES2_SAF 0x00010000
183 #define ETH_RDES2_VF 0x00008000
184 #define ETH_RDES2_ARPRN 0x00000400
185 #define ETH_RDES3_OWN 0x80000000
186 #define ETH_RDES3_CTXT 0x40000000
187 #define ETH_RDES3_FD 0x20000000
188 #define ETH_RDES3_LD 0x10000000
189 #define ETH_RDES3_RS2V 0x08000000
190 #define ETH_RDES3_RS1V 0x04000000
191 #define ETH_RDES3_RS0V 0x02000000
192 #define ETH_RDES3_CE 0x01000000
193 #define ETH_RDES3_GP 0x00800000
194 #define ETH_RDES3_RWT 0x00400000
195 #define ETH_RDES3_OE 0x00200000
196 #define ETH_RDES3_RE 0x00100000
197 #define ETH_RDES3_DE 0x00080000
198 #define ETH_RDES3_LT 0x00070000
199 #define ETH_RDES3_ES 0x00008000
200 #define ETH_RDES3_PL 0x00007FFF
201 
202 //Receive context descriptor
203 #define ETH_RDES0_RTSL 0xFFFFFFFF
204 #define ETH_RDES1_RTSH 0xFFFFFFFF
205 #define ETH_RDES3_OWN 0x80000000
206 #define ETH_RDES3_CTXT 0x40000000
207 
208 //C++ guard
209 #ifdef __cplusplus
210  extern "C" {
211 #endif
212 
213 
214 /**
215  * @brief Transmit descriptor
216  **/
217 
218 typedef struct
219 {
220  uint32_t tdes0;
221  uint32_t tdes1;
222  uint32_t tdes2;
223  uint32_t tdes3;
225 
226 
227 /**
228  * @brief Receive descriptor
229  **/
230 
231 typedef struct
232 {
233  uint32_t rdes0;
234  uint32_t rdes1;
235  uint32_t rdes2;
236  uint32_t rdes3;
238 
239 
240 //STM32H743/753 Ethernet MAC driver
241 extern const NicDriver stm32h7xxEthDriver;
242 
243 //STM32H743/753 Ethernet MAC related functions
245 void stm32h7xxEthInitGpio(NetInterface *interface);
246 void stm32h7xxEthInitDmaDesc(NetInterface *interface);
247 
248 void stm32h7xxEthTick(NetInterface *interface);
249 
250 void stm32h7xxEthEnableIrq(NetInterface *interface);
251 void stm32h7xxEthDisableIrq(NetInterface *interface);
252 void stm32h7xxEthEventHandler(NetInterface *interface);
253 
255  const NetBuffer *buffer, size_t offset);
256 
258 
261 
262 void stm32h7xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
263 uint16_t stm32h7xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
264 
265 uint32_t stm32h7xxEthCalcCrc(const void *data, size_t length);
266 
267 //C++ guard
268 #ifdef __cplusplus
269  }
270 #endif
271 
272 #endif
uint32_t stm32h7xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
void stm32h7xxEthEventHandler(NetInterface *interface)
STM32H743/753 Ethernet MAC event handler.
error_t stm32h7xxEthInit(NetInterface *interface)
STM32H743/753 Ethernet MAC initialization.
void stm32h7xxEthTick(NetInterface *interface)
STM32H743/753 Ethernet MAC timer handler.
void stm32h7xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
Transmit descriptor.
error_t stm32h7xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
Receive descriptor.
error_t stm32h7xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint16_t regAddr
const NicDriver stm32h7xxEthDriver
STM32H743/753 Ethernet MAC driver.
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t stm32h7xxEthReceivePacket(NetInterface *interface)
Receive a packet.
void stm32h7xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t stm32h7xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t length
Definition: dtls_misc.h:140
uint16_t stm32h7xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32h7xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void stm32h7xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void stm32h7xxEthInitGpio(NetInterface *interface)
Network interface controller abstraction layer.