32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "stm32h7xx.h"
36 #include "stm32h7xx_hal.h"
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 4
49 #pragma location = STM32H7XX_ETH_RAM_SECTION
52 #pragma data_alignment = 4
53 #pragma location = STM32H7XX_ETH_RAM_SECTION
56 #pragma data_alignment = 4
57 #pragma location = STM32H7XX_ETH_RAM_SECTION
60 #pragma data_alignment = 4
61 #pragma location = STM32H7XX_ETH_RAM_SECTION
125 TRACE_INFO(
"Initializing STM32H7 Ethernet MAC...\r\n");
128 nicDriverInterface = interface;
134 __HAL_RCC_ETH1MAC_CLK_ENABLE();
135 __HAL_RCC_ETH1TX_CLK_ENABLE();
136 __HAL_RCC_ETH1RX_CLK_ENABLE();
139 __HAL_RCC_ETH1MAC_FORCE_RESET();
140 __HAL_RCC_ETH1MAC_RELEASE_RESET();
143 ETH->DMAMR |= ETH_DMAMR_SWR;
145 while((ETH->DMAMR & ETH_DMAMR_SWR) != 0)
150 ETH->MACMDIOAR = ETH_MACMDIOAR_CR_DIV124;
153 if(interface->phyDriver != NULL)
156 error = interface->phyDriver->init(interface);
158 else if(interface->switchDriver != NULL)
161 error = interface->switchDriver->init(interface);
179 temp = ETH->MACECR & ~ETH_MACECR_GPSL;
190 ETH->DMAMR = ETH_DMAMR_INTM_0 | ETH_DMAMR_PR_1_1;
192 ETH->DMASBMR |= ETH_DMASBMR_AAL;
194 ETH->DMACCR = ETH_DMACCR_DSL_0BIT;
197 ETH->DMACTCR = ETH_DMACTCR_TPBL_32PBL;
200 ETH->DMACRCR = ETH_DMACRCR_RPBL_32PBL;
204 ETH->MTLTQOMR |= ETH_MTLTQOMR_TSF;
205 ETH->MTLRQOMR |= ETH_MTLRQOMR_RSF;
223 ETH->DMACIER = ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE;
233 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
236 ETH->DMACTCR |= ETH_DMACTCR_ST;
237 ETH->DMACRCR |= ETH_DMACRCR_SR;
255 #if defined(USE_STM32H743I_EVAL) || defined(USE_STM32H747I_EVAL) || \
256 defined(USE_STM32H747I_DISCO)
257 GPIO_InitTypeDef GPIO_InitStructure;
260 __HAL_RCC_SYSCFG_CLK_ENABLE();
263 __HAL_RCC_GPIOA_CLK_ENABLE();
264 __HAL_RCC_GPIOC_CLK_ENABLE();
265 __HAL_RCC_GPIOG_CLK_ENABLE();
268 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
271 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
272 GPIO_InitStructure.Pull = GPIO_NOPULL;
273 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
274 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
277 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
278 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
281 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
282 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
285 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
286 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
289 #elif defined(USE_STM32H735G_DK)
290 GPIO_InitTypeDef GPIO_InitStructure;
293 __HAL_RCC_SYSCFG_CLK_ENABLE();
296 __HAL_RCC_GPIOA_CLK_ENABLE();
297 __HAL_RCC_GPIOB_CLK_ENABLE();
298 __HAL_RCC_GPIOC_CLK_ENABLE();
301 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
304 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
305 GPIO_InitStructure.Pull = GPIO_NOPULL;
306 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
307 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
310 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
311 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
315 GPIO_InitStructure.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
316 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
319 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
320 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
323 #elif defined(USE_STM32H745I_DISCO) || defined(USE_STM32H750B_DISCO)
324 GPIO_InitTypeDef GPIO_InitStructure;
327 __HAL_RCC_SYSCFG_CLK_ENABLE();
330 __HAL_RCC_GPIOA_CLK_ENABLE();
331 __HAL_RCC_GPIOB_CLK_ENABLE();
332 __HAL_RCC_GPIOC_CLK_ENABLE();
333 __HAL_RCC_GPIOE_CLK_ENABLE();
334 __HAL_RCC_GPIOG_CLK_ENABLE();
335 __HAL_RCC_GPIOH_CLK_ENABLE();
336 __HAL_RCC_GPIOI_CLK_ENABLE();
339 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
342 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
343 GPIO_InitStructure.Pull = GPIO_NOPULL;
344 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
345 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
348 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
349 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
352 GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2;
353 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
357 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
358 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
361 GPIO_InitStructure.Pin = GPIO_PIN_2;
362 HAL_GPIO_Init(GPIOE, &GPIO_InitStructure);
365 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
366 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
373 GPIO_InitStructure.Pin = GPIO_PIN_10;
374 HAL_GPIO_Init(GPIOI, &GPIO_InitStructure);
378 #elif defined(USE_NUCLEO_H723ZG) || defined(USE_NUCLEO_H743ZI) || \
379 defined(USE_NUCLEO_H743ZI2) || defined(USE_NUCLEO_H745ZI_Q)
380 GPIO_InitTypeDef GPIO_InitStructure;
383 __HAL_RCC_SYSCFG_CLK_ENABLE();
386 __HAL_RCC_GPIOA_CLK_ENABLE();
387 __HAL_RCC_GPIOB_CLK_ENABLE();
388 __HAL_RCC_GPIOC_CLK_ENABLE();
389 __HAL_RCC_GPIOG_CLK_ENABLE();
392 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
395 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
396 GPIO_InitStructure.Pull = GPIO_NOPULL;
397 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
398 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
401 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
402 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
405 GPIO_InitStructure.Pin = GPIO_PIN_13;
406 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
409 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
410 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
413 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
414 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
455 ETH->DMACTDLAR = (uint32_t) &
txDmaDesc[0];
460 ETH->DMACRDLAR = (uint32_t) &
rxDmaDesc[0];
478 if(interface->phyDriver != NULL)
481 interface->phyDriver->tick(interface);
483 else if(interface->switchDriver != NULL)
486 interface->switchDriver->tick(interface);
503 NVIC_EnableIRQ(ETH_IRQn);
506 if(interface->phyDriver != NULL)
509 interface->phyDriver->enableIrq(interface);
511 else if(interface->switchDriver != NULL)
514 interface->switchDriver->enableIrq(interface);
531 NVIC_DisableIRQ(ETH_IRQn);
534 if(interface->phyDriver != NULL)
537 interface->phyDriver->disableIrq(interface);
539 else if(interface->switchDriver != NULL)
542 interface->switchDriver->disableIrq(interface);
567 status = ETH->DMACSR;
570 if((status & ETH_DMACSR_TI) != 0)
573 ETH->DMACSR = ETH_DMACSR_TI;
584 if((status & ETH_DMACSR_RI) != 0)
587 ETH->DMACSR = ETH_DMACSR_RI;
590 nicDriverInterface->nicEvent =
TRUE;
596 ETH->DMACSR = ETH_DMACSR_NIS;
672 ETH->DMACSR = ETH_DMACSR_TBU;
720 if((SYSCFG->PMCR & SYSCFG_PMCR_EPIS_SEL) != SYSCFG_ETH_MII)
775 ETH->DMACSR = ETH_DMACSR_RBU;
796 uint32_t hashTable[2];
804 if(interface->promiscuous)
807 ETH->MACPFR = ETH_MACPFR_PR;
812 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
813 ETH->MACA0HR = interface->macAddr.w[2];
829 entry = &interface->macAddrFilter[i];
842 k = (crc >> 26) & 0x3F;
845 hashTable[k / 32] |= (1 << (k % 32));
853 unicastMacAddr[j++] = entry->
addr;
863 ETH->MACA1LR = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
864 ETH->MACA1HR = unicastMacAddr[0].w[2] | ETH_MACAHR_AE;
877 ETH->MACA2LR = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
878 ETH->MACA2HR = unicastMacAddr[1].w[2] | ETH_MACAHR_AE;
891 ETH->MACA3LR = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
892 ETH->MACA3HR = unicastMacAddr[2].w[2] | ETH_MACAHR_AE;
903 if(interface->acceptAllMulticast)
906 ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_PM;
911 ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
914 ETH->MACHT0R = hashTable[0];
915 ETH->MACHT1R = hashTable[1];
918 TRACE_DEBUG(
" MACHT0R = %08" PRIX32
"\r\n", ETH->MACHT0R);
919 TRACE_DEBUG(
" MACHT1R = %08" PRIX32
"\r\n", ETH->MACHT1R);
944 config |= ETH_MACCR_FES;
948 config &= ~ETH_MACCR_FES;
954 config |= ETH_MACCR_DM;
958 config &= ~ETH_MACCR_DM;
986 temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
988 temp |= ETH_MACMDIOAR_MOC_WR | ETH_MACMDIOAR_MB;
990 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
992 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
995 ETH->MACMDIODR =
data & ETH_MACMDIODR_MD;
998 ETH->MACMDIOAR = temp;
1000 while((ETH->MACMDIOAR & ETH_MACMDIOAR_MB) != 0)
1029 temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
1031 temp |= ETH_MACMDIOAR_MOC_RD | ETH_MACMDIOAR_MB;
1033 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
1035 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
1038 ETH->MACMDIOAR = temp;
1040 while((ETH->MACMDIOAR & ETH_MACMDIOAR_MB) != 0)
1045 data = ETH->MACMDIODR & ETH_MACMDIODR_MD;
1073 p = (uint8_t *)
data;
1078 for(i = 0; i <
length; i++)
1081 for(j = 0; j < 8; j++)
1084 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
1086 crc = (crc << 1) ^ 0x04C11DB7;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define ETH_MACCR_RESERVED15
#define ETH_MMCTIMR_TXLPIUSCIM
#define ETH_MMCTIMR_TXSCOLGPIM
#define ETH_MMCTIMR_TXLPITRCIM
#define ETH_MMCTIMR_TXMCOLGPIM
#define ETH_MMCRIMR_RXUCGPIM
#define ETH_MMCTIMR_TXGPKTIM
#define ETH_MMCRIMR_RXALGNERPIM
#define ETH_MMCRIMR_RXLPIUSCIM
#define ETH_MMCRIMR_RXLPITRCIM
#define ETH_MMCRIMR_RXCRCERPIM
void stm32h7xxEthTick(NetInterface *interface)
STM32H7 Ethernet MAC timer handler.
uint16_t stm32h7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32h7xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
void stm32h7xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t stm32h7xxEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t stm32h7xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
const NicDriver stm32h7xxEthDriver
STM32H7 Ethernet MAC driver.
uint32_t stm32h7xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
__weak_func void stm32h7xxEthInitGpio(NetInterface *interface)
GPIO configuration.
error_t stm32h7xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void stm32h7xxEthEventHandler(NetInterface *interface)
STM32H7 Ethernet MAC event handler.
void stm32h7xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void ETH_IRQHandler(void)
STM32H7 Ethernet MAC interrupt service routine.
error_t stm32h7xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t stm32h7xxEthInit(NetInterface *interface)
STM32H7 Ethernet MAC initialization.
void stm32h7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
STM32H7 Ethernet MAC driver.
#define STM32H7XX_ETH_IRQ_SUB_PRIORITY
#define STM32H7XX_ETH_TX_BUFFER_SIZE
#define STM32H7XX_ETH_RAM_SECTION
#define STM32H7XX_ETH_TX_BUFFER_COUNT
#define STM32H7XX_ETH_RX_BUFFER_SIZE
#define STM32H7XX_ETH_RX_BUFFER_COUNT
#define STM32H7XX_ETH_IRQ_PRIORITY_GROUPING
#define STM32H7XX_ETH_IRQ_GROUP_PRIORITY
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.