STM32MP1 Gigabit Ethernet MAC driver. More...

#include "core/nic.h"

Data Structures
struct	Stm32mp1xxTxDmaDesc
	Transmit descriptor. More...

struct	Stm32mp1xxRxDmaDesc
	Receive descriptor. More...

Macros
#define	STM32MP1XX_ETH_TX_BUFFER_COUNT 3

#define	STM32MP1XX_ETH_TX_BUFFER_SIZE 1536

#define	STM32MP1XX_ETH_RX_BUFFER_COUNT 6

#define	STM32MP1XX_ETH_RX_BUFFER_SIZE 1536

#define	STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING 3

#define	STM32MP1XX_ETH_IRQ_GROUP_PRIORITY 12

#define	STM32MP1XX_ETH_IRQ_SUB_PRIORITY 0

#define	ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk

#define	ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)

#define	ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)

#define	ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)

#define	ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)

#define	ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)

#define	ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)

#define	ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)

#define	ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)

#define	ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)

#define	ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)

#define	ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)

#define	ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)

#define	ETH_TDES0_BUF1AP 0xFFFFFFFF

#define	ETH_TDES1_BUF2AP 0xFFFFFFFF

#define	ETH_TDES2_IOC 0x80000000

#define	ETH_TDES2_TTSE 0x40000000

#define	ETH_TDES2_B2L 0x3FFF0000

#define	ETH_TDES2_VTIR 0x0000C000

#define	ETH_TDES2_B1L 0x00003FFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_FD 0x20000000

#define	ETH_TDES3_LD 0x10000000

#define	ETH_TDES3_CPC 0x0C000000

#define	ETH_TDES3_SAIC 0x03800000

#define	ETH_TDES3_THL 0x00780000

#define	ETH_TDES3_TSE 0x00040000

#define	ETH_TDES3_CIC 0x00030000

#define	ETH_TDES3_FL 0x00007FFF

#define	ETH_TDES0_TTSL 0xFFFFFFFF

#define	ETH_TDES1_TTSH 0xFFFFFFFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_FD 0x20000000

#define	ETH_TDES3_LD 0x10000000

#define	ETH_TDES3_TTSS 0x00020000

#define	ETH_TDES3_ES 0x00008000

#define	ETH_TDES3_JT 0x00004000

#define	ETH_TDES3_FF 0x00002000

#define	ETH_TDES3_PCE 0x00001000

#define	ETH_TDES3_LOC 0x00000800

#define	ETH_TDES3_NC 0x00000400

#define	ETH_TDES3_LC 0x00000200

#define	ETH_TDES3_EC 0x00000100

#define	ETH_TDES3_CC 0x000000F0

#define	ETH_TDES3_ED 0x00000008

#define	ETH_TDES3_UF 0x00000004

#define	ETH_TDES3_DB 0x00000002

#define	ETH_TDES3_IHE 0x00000001

#define	ETH_TDES0_TTSL 0xFFFFFFFF

#define	ETH_TDES1_TTSH 0xFFFFFFFF

#define	ETH_TDES2_IVT 0xFFFF0000

#define	ETH_TDES2_MSS 0x00003FFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_OSTC 0x08000000

#define	ETH_TDES3_TCMSSV 0x04000000

#define	ETH_TDES3_CDE 0x00800000

#define	ETH_TDES3_IVLTV 0x00020000

#define	ETH_TDES3_VLTV 0x00010000

#define	ETH_TDES3_VT 0x0000FFFF

#define	ETH_RDES0_BUF1AP 0xFFFFFFFF

#define	ETH_RDES2_BUF2AP 0xFFFFFFFF

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_IOC 0x40000000

#define	ETH_RDES3_BUF2V 0x02000000

#define	ETH_RDES3_BUF1V 0x01000000

#define	ETH_RDES0_IVT 0xFFFF0000

#define	ETH_RDES0_OVT 0x0000FFFF

#define	ETH_RDES1_OPC 0xFFFF0000

#define	ETH_RDES1_TD 0x00008000

#define	ETH_RDES1_TSA 0x00004000

#define	ETH_RDES1_PV 0x00002000

#define	ETH_RDES1_PFT 0x00001000

#define	ETH_RDES1_PMT 0x00000F00

#define	ETH_RDES1_IPCE 0x00000080

#define	ETH_RDES1_IPCB 0x00000040

#define	ETH_RDES1_IPV6 0x00000020

#define	ETH_RDES1_IPV4 0x00000010

#define	ETH_RDES1_IPHE 0x00000008

#define	ETH_RDES1_PT 0x00000007

#define	ETH_RDES2_L3L4FM 0xE0000000

#define	ETH_RDES2_L4FM 0x10000000

#define	ETH_RDES2_L3FM 0x08000000

#define	ETH_RDES2_MADRM 0x07F80000

#define	ETH_RDES2_HF 0x00040000

#define	ETH_RDES2_DAF 0x00020000

#define	ETH_RDES2_SAF 0x00010000

#define	ETH_RDES2_VF 0x00008000

#define	ETH_RDES2_ARPRN 0x00000400

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_CTXT 0x40000000

#define	ETH_RDES3_FD 0x20000000

#define	ETH_RDES3_LD 0x10000000

#define	ETH_RDES3_RS2V 0x08000000

#define	ETH_RDES3_RS1V 0x04000000

#define	ETH_RDES3_RS0V 0x02000000

#define	ETH_RDES3_CE 0x01000000

#define	ETH_RDES3_GP 0x00800000

#define	ETH_RDES3_RWT 0x00400000

#define	ETH_RDES3_OE 0x00200000

#define	ETH_RDES3_RE 0x00100000

#define	ETH_RDES3_DE 0x00080000

#define	ETH_RDES3_LT 0x00070000

#define	ETH_RDES3_ES 0x00008000

#define	ETH_RDES3_PL 0x00007FFF

#define	ETH_RDES0_RTSL 0xFFFFFFFF

#define	ETH_RDES1_RTSH 0xFFFFFFFF

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_CTXT 0x40000000

Functions
error_t	stm32mp1xxEthInit (NetInterface *interface)
	STM32MP1 Ethernet MAC initialization. More...

void	stm32mp1xxEthInitGpio (NetInterface *interface)
	GPIO configuration. More...

void	stm32mp1xxEthInitDmaDesc (NetInterface *interface)
	Initialize DMA descriptor lists. More...

void	stm32mp1xxEthTick (NetInterface *interface)
	STM32MP1 Ethernet MAC timer handler. More...

void	stm32mp1xxEthEnableIrq (NetInterface *interface)
	Enable interrupts. More...

void	stm32mp1xxEthDisableIrq (NetInterface *interface)
	Disable interrupts. More...

void	stm32mp1xxEthEventHandler (NetInterface *interface)
	STM32MP1 Ethernet MAC event handler. More...

error_t	stm32mp1xxEthSendPacket (NetInterface interface, const NetBuffer buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...

error_t	stm32mp1xxEthReceivePacket (NetInterface *interface)
	Receive a packet. More...

error_t	stm32mp1xxEthUpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...

error_t	stm32mp1xxEthUpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...

void	stm32mp1xxEthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...

uint16_t	stm32mp1xxEthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

uint32_t	stm32mp1xxEthCalcCrc (const void *data, size_t length)
	CRC calculation. More...

Variables
const NicDriver	stm32mp1xxEthDriver
	STM32MP1 Ethernet MAC driver. More...

Detailed Description

STM32MP1 Gigabit Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author: Oryx Embedded SARL (www.oryx-embedded.com)

Version: 2.4.4

Definition in file stm32mp1xx_eth_driver.h.

Macro Definition Documentation

◆ ETH_DMAC0CR_DSL_Val

#define ETH_DMAC0CR_DSL_Val ( n ) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)

Definition at line 100 of file stm32mp1xx_eth_driver.h.

◆ ETH_DMAC0RXCR_RBSZ_Val

#define ETH_DMAC0RXCR_RBSZ_Val ( n ) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)

Definition at line 103 of file stm32mp1xx_eth_driver.h.

◆ ETH_DMAC0RXCR_RXPBL_Val

#define ETH_DMAC0RXCR_RXPBL_Val ( n ) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)

Definition at line 102 of file stm32mp1xx_eth_driver.h.

◆ ETH_DMAC0TXCR_TXPBL_Val

#define ETH_DMAC0TXCR_TXPBL_Val ( n ) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)

Definition at line 101 of file stm32mp1xx_eth_driver.h.

◆ ETH_DMAMR_INTM_Val

#define ETH_DMAMR_INTM_Val ( n ) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)

Definition at line 98 of file stm32mp1xx_eth_driver.h.

◆ ETH_DMAMR_PR_Val

#define ETH_DMAMR_PR_Val ( n ) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)

Definition at line 99 of file stm32mp1xx_eth_driver.h.

◆ ETH_MACMDIOAR_CR_Val

#define ETH_MACMDIOAR_CR_Val ( n ) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)

Definition at line 93 of file stm32mp1xx_eth_driver.h.

◆ ETH_MACMDIOAR_GOC_Val

#define ETH_MACMDIOAR_GOC_Val ( n ) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)

Definition at line 94 of file stm32mp1xx_eth_driver.h.

◆ ETH_MACRXQC0R_RXQ0EN_Val

#define ETH_MACRXQC0R_RXQ0EN_Val ( n ) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)

Definition at line 92 of file stm32mp1xx_eth_driver.h.

◆ ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk

#define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk

Definition at line 88 of file stm32mp1xx_eth_driver.h.

◆ ETH_MTLRXQ0OMR_RQS_Val

#define ETH_MTLRXQ0OMR_RQS_Val ( n ) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)

Definition at line 97 of file stm32mp1xx_eth_driver.h.

◆ ETH_MTLTXQ0OMR_TQS_Val

#define ETH_MTLTXQ0OMR_TQS_Val ( n ) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)

Definition at line 95 of file stm32mp1xx_eth_driver.h.

◆ ETH_MTLTXQ0OMR_TXQEN_Val

#define ETH_MTLTXQ0OMR_TXQEN_Val ( n ) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)

Definition at line 96 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES0_BUF1AP

#define ETH_RDES0_BUF1AP 0xFFFFFFFF

Definition at line 161 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES0_IVT

#define ETH_RDES0_IVT 0xFFFF0000

Definition at line 169 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES0_OVT

#define ETH_RDES0_OVT 0x0000FFFF

Definition at line 170 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES0_RTSL

#define ETH_RDES0_RTSL 0xFFFFFFFF

Definition at line 210 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_IPCB

#define ETH_RDES1_IPCB 0x00000040

Definition at line 178 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_IPCE

#define ETH_RDES1_IPCE 0x00000080

Definition at line 177 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_IPHE

#define ETH_RDES1_IPHE 0x00000008

Definition at line 181 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_IPV4

#define ETH_RDES1_IPV4 0x00000010

Definition at line 180 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_IPV6

#define ETH_RDES1_IPV6 0x00000020

Definition at line 179 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_OPC

#define ETH_RDES1_OPC 0xFFFF0000

Definition at line 171 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_PFT

#define ETH_RDES1_PFT 0x00001000

Definition at line 175 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_PMT

#define ETH_RDES1_PMT 0x00000F00

Definition at line 176 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_PT

#define ETH_RDES1_PT 0x00000007

Definition at line 182 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_PV

#define ETH_RDES1_PV 0x00002000

Definition at line 174 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_RTSH

#define ETH_RDES1_RTSH 0xFFFFFFFF

Definition at line 211 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_TD

#define ETH_RDES1_TD 0x00008000

Definition at line 172 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES1_TSA

#define ETH_RDES1_TSA 0x00004000

Definition at line 173 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_ARPRN

#define ETH_RDES2_ARPRN 0x00000400

Definition at line 191 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_BUF2AP

#define ETH_RDES2_BUF2AP 0xFFFFFFFF

Definition at line 162 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_DAF

#define ETH_RDES2_DAF 0x00020000

Definition at line 188 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_HF

#define ETH_RDES2_HF 0x00040000

Definition at line 187 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_L3FM

#define ETH_RDES2_L3FM 0x08000000

Definition at line 185 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_L3L4FM

#define ETH_RDES2_L3L4FM 0xE0000000

Definition at line 183 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_L4FM

#define ETH_RDES2_L4FM 0x10000000

Definition at line 184 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_MADRM

#define ETH_RDES2_MADRM 0x07F80000

Definition at line 186 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_SAF

#define ETH_RDES2_SAF 0x00010000

Definition at line 189 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES2_VF

#define ETH_RDES2_VF 0x00008000

Definition at line 190 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_BUF1V

#define ETH_RDES3_BUF1V 0x01000000

Definition at line 166 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_BUF2V

#define ETH_RDES3_BUF2V 0x02000000

Definition at line 165 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_CE

#define ETH_RDES3_CE 0x01000000

Definition at line 199 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_CTXT [1/2]

#define ETH_RDES3_CTXT 0x40000000

Definition at line 213 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_CTXT [2/2]

#define ETH_RDES3_CTXT 0x40000000

Definition at line 213 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_DE

#define ETH_RDES3_DE 0x00080000

Definition at line 204 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_ES

#define ETH_RDES3_ES 0x00008000

Definition at line 206 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_FD

#define ETH_RDES3_FD 0x20000000

Definition at line 194 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_GP

#define ETH_RDES3_GP 0x00800000

Definition at line 200 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_IOC

#define ETH_RDES3_IOC 0x40000000

Definition at line 164 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_LD

#define ETH_RDES3_LD 0x10000000

Definition at line 195 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_LT

#define ETH_RDES3_LT 0x00070000

Definition at line 205 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_OE

#define ETH_RDES3_OE 0x00200000

Definition at line 202 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_OWN [1/3]

#define ETH_RDES3_OWN 0x80000000

Definition at line 212 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_OWN [2/3]

#define ETH_RDES3_OWN 0x80000000

Definition at line 212 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_OWN [3/3]

#define ETH_RDES3_OWN 0x80000000

Definition at line 212 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_PL

#define ETH_RDES3_PL 0x00007FFF

Definition at line 207 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_RE

#define ETH_RDES3_RE 0x00100000

Definition at line 203 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_RS0V

#define ETH_RDES3_RS0V 0x02000000

Definition at line 198 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_RS1V

#define ETH_RDES3_RS1V 0x04000000

Definition at line 197 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_RS2V

#define ETH_RDES3_RS2V 0x08000000

Definition at line 196 of file stm32mp1xx_eth_driver.h.

◆ ETH_RDES3_RWT

#define ETH_RDES3_RWT 0x00400000

Definition at line 201 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES0_BUF1AP

#define ETH_TDES0_BUF1AP 0xFFFFFFFF

Definition at line 106 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES0_TTSL [1/2]

#define ETH_TDES0_TTSL 0xFFFFFFFF

Definition at line 147 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES0_TTSL [2/2]

#define ETH_TDES0_TTSL 0xFFFFFFFF

Definition at line 147 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES1_BUF2AP

#define ETH_TDES1_BUF2AP 0xFFFFFFFF

Definition at line 107 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES1_TTSH [1/2]

#define ETH_TDES1_TTSH 0xFFFFFFFF

Definition at line 148 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES1_TTSH [2/2]

#define ETH_TDES1_TTSH 0xFFFFFFFF

Definition at line 148 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_B1L

#define ETH_TDES2_B1L 0x00003FFF

Definition at line 112 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_B2L

#define ETH_TDES2_B2L 0x3FFF0000

Definition at line 110 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_IOC

#define ETH_TDES2_IOC 0x80000000

Definition at line 108 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_IVT

#define ETH_TDES2_IVT 0xFFFF0000

Definition at line 149 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_MSS

#define ETH_TDES2_MSS 0x00003FFF

Definition at line 150 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_TTSE

#define ETH_TDES2_TTSE 0x40000000

Definition at line 109 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES2_VTIR

#define ETH_TDES2_VTIR 0x0000C000

Definition at line 111 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CC

#define ETH_TDES3_CC 0x000000F0

Definition at line 140 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CDE

#define ETH_TDES3_CDE 0x00800000

Definition at line 155 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CIC

#define ETH_TDES3_CIC 0x00030000

Definition at line 121 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CPC

#define ETH_TDES3_CPC 0x0C000000

Definition at line 117 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CTXT [1/3]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 152 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CTXT [2/3]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 152 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_CTXT [3/3]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 152 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_DB

#define ETH_TDES3_DB 0x00000002

Definition at line 143 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_EC

#define ETH_TDES3_EC 0x00000100

Definition at line 139 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_ED

#define ETH_TDES3_ED 0x00000008

Definition at line 141 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_ES

#define ETH_TDES3_ES 0x00008000

Definition at line 132 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_FD [1/2]

#define ETH_TDES3_FD 0x20000000

Definition at line 129 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_FD [2/2]

#define ETH_TDES3_FD 0x20000000

Definition at line 129 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_FF

#define ETH_TDES3_FF 0x00002000

Definition at line 134 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_FL

#define ETH_TDES3_FL 0x00007FFF

Definition at line 122 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_IHE

#define ETH_TDES3_IHE 0x00000001

Definition at line 144 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_IVLTV

#define ETH_TDES3_IVLTV 0x00020000

Definition at line 156 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_JT

#define ETH_TDES3_JT 0x00004000

Definition at line 133 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_LC

#define ETH_TDES3_LC 0x00000200

Definition at line 138 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_LD [1/2]

#define ETH_TDES3_LD 0x10000000

Definition at line 130 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_LD [2/2]

#define ETH_TDES3_LD 0x10000000

Definition at line 130 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_LOC

#define ETH_TDES3_LOC 0x00000800

Definition at line 136 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_NC

#define ETH_TDES3_NC 0x00000400

Definition at line 137 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_OSTC

#define ETH_TDES3_OSTC 0x08000000

Definition at line 153 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_OWN [1/3]

#define ETH_TDES3_OWN 0x80000000

Definition at line 151 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_OWN [2/3]

#define ETH_TDES3_OWN 0x80000000

Definition at line 151 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_OWN [3/3]

#define ETH_TDES3_OWN 0x80000000

Definition at line 151 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_PCE

#define ETH_TDES3_PCE 0x00001000

Definition at line 135 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_SAIC

#define ETH_TDES3_SAIC 0x03800000

Definition at line 118 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_TCMSSV

#define ETH_TDES3_TCMSSV 0x04000000

Definition at line 154 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_THL

#define ETH_TDES3_THL 0x00780000

Definition at line 119 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_TSE

#define ETH_TDES3_TSE 0x00040000

Definition at line 120 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_TTSS

#define ETH_TDES3_TTSS 0x00020000

Definition at line 131 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_UF

#define ETH_TDES3_UF 0x00000004

Definition at line 142 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_VLTV

#define ETH_TDES3_VLTV 0x00010000

Definition at line 157 of file stm32mp1xx_eth_driver.h.

◆ ETH_TDES3_VT

#define ETH_TDES3_VT 0x0000FFFF

Definition at line 158 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_IRQ_GROUP_PRIORITY

#define STM32MP1XX_ETH_IRQ_GROUP_PRIORITY 12

Definition at line 74 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING

#define STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING 3

Definition at line 67 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_IRQ_SUB_PRIORITY

#define STM32MP1XX_ETH_IRQ_SUB_PRIORITY 0

Definition at line 81 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_RX_BUFFER_COUNT

#define STM32MP1XX_ETH_RX_BUFFER_COUNT 6

Definition at line 53 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_RX_BUFFER_SIZE

#define STM32MP1XX_ETH_RX_BUFFER_SIZE 1536

Definition at line 60 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_TX_BUFFER_COUNT

#define STM32MP1XX_ETH_TX_BUFFER_COUNT 3

Definition at line 39 of file stm32mp1xx_eth_driver.h.

◆ STM32MP1XX_ETH_TX_BUFFER_SIZE

#define STM32MP1XX_ETH_TX_BUFFER_SIZE 1536

Definition at line 46 of file stm32mp1xx_eth_driver.h.

Function Documentation

◆ stm32mp1xxEthCalcCrc()

uint32_t stm32mp1xxEthCalcCrc	(	const void *	data,
		size_t	length
	)

CRC calculation.

Parameters

[in]	data	Pointer to the data over which to calculate the CRC
[in]	length	Number of bytes to process

Returns: Resulting CRC value

Definition at line 1018 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthDisableIrq()

void stm32mp1xxEthDisableIrq ( NetInterface * interface )

Disable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 489 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthEnableIrq()

void stm32mp1xxEthEnableIrq ( NetInterface * interface )

Enable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 461 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthEventHandler()

void stm32mp1xxEthEventHandler ( NetInterface * interface )

STM32MP1 Ethernet MAC event handler.

Parameters

[in] interface Underlying network interface

Definition at line 569 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthInit()

error_t stm32mp1xxEthInit ( NetInterface * interface )

STM32MP1 Ethernet MAC initialization.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 115 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthInitDmaDesc()

void stm32mp1xxEthInitDmaDesc ( NetInterface * interface )

Initialize DMA descriptor lists.

Parameters

[in] interface Underlying network interface

Definition at line 385 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthInitGpio()

void stm32mp1xxEthInitGpio ( NetInterface * interface )

GPIO configuration.

Parameters

[in] interface Underlying network interface

Definition at line 254 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthReadPhyReg()

uint16_t stm32mp1xxEthReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns: Register value

Definition at line 972 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthReceivePacket()

error_t stm32mp1xxEthReceivePacket ( NetInterface * interface )

Receive a packet.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 659 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthSendPacket()

error_t stm32mp1xxEthSendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns: Error code

Definition at line 594 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthTick()

void stm32mp1xxEthTick ( NetInterface * interface )

STM32MP1 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in] interface Underlying network interface

Definition at line 436 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthUpdateMacAddrFilter()

error_t stm32mp1xxEthUpdateMacAddrFilter ( NetInterface * interface )

Configure MAC address filtering.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 734 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthUpdateMacConfig()

error_t stm32mp1xxEthUpdateMacConfig ( NetInterface * interface )

Adjust MAC configuration parameters for proper operation.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 878 of file stm32mp1xx_eth_driver.c.

◆ stm32mp1xxEthWritePhyReg()

void stm32mp1xxEthWritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 930 of file stm32mp1xx_eth_driver.c.

Variable Documentation

◆ stm32mp1xxEthDriver

const NicDriver stm32mp1xxEthDriver

extern

STM32MP1 Ethernet MAC driver.

Definition at line 88 of file stm32mp1xx_eth_driver.c.

Data Structures

Macros

Functions

Variables

Detailed Description

License

Macro Definition Documentation

◆ ETH_DMAC0CR_DSL_Val

◆ ETH_DMAC0RXCR_RBSZ_Val

◆ ETH_DMAC0RXCR_RXPBL_Val

◆ ETH_DMAC0TXCR_TXPBL_Val

◆ ETH_DMAMR_INTM_Val

◆ ETH_DMAMR_PR_Val

◆ ETH_MACMDIOAR_CR_Val

◆ ETH_MACMDIOAR_GOC_Val

◆ ETH_MACRXQC0R_RXQ0EN_Val

◆ ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk

◆ ETH_MTLRXQ0OMR_RQS_Val

◆ ETH_MTLTXQ0OMR_TQS_Val

◆ ETH_MTLTXQ0OMR_TXQEN_Val

◆ ETH_RDES0_BUF1AP

◆ ETH_RDES0_IVT

◆ ETH_RDES0_OVT

◆ ETH_RDES0_RTSL

◆ ETH_RDES1_IPCB

◆ ETH_RDES1_IPCE

◆ ETH_RDES1_IPHE

◆ ETH_RDES1_IPV4

◆ ETH_RDES1_IPV6

◆ ETH_RDES1_OPC

◆ ETH_RDES1_PFT

◆ ETH_RDES1_PMT

◆ ETH_RDES1_PT

◆ ETH_RDES1_PV

◆ ETH_RDES1_RTSH

◆ ETH_RDES1_TD

◆ ETH_RDES1_TSA

◆ ETH_RDES2_ARPRN

◆ ETH_RDES2_BUF2AP

◆ ETH_RDES2_DAF

◆ ETH_RDES2_HF

◆ ETH_RDES2_L3FM

◆ ETH_RDES2_L3L4FM

◆ ETH_RDES2_L4FM

◆ ETH_RDES2_MADRM

◆ ETH_RDES2_SAF

◆ ETH_RDES2_VF

◆ ETH_RDES3_BUF1V

◆ ETH_RDES3_BUF2V

◆ ETH_RDES3_CE

◆ ETH_RDES3_CTXT [1/2]

◆ ETH_RDES3_CTXT [2/2]

◆ ETH_RDES3_DE

◆ ETH_RDES3_ES

◆ ETH_RDES3_FD

◆ ETH_RDES3_GP

◆ ETH_RDES3_IOC

◆ ETH_RDES3_LD

◆ ETH_RDES3_LT

◆ ETH_RDES3_OE

◆ ETH_RDES3_OWN [1/3]

◆ ETH_RDES3_OWN [2/3]

◆ ETH_RDES3_OWN [3/3]

◆ ETH_RDES3_PL

◆ ETH_RDES3_RE

◆ ETH_RDES3_RS0V

◆ ETH_RDES3_RS1V

◆ ETH_RDES3_RS2V

◆ ETH_RDES3_RWT

◆ ETH_TDES0_BUF1AP

◆ ETH_TDES0_TTSL [1/2]

◆ ETH_TDES0_TTSL [2/2]

◆ ETH_TDES1_BUF2AP

◆ ETH_TDES1_TTSH [1/2]

◆ ETH_TDES1_TTSH [2/2]

◆ ETH_TDES2_B1L

◆ ETH_TDES2_B2L

◆ ETH_TDES2_IOC

◆ ETH_TDES2_IVT

◆ ETH_TDES2_MSS