stm32mp1xx_eth_driver.h
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1 /**
2  * @file stm32mp1xx_eth_driver.h
3  * @brief STM32MP1 Gigabit Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _STM32MP1XX_ETH_DRIVER_H
32 #define _STM32MP1XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32MP1XX_ETH_TX_BUFFER_COUNT
39  #define STM32MP1XX_ETH_TX_BUFFER_COUNT 3
40 #elif (STM32MP1XX_ETH_TX_BUFFER_COUNT < 1)
41  #error STM32MP1XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32MP1XX_ETH_TX_BUFFER_SIZE
46  #define STM32MP1XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (STM32MP1XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error STM32MP1XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32MP1XX_ETH_RX_BUFFER_COUNT
53  #define STM32MP1XX_ETH_RX_BUFFER_COUNT 6
54 #elif (STM32MP1XX_ETH_RX_BUFFER_COUNT < 1)
55  #error STM32MP1XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32MP1XX_ETH_RX_BUFFER_SIZE
60  #define STM32MP1XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (STM32MP1XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error STM32MP1XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING
67  #define STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef STM32MP1XX_ETH_IRQ_GROUP_PRIORITY
74  #define STM32MP1XX_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (STM32MP1XX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error STM32MP1XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef STM32MP1XX_ETH_IRQ_SUB_PRIORITY
81  #define STM32MP1XX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (STM32MP1XX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error STM32MP1XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //MACRC0R register
87 #define ETH_MACRC0R_RXQ1EN_1 0x00000004
88 #define ETH_MACRC0R_RXQ0EN_1 0x00000001
89 
90 //MMCRIMR register
91 #define ETH_MMCRIMR_RXLPITRCIM 0x08000000
92 #define ETH_MMCRIMR_RXLPIUSCIM 0x04000000
93 #define ETH_MMCRIMR_RXUCGPIM 0x00020000
94 #define ETH_MMCRIMR_RXALGNERPIM 0x00000040
95 #define ETH_MMCRIMR_RXCRCERPIM 0x00000020
96 
97 //MMCTIMR register
98 #define ETH_MMCTIMR_TXLPITRCIM 0x08000000
99 #define ETH_MMCTIMR_TXLPIUSCIM 0x04000000
100 #define ETH_MMCTIMR_TXGPKTIM 0x00200000
101 #define ETH_MMCTIMR_TXMCOLGPIM 0x00008000
102 #define ETH_MMCTIMR_TXSCOLGPIM 0x00004000
103 
104 //MTLTQOMR register
105 #define ETH_MTLTQOMR_TQS_7 0x00070000
106 #define ETH_MTLTQOMR_TXQEN_2 0x00000008
107 
108 //MTLRQOMR register
109 #define ETH_MTLRQOMR_RQS_7 0x00700000
110 
111 //Transmit normal descriptor (read format)
112 #define ETH_TDES0_BUF1AP 0xFFFFFFFF
113 #define ETH_TDES1_BUF2AP 0xFFFFFFFF
114 #define ETH_TDES2_IOC 0x80000000
115 #define ETH_TDES2_TTSE 0x40000000
116 #define ETH_TDES2_B2L 0x3FFF0000
117 #define ETH_TDES2_VTIR 0x0000C000
118 #define ETH_TDES2_B1L 0x00003FFF
119 #define ETH_TDES3_OWN 0x80000000
120 #define ETH_TDES3_CTXT 0x40000000
121 #define ETH_TDES3_FD 0x20000000
122 #define ETH_TDES3_LD 0x10000000
123 #define ETH_TDES3_CPC 0x0C000000
124 #define ETH_TDES3_SAIC 0x03800000
125 #define ETH_TDES3_THL 0x00780000
126 #define ETH_TDES3_TSE 0x00040000
127 #define ETH_TDES3_CIC 0x00030000
128 #define ETH_TDES3_FL 0x00007FFF
129 
130 //Transmit normal descriptor (write-back format)
131 #define ETH_TDES0_TTSL 0xFFFFFFFF
132 #define ETH_TDES1_TTSH 0xFFFFFFFF
133 #define ETH_TDES3_OWN 0x80000000
134 #define ETH_TDES3_CTXT 0x40000000
135 #define ETH_TDES3_FD 0x20000000
136 #define ETH_TDES3_LD 0x10000000
137 #define ETH_TDES3_TTSS 0x00020000
138 #define ETH_TDES3_ES 0x00008000
139 #define ETH_TDES3_JT 0x00004000
140 #define ETH_TDES3_FF 0x00002000
141 #define ETH_TDES3_PCE 0x00001000
142 #define ETH_TDES3_LOC 0x00000800
143 #define ETH_TDES3_NC 0x00000400
144 #define ETH_TDES3_LC 0x00000200
145 #define ETH_TDES3_EC 0x00000100
146 #define ETH_TDES3_CC 0x000000F0
147 #define ETH_TDES3_ED 0x00000008
148 #define ETH_TDES3_UF 0x00000004
149 #define ETH_TDES3_DB 0x00000002
150 #define ETH_TDES3_IHE 0x00000001
151 
152 //Transmit context descriptor
153 #define ETH_TDES0_TTSL 0xFFFFFFFF
154 #define ETH_TDES1_TTSH 0xFFFFFFFF
155 #define ETH_TDES2_IVT 0xFFFF0000
156 #define ETH_TDES2_MSS 0x00003FFF
157 #define ETH_TDES3_OWN 0x80000000
158 #define ETH_TDES3_CTXT 0x40000000
159 #define ETH_TDES3_OSTC 0x08000000
160 #define ETH_TDES3_TCMSSV 0x04000000
161 #define ETH_TDES3_CDE 0x00800000
162 #define ETH_TDES3_IVLTV 0x00020000
163 #define ETH_TDES3_VLTV 0x00010000
164 #define ETH_TDES3_VT 0x0000FFFF
165 
166 //Receive normal descriptor (read format)
167 #define ETH_RDES0_BUF1AP 0xFFFFFFFF
168 #define ETH_RDES2_BUF2AP 0xFFFFFFFF
169 #define ETH_RDES3_OWN 0x80000000
170 #define ETH_RDES3_IOC 0x40000000
171 #define ETH_RDES3_BUF2V 0x02000000
172 #define ETH_RDES3_BUF1V 0x01000000
173 
174 //Receive normal descriptor (write-back format)
175 #define ETH_RDES0_IVT 0xFFFF0000
176 #define ETH_RDES0_OVT 0x0000FFFF
177 #define ETH_RDES1_OPC 0xFFFF0000
178 #define ETH_RDES1_TD 0x00008000
179 #define ETH_RDES1_TSA 0x00004000
180 #define ETH_RDES1_PV 0x00002000
181 #define ETH_RDES1_PFT 0x00001000
182 #define ETH_RDES1_PMT 0x00000F00
183 #define ETH_RDES1_IPCE 0x00000080
184 #define ETH_RDES1_IPCB 0x00000040
185 #define ETH_RDES1_IPV6 0x00000020
186 #define ETH_RDES1_IPV4 0x00000010
187 #define ETH_RDES1_IPHE 0x00000008
188 #define ETH_RDES1_PT 0x00000007
189 #define ETH_RDES2_L3L4FM 0xE0000000
190 #define ETH_RDES2_L4FM 0x10000000
191 #define ETH_RDES2_L3FM 0x08000000
192 #define ETH_RDES2_MADRM 0x07F80000
193 #define ETH_RDES2_HF 0x00040000
194 #define ETH_RDES2_DAF 0x00020000
195 #define ETH_RDES2_SAF 0x00010000
196 #define ETH_RDES2_VF 0x00008000
197 #define ETH_RDES2_ARPRN 0x00000400
198 #define ETH_RDES3_OWN 0x80000000
199 #define ETH_RDES3_CTXT 0x40000000
200 #define ETH_RDES3_FD 0x20000000
201 #define ETH_RDES3_LD 0x10000000
202 #define ETH_RDES3_RS2V 0x08000000
203 #define ETH_RDES3_RS1V 0x04000000
204 #define ETH_RDES3_RS0V 0x02000000
205 #define ETH_RDES3_CE 0x01000000
206 #define ETH_RDES3_GP 0x00800000
207 #define ETH_RDES3_RWT 0x00400000
208 #define ETH_RDES3_OE 0x00200000
209 #define ETH_RDES3_RE 0x00100000
210 #define ETH_RDES3_DE 0x00080000
211 #define ETH_RDES3_LT 0x00070000
212 #define ETH_RDES3_ES 0x00008000
213 #define ETH_RDES3_PL 0x00007FFF
214 
215 //Receive context descriptor
216 #define ETH_RDES0_RTSL 0xFFFFFFFF
217 #define ETH_RDES1_RTSH 0xFFFFFFFF
218 #define ETH_RDES3_OWN 0x80000000
219 #define ETH_RDES3_CTXT 0x40000000
220 
221 //C++ guard
222 #ifdef __cplusplus
223  extern "C" {
224 #endif
225 
226 
227 /**
228  * @brief Transmit descriptor
229  **/
230 
231 typedef struct
232 {
233  uint32_t tdes0;
234  uint32_t tdes1;
235  uint32_t tdes2;
236  uint32_t tdes3;
238 
239 
240 /**
241  * @brief Receive descriptor
242  **/
243 
244 typedef struct
245 {
246  uint32_t rdes0;
247  uint32_t rdes1;
248  uint32_t rdes2;
249  uint32_t rdes3;
251 
252 
253 //STM32MP1 Ethernet MAC driver
254 extern const NicDriver stm32mp1xxEthDriver;
255 
256 //STM32MP1 Ethernet MAC related functions
258 void stm32mp1xxEthInitGpio(NetInterface *interface);
259 void stm32mp1xxEthInitDmaDesc(NetInterface *interface);
260 
261 void stm32mp1xxEthTick(NetInterface *interface);
262 
263 void stm32mp1xxEthEnableIrq(NetInterface *interface);
264 void stm32mp1xxEthDisableIrq(NetInterface *interface);
265 void stm32mp1xxEthEventHandler(NetInterface *interface);
266 
268  const NetBuffer *buffer, size_t offset);
269 
271 
274 
275 void stm32mp1xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
276  uint8_t regAddr, uint16_t data);
277 
278 uint16_t stm32mp1xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
279  uint8_t regAddr);
280 
281 uint32_t stm32mp1xxEthCalcCrc(const void *data, size_t length);
282 
283 //C++ guard
284 #ifdef __cplusplus
285  }
286 #endif
287 
288 #endif
void stm32mp1xxEthEventHandler(NetInterface *interface)
STM32MP1 Ethernet MAC event handler.
Receive descriptor.
error_t stm32mp1xxEthInit(NetInterface *interface)
STM32MP1 Ethernet MAC initialization.
void stm32mp1xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t stm32mp1xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint16_t stm32mp1xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32mp1xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t opcode
Definition: dns_common.h:172
error_t stm32mp1xxEthReceivePacket(NetInterface *interface)
Receive a packet.
void stm32mp1xxEthInitGpio(NetInterface *interface)
Transmit descriptor.
NIC driver.
Definition: nic.h:179
const NicDriver stm32mp1xxEthDriver
STM32MP1 Ethernet MAC driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void stm32mp1xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t regAddr
void stm32mp1xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t
Error codes.
Definition: error.h:42
error_t stm32mp1xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t stm32mp1xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint8_t data[]
Definition: dtls_misc.h:169
void stm32mp1xxEthTick(NetInterface *interface)
STM32MP1 Ethernet MAC timer handler.
#define NetInterface
Definition: net.h:36
uint32_t stm32mp1xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
uint8_t length
Definition: dtls_misc.h:142
Network interface controller abstraction layer.