str912_eth_driver.h
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1 /**
2  * @file str912_eth_driver.h
3  * @brief STR9 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _STR912_ETH_DRIVER_H
32 #define _STR912_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STR912_ETH_TX_BUFFER_COUNT
39  #define STR912_ETH_TX_BUFFER_COUNT 2
40 #elif (STR912_ETH_TX_BUFFER_COUNT < 1)
41  #error STR912_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STR912_ETH_TX_BUFFER_SIZE
46  #define STR912_ETH_TX_BUFFER_SIZE 1536
47 #elif (STR912_ETH_TX_BUFFER_SIZE != 1536)
48  #error STR912_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STR912_ETH_RX_BUFFER_COUNT
53  #define STR912_ETH_RX_BUFFER_COUNT 4
54 #elif (STR912_ETH_RX_BUFFER_COUNT < 1)
55  #error STR912_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STR912_ETH_RX_BUFFER_SIZE
60  #define STR912_ETH_RX_BUFFER_SIZE 1536
61 #elif (STR912_ETH_RX_BUFFER_SIZE != 1536)
62  #error STR912_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt priority
66 #ifndef STR912_ETH_IRQ_PRIORITY
67  #define STR912_ETH_IRQ_PRIORITY 15
68 #elif (STR912_ETH_IRQ_PRIORITY < 0)
69  #error STR912_ETH_IRQ_PRIORITY parameter is not valid
70 #endif
71 
72 //ENET_SCR register
73 #define ENET_SCR_TX_FIFO_SIZE 0xF0000000
74 #define ENET_SCR_TX_IO_DATA_WIDTH 0x0C000000
75 #define ENET_SCR_TX_CHAN_STATUS 0x03000000
76 #define ENET_SCR_RX_FIFO_SIZE 0x00F00000
77 #define ENET_SCR_RX_IO_DATA_WIDTH 0x000C0000
78 #define ENET_SCR_RX_CHAN_STATUS 0x00030000
79 #define ENET_SCR_TX_MAX_BURST_SIZE 0x000000C0
80 #define ENET_SCR_RX_MAX_BURST_SIZE 0x00000030
81 #define ENET_SCR_LOOPB 0x00000002
82 #define ENET_SCR_SRESET 0x00000001
83 
84 //ENET_IER register
85 #define ENET_IER_TX_CURR_DONE_EN 0x80000000
86 #define ENET_IER_MAC_802_3_INT_EN 0x10000000
87 #define ENET_IER_TX_MERR_INT_EN 0x02000000
88 #define ENET_IER_TX_DONE_EN 0x00800000
89 #define ENET_IER_TX_NEXT_EN 0x00400000
90 #define ENET_IER_TX_TO_EN 0x00080000
91 #define ENET_IER_TX_ENTRY_EN 0x00040000
92 #define ENET_IER_TX_FULL_EN 0x00020000
93 #define ENET_IER_TX_EMPTY_EN 0x00010000
94 #define ENET_IER_RX_CURR_DONE_EN 0x00008000
95 #define ENET_IER_RX_MERR_INT_EN 0x00000200
96 #define ENET_IER_RX_DONE_EN 0x00000080
97 #define ENET_IER_RX_NEXT_EN 0x00000040
98 #define ENET_IER_PACKET_LOST_EN 0x00000020
99 #define ENET_IER_RX_TO_EN 0x00000008
100 #define ENET_IER_RX_ENTRY_EN 0x00000004
101 #define ENET_IER_RX_FULL_EN 0x00000002
102 #define ENET_IER_RX_EMPTY_EN 0x00000001
103 
104 //ENET_ISR register
105 #define ENET_ISR_TX_CURR_DONE 0x80000000
106 #define ENET_ISR_MAC_802_3_INT 0x10000000
107 #define ENET_ISR_TX_MERR_INT 0x02000000
108 #define ENET_ISR_TX_DONE 0x00800000
109 #define ENET_ISR_TX_NEXT 0x00400000
110 #define ENET_ISR_TX_TO 0x00080000
111 #define ENET_ISR_TX_ENTRY 0x00040000
112 #define ENET_ISR_TX_FULL 0x00020000
113 #define ENET_ISR_TX_EMPTY 0x00010000
114 #define ENET_ISR_RX_CURR_DONE 0x00008000
115 #define ENET_ISR_RX_MERR_INT 0x00000200
116 #define ENET_ISR_RX_DONE 0x00000080
117 #define ENET_ISR_RX_NEXT 0x00000040
118 #define ENET_ISR_PACKET_LOST 0x00000020
119 #define ENET_ISR_RX_TO 0x00000008
120 #define ENET_ISR_RX_ENTRY 0x00000004
121 #define ENET_ISR_RX_FULL 0x00000002
122 #define ENET_ISR_RX_EMPTY 0x00000001
123 
124 //ENET_CCR register
125 #define ENET_CCR_SEL_CLK 0x0000000C
126 
127 #define ENET_CCR_SEL_CLK_0 0x00000000
128 #define ENET_CCR_SEL_CLK_1 0x00000004
129 
130 //ENET_RXSTR register
131 #define ENET_RXSTR_DFETCH_DLY 0x00FFFF00
132 #define ENET_RXSTR_COLL_SEEN 0x00000080
133 #define ENET_RXSTR_RUNT_FRAME 0x00000040
134 #define ENET_RXSTR_FILTER_FAIL 0x00000020
135 #define ENET_RXSTR_START_FETCH 0x00000004
136 #define ENET_RXSTR_DMA_EN 0x00000001
137 
138 #define ENET_RXSTR_DFETCH_DLY_DEFAULT 0x00800000
139 
140 //ENET_TXSTR register
141 #define ENET_TXSTR_DFETCH_DLY 0x00FFFF00
142 #define ENET_TXSTR_UNDER_RUN 0x00000020
143 #define ENET_TXSTR_START_FETCH 0x00000004
144 #define ENET_TXSTR_DMA_EN 0x00000001
145 
146 #define ENET_TXSTR_DFETCH_DLY_DEFAULT 0x00800000
147 
148 //ENET_MCR register
149 #define ENET_MCR_RA 0x80000000
150 #define ENET_MCR_EN 0x40000000
151 #define ENET_MCR_PS 0x03000000
152 #define ENET_MCR_DRO 0x00800000
153 #define ENET_MCR_LM 0x00600000
154 #define ENET_MCR_FDM 0x00100000
155 #define ENET_MCR_AFM 0x000E0000
156 #define ENET_MCR_PWF 0x00010000
157 #define ENET_MCR_VFM 0x00008000
158 #define ENET_MCR_ELC 0x00001000
159 #define ENET_MCR_DBF 0x00000800
160 #define ENET_MCR_DPR 0x00000400
161 #define ENET_MCR_RVFF 0x00000200
162 #define ENET_MCR_APR 0x00000100
163 #define ENET_MCR_BL 0x000000C0
164 #define ENET_MCR_DCE 0x00000020
165 #define ENET_MCR_RVBE 0x00000010
166 #define ENET_MCR_TE 0x00000008
167 #define ENET_MCR_RE 0x00000004
168 #define ENET_MCR_RCFA 0x00000001
169 
170 #define ENET_MCR_PS_0 0x00000000
171 #define ENET_MCR_PS_1 0x01000000
172 
173 #define ENET_MCR_AFM_0 0x00000000
174 #define ENET_MCR_AFM_1 0x00020000
175 #define ENET_MCR_AFM_2 0x00040000
176 #define ENET_MCR_AFM_3 0x00060000
177 #define ENET_MCR_AFM_4 0x00080000
178 #define ENET_MCR_AFM_5 0x000A0000
179 #define ENET_MCR_AFM_6 0x000C0000
180 #define ENET_MCR_AFM_7 0x000E0000
181 
182 #define ENET_MCR_BL_0 0x00000000
183 #define ENET_MCR_BL_1 0x00000040
184 #define ENET_MCR_BL_2 0x00000080
185 #define ENET_MCR_BL_3 0x000000C0
186 
187 //ENET_MIIA register
188 #define ENET_MIIA_PADDR 0x0000F800
189 #define ENET_MIIA_RADDR 0x000007C0
190 #define ENET_MIIA_PR 0x00000004
191 #define ENET_MIIA_WR 0x00000002
192 #define ENET_MIIA_BUSY 0x00000001
193 
194 //ENET_MIID register
195 #define ENET_MIID_RDATA 0x0000FFFF
196 
197 //TX DMA descriptor (control word)
198 #define ENET_TDES_CTRL_DLY_EN 0x00008000
199 #define ENET_TDES_CTRL_NXT_EN 0x00004000
200 #define ENET_TDES_CTRL_CONT_EN 0x00001000
201 #define ENET_TDES_CTRL_FL 0x00000FFF
202 
203 //TX DMA descriptor (start address)
204 #define ENET_TDES_START_ADDR 0xFFFFFFFC
205 #define ENET_TDES_START_FIX_ADDR 0x00000002
206 #define ENET_TDES_START_WRAP_EN 0x00000001
207 
208 //TX DMA descriptor (next descriptor address)
209 #define ENET_TDES_NEXT_ADDR 0xFFFFFFFC
210 #define ENET_TDES_NEXT_NPOL_EN 0x00000001
211 
212 //TX DMA descriptor (status word)
213 #define ENET_TDES_STATUS_PR 0x80000000
214 #define ENET_TDES_STATUS_BC 0x7FFC0000
215 #define ENET_TDES_STATUS_VALID 0x00010000
216 #define ENET_TDES_STATUS_CC 0x00003C00
217 #define ENET_TDES_STATUS_LCO 0x00000200
218 #define ENET_TDES_STATUS_DEF 0x00000100
219 #define ENET_TDES_STATUS_UR 0x00000080
220 #define ENET_TDES_STATUS_EC 0x00000040
221 #define ENET_TDES_STATUS_LC 0x00000020
222 #define ENET_TDES_STATUS_ED 0x00000010
223 #define ENET_TDES_STATUS_LOC 0x00000008
224 #define ENET_TDES_STATUS_NC 0x00000004
225 #define ENET_TDES_STATUS_FA 0x00000001
226 
227 //RX DMA descriptor (control word)
228 #define ENET_RDES_CTRL_DLY_EN 0x00008000
229 #define ENET_RDES_CTRL_NXT_EN 0x00004000
230 #define ENET_RDES_CTRL_CONT_EN 0x00001000
231 #define ENET_RDES_CTRL_FL 0x00000FFF
232 
233 //RX DMA descriptor (start address)
234 #define ENET_RDES_START_ADDR 0xFFFFFFFC
235 #define ENET_RDES_START_FIX_ADDR 0x00000002
236 #define ENET_RDES_START_WRAP_EN 0x00000001
237 
238 //RX DMA descriptor (next descriptor address)
239 #define ENET_RDES_NEXT_ADDR 0xFFFFFFFC
240 #define ENET_RDES_NEXT_NPOL_EN 0x00000001
241 
242 //RX DMA descriptor (status word)
243 #define ENET_RDES_STATUS_FA 0x80000000
244 #define ENET_RDES_STATUS_PF 0x40000000
245 #define ENET_RDES_STATUS_FF 0x20000000
246 #define ENET_RDES_STATUS_BF 0x10000000
247 #define ENET_RDES_STATUS_MCF 0x08000000
248 #define ENET_RDES_STATUS_UCF 0x04000000
249 #define ENET_RDES_STATUS_CF 0x02000000
250 #define ENET_RDES_STATUS_LE 0x01000000
251 #define ENET_RDES_STATUS_VL2 0x00800000
252 #define ENET_RDES_STATUS_VL1 0x00400000
253 #define ENET_RDES_STATUS_CE 0x00200000
254 #define ENET_RDES_STATUS_EB 0x00100000
255 #define ENET_RDES_STATUS_ME 0x00080000
256 #define ENET_RDES_STATUS_FT 0x00040000
257 #define ENET_RDES_STATUS_LC 0x00020000
258 #define ENET_RDES_STATUS_VALID 0x00010000
259 #define ENET_RDES_STATUS_RF 0x00008000
260 #define ENET_RDES_STATUS_WT 0x00004000
261 #define ENET_RDES_STATUS_FCI 0x00002000
262 #define ENET_RDES_STATUS_OL 0x00001000
263 #define ENET_RDES_STATUS_FL 0x000007FF
264 
265 //Error mask
266 #define ENET_RDES_STATUS_ERROR (ENET_RDES_STATUS_FA | \
267  ENET_RDES_STATUS_LE | ENET_RDES_STATUS_CE | \
268  ENET_RDES_STATUS_EB | ENET_RDES_STATUS_ME | \
269  ENET_RDES_STATUS_LC | ENET_RDES_STATUS_RF | \
270  ENET_RDES_STATUS_WT | ENET_RDES_STATUS_OL)
271 
272 //C++ guard
273 #ifdef __cplusplus
274 extern "C" {
275 #endif
276 
277 
278 /**
279  * @brief Transmit DMA descriptor
280  **/
281 
282 typedef struct
283 {
284  uint32_t ctrl;
285  uint32_t start;
286  uint32_t next;
287  uint32_t status;
289 
290 
291 /**
292  * @brief Receive DMA descriptor
293  **/
294 
295 typedef struct
296 {
297  uint32_t ctrl;
298  uint32_t start;
299  uint32_t next;
300  uint32_t status;
302 
303 
304 //STR912 Ethernet MAC driver
305 extern const NicDriver str912EthDriver;
306 
307 //STR912 Ethernet MAC related functions
309 void str912EthInitGpio(NetInterface *interface);
310 void str912EthInitDmaDesc(NetInterface *interface);
311 
312 void str912EthTick(NetInterface *interface);
313 
314 void str912EthEnableIrq(NetInterface *interface);
315 void str912EthDisableIrq(NetInterface *interface);
316 void str912EthEventHandler(NetInterface *interface);
317 
319  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
320 
322 
325 
326 void str912EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
327  uint8_t regAddr, uint16_t data);
328 
329 uint16_t str912EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
330  uint8_t regAddr);
331 
332 uint32_t str912EthCalcCrc(const void *data, size_t length);
333 
334 //C++ guard
335 #ifdef __cplusplus
336 }
337 #endif
338 
339 #endif
error_t str912EthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t length
Definition: coap_common.h:190
uint8_t opcode
Definition: dns_common.h:172
void str912EthTick(NetInterface *interface)
STR912 Ethernet MAC timer handler.
uint8_t data[]
Definition: ethernet.h:209
void str912EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t str912EthInit(NetInterface *interface)
STR912 Ethernet MAC initialization.
void str912EthEventHandler(NetInterface *interface)
STR912 Ethernet MAC event handler.
error_t str912EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
const NicDriver str912EthDriver
STR912 Ethernet MAC driver.
uint16_t str912EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint32_t str912EthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t
Error codes.
Definition: error.h:42
void str912EthInitGpio(NetInterface *interface)
void str912EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
uint16_t regAddr
Transmit DMA descriptor.
void str912EthDisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
void str912EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t str912EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive DMA descriptor.
error_t str912EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
NIC driver.
Definition: nic.h:257