str912_eth_driver.h
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1 /**
2  * @file str912_eth_driver.h
3  * @brief STR9 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _STR912_ETH_DRIVER_H
30 #define _STR912_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef STR912_ETH_TX_BUFFER_COUNT
37  #define STR912_ETH_TX_BUFFER_COUNT 2
38 #elif (STR912_ETH_TX_BUFFER_COUNT < 1)
39  #error STR912_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef STR912_ETH_TX_BUFFER_SIZE
44  #define STR912_ETH_TX_BUFFER_SIZE 1536
45 #elif (STR912_ETH_TX_BUFFER_SIZE != 1536)
46  #error STR912_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef STR912_ETH_RX_BUFFER_COUNT
51  #define STR912_ETH_RX_BUFFER_COUNT 4
52 #elif (STR912_ETH_RX_BUFFER_COUNT < 1)
53  #error STR912_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef STR912_ETH_RX_BUFFER_SIZE
58  #define STR912_ETH_RX_BUFFER_SIZE 1536
59 #elif (STR912_ETH_RX_BUFFER_SIZE != 1536)
60  #error STR912_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef STR912_ETH_IRQ_PRIORITY
65  #define STR912_ETH_IRQ_PRIORITY 15
66 #elif (STR912_ETH_IRQ_PRIORITY < 0)
67  #error STR912_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //ENET_SCR register
71 #define ENET_SCR_TX_FIFO_SIZE 0xF0000000
72 #define ENET_SCR_TX_IO_DATA_WIDTH 0x0C000000
73 #define ENET_SCR_TX_CHAN_STATUS 0x03000000
74 #define ENET_SCR_RX_FIFO_SIZE 0x00F00000
75 #define ENET_SCR_RX_IO_DATA_WIDTH 0x000C0000
76 #define ENET_SCR_RX_CHAN_STATUS 0x00030000
77 #define ENET_SCR_TX_MAX_BURST_SIZE 0x000000C0
78 #define ENET_SCR_RX_MAX_BURST_SIZE 0x00000030
79 #define ENET_SCR_LOOPB 0x00000002
80 #define ENET_SCR_SRESET 0x00000001
81 
82 //ENET_IER register
83 #define ENET_IER_TX_CURR_DONE_EN 0x80000000
84 #define ENET_IER_MAC_802_3_INT_EN 0x10000000
85 #define ENET_IER_TX_MERR_INT_EN 0x02000000
86 #define ENET_IER_TX_DONE_EN 0x00800000
87 #define ENET_IER_TX_NEXT_EN 0x00400000
88 #define ENET_IER_TX_TO_EN 0x00080000
89 #define ENET_IER_TX_ENTRY_EN 0x00040000
90 #define ENET_IER_TX_FULL_EN 0x00020000
91 #define ENET_IER_TX_EMPTY_EN 0x00010000
92 #define ENET_IER_RX_CURR_DONE_EN 0x00008000
93 #define ENET_IER_RX_MERR_INT_EN 0x00000200
94 #define ENET_IER_RX_DONE_EN 0x00000080
95 #define ENET_IER_RX_NEXT_EN 0x00000040
96 #define ENET_IER_PACKET_LOST_EN 0x00000020
97 #define ENET_IER_RX_TO_EN 0x00000008
98 #define ENET_IER_RX_ENTRY_EN 0x00000004
99 #define ENET_IER_RX_FULL_EN 0x00000002
100 #define ENET_IER_RX_EMPTY_EN 0x00000001
101 
102 //ENET_ISR register
103 #define ENET_ISR_TX_CURR_DONE 0x80000000
104 #define ENET_ISR_MAC_802_3_INT 0x10000000
105 #define ENET_ISR_TX_MERR_INT 0x02000000
106 #define ENET_ISR_TX_DONE 0x00800000
107 #define ENET_ISR_TX_NEXT 0x00400000
108 #define ENET_ISR_TX_TO 0x00080000
109 #define ENET_ISR_TX_ENTRY 0x00040000
110 #define ENET_ISR_TX_FULL 0x00020000
111 #define ENET_ISR_TX_EMPTY 0x00010000
112 #define ENET_ISR_RX_CURR_DONE 0x00008000
113 #define ENET_ISR_RX_MERR_INT 0x00000200
114 #define ENET_ISR_RX_DONE 0x00000080
115 #define ENET_ISR_RX_NEXT 0x00000040
116 #define ENET_ISR_PACKET_LOST 0x00000020
117 #define ENET_ISR_RX_TO 0x00000008
118 #define ENET_ISR_RX_ENTRY 0x00000004
119 #define ENET_ISR_RX_FULL 0x00000002
120 #define ENET_ISR_RX_EMPTY 0x00000001
121 
122 //ENET_CCR register
123 #define ENET_CCR_SEL_CLK 0x0000000C
124 
125 #define ENET_CCR_SEL_CLK_0 0x00000000
126 #define ENET_CCR_SEL_CLK_1 0x00000004
127 
128 //ENET_RXSTR register
129 #define ENET_RXSTR_DFETCH_DLY 0x00FFFF00
130 #define ENET_RXSTR_COLL_SEEN 0x00000080
131 #define ENET_RXSTR_RUNT_FRAME 0x00000040
132 #define ENET_RXSTR_FILTER_FAIL 0x00000020
133 #define ENET_RXSTR_START_FETCH 0x00000004
134 #define ENET_RXSTR_DMA_EN 0x00000001
135 
136 #define ENET_RXSTR_DFETCH_DLY_DEFAULT 0x00800000
137 
138 //ENET_TXSTR register
139 #define ENET_TXSTR_DFETCH_DLY 0x00FFFF00
140 #define ENET_TXSTR_UNDER_RUN 0x00000020
141 #define ENET_TXSTR_START_FETCH 0x00000004
142 #define ENET_TXSTR_DMA_EN 0x00000001
143 
144 #define ENET_TXSTR_DFETCH_DLY_DEFAULT 0x00800000
145 
146 //ENET_MCR register
147 #define ENET_MCR_RA 0x80000000
148 #define ENET_MCR_EN 0x40000000
149 #define ENET_MCR_PS 0x03000000
150 #define ENET_MCR_DRO 0x00800000
151 #define ENET_MCR_LM 0x00600000
152 #define ENET_MCR_FDM 0x00100000
153 #define ENET_MCR_AFM 0x000E0000
154 #define ENET_MCR_PWF 0x00010000
155 #define ENET_MCR_VFM 0x00008000
156 #define ENET_MCR_ELC 0x00001000
157 #define ENET_MCR_DBF 0x00000800
158 #define ENET_MCR_DPR 0x00000400
159 #define ENET_MCR_RVFF 0x00000200
160 #define ENET_MCR_APR 0x00000100
161 #define ENET_MCR_BL 0x000000C0
162 #define ENET_MCR_DCE 0x00000020
163 #define ENET_MCR_RVBE 0x00000010
164 #define ENET_MCR_TE 0x00000008
165 #define ENET_MCR_RE 0x00000004
166 #define ENET_MCR_RCFA 0x00000001
167 
168 #define ENET_MCR_PS_0 0x00000000
169 #define ENET_MCR_PS_1 0x01000000
170 
171 #define ENET_MCR_AFM_0 0x00000000
172 #define ENET_MCR_AFM_1 0x00020000
173 #define ENET_MCR_AFM_2 0x00040000
174 #define ENET_MCR_AFM_3 0x00060000
175 #define ENET_MCR_AFM_4 0x00080000
176 #define ENET_MCR_AFM_5 0x000A0000
177 #define ENET_MCR_AFM_6 0x000C0000
178 #define ENET_MCR_AFM_7 0x000E0000
179 
180 #define ENET_MCR_BL_0 0x00000000
181 #define ENET_MCR_BL_1 0x00000040
182 #define ENET_MCR_BL_2 0x00000080
183 #define ENET_MCR_BL_3 0x000000C0
184 
185 //ENET_MIIA register
186 #define ENET_MIIA_PADDR 0x0000F800
187 #define ENET_MIIA_RADDR 0x000007C0
188 #define ENET_MIIA_PR 0x00000004
189 #define ENET_MIIA_WR 0x00000002
190 #define ENET_MIIA_BUSY 0x00000001
191 
192 //ENET_MIID register
193 #define ENET_MIID_RDATA 0x0000FFFF
194 
195 //TX DMA descriptor (control word)
196 #define ENET_TDES_CTRL_DLY_EN 0x00008000
197 #define ENET_TDES_CTRL_NXT_EN 0x00004000
198 #define ENET_TDES_CTRL_CONT_EN 0x00001000
199 #define ENET_TDES_CTRL_FL 0x00000FFF
200 
201 //TX DMA descriptor (start address)
202 #define ENET_TDES_START_ADDR 0xFFFFFFFC
203 #define ENET_TDES_START_FIX_ADDR 0x00000002
204 #define ENET_TDES_START_WRAP_EN 0x00000001
205 
206 //TX DMA descriptor (next descriptor address)
207 #define ENET_TDES_NEXT_ADDR 0xFFFFFFFC
208 #define ENET_TDES_NEXT_NPOL_EN 0x00000001
209 
210 //TX DMA descriptor (status word)
211 #define ENET_TDES_STATUS_PR 0x80000000
212 #define ENET_TDES_STATUS_BC 0x7FFC0000
213 #define ENET_TDES_STATUS_VALID 0x00010000
214 #define ENET_TDES_STATUS_CC 0x00003C00
215 #define ENET_TDES_STATUS_LCO 0x00000200
216 #define ENET_TDES_STATUS_DEF 0x00000100
217 #define ENET_TDES_STATUS_UR 0x00000080
218 #define ENET_TDES_STATUS_EC 0x00000040
219 #define ENET_TDES_STATUS_LC 0x00000020
220 #define ENET_TDES_STATUS_ED 0x00000010
221 #define ENET_TDES_STATUS_LOC 0x00000008
222 #define ENET_TDES_STATUS_NC 0x00000004
223 #define ENET_TDES_STATUS_FA 0x00000001
224 
225 //RX DMA descriptor (control word)
226 #define ENET_RDES_CTRL_DLY_EN 0x00008000
227 #define ENET_RDES_CTRL_NXT_EN 0x00004000
228 #define ENET_RDES_CTRL_CONT_EN 0x00001000
229 #define ENET_RDES_CTRL_FL 0x00000FFF
230 
231 //RX DMA descriptor (start address)
232 #define ENET_RDES_START_ADDR 0xFFFFFFFC
233 #define ENET_RDES_START_FIX_ADDR 0x00000002
234 #define ENET_RDES_START_WRAP_EN 0x00000001
235 
236 //RX DMA descriptor (next descriptor address)
237 #define ENET_RDES_NEXT_ADDR 0xFFFFFFFC
238 #define ENET_RDES_NEXT_NPOL_EN 0x00000001
239 
240 //RX DMA descriptor (status word)
241 #define ENET_RDES_STATUS_FA 0x80000000
242 #define ENET_RDES_STATUS_PF 0x40000000
243 #define ENET_RDES_STATUS_FF 0x20000000
244 #define ENET_RDES_STATUS_BF 0x10000000
245 #define ENET_RDES_STATUS_MCF 0x08000000
246 #define ENET_RDES_STATUS_UCF 0x04000000
247 #define ENET_RDES_STATUS_CF 0x02000000
248 #define ENET_RDES_STATUS_LE 0x01000000
249 #define ENET_RDES_STATUS_VL2 0x00800000
250 #define ENET_RDES_STATUS_VL1 0x00400000
251 #define ENET_RDES_STATUS_CE 0x00200000
252 #define ENET_RDES_STATUS_EB 0x00100000
253 #define ENET_RDES_STATUS_ME 0x00080000
254 #define ENET_RDES_STATUS_FT 0x00040000
255 #define ENET_RDES_STATUS_LC 0x00020000
256 #define ENET_RDES_STATUS_VALID 0x00010000
257 #define ENET_RDES_STATUS_RF 0x00008000
258 #define ENET_RDES_STATUS_WT 0x00004000
259 #define ENET_RDES_STATUS_FCI 0x00002000
260 #define ENET_RDES_STATUS_OL 0x00001000
261 #define ENET_RDES_STATUS_FL 0x000007FF
262 
263 //Error mask
264 #define ENET_RDES_STATUS_ERROR (ENET_RDES_STATUS_FA | \
265  ENET_RDES_STATUS_LE | ENET_RDES_STATUS_CE | \
266  ENET_RDES_STATUS_EB | ENET_RDES_STATUS_ME | \
267  ENET_RDES_STATUS_LC | ENET_RDES_STATUS_RF | \
268  ENET_RDES_STATUS_WT | ENET_RDES_STATUS_OL)
269 
270 //C++ guard
271 #ifdef __cplusplus
272  extern "C" {
273 #endif
274 
275 
276 /**
277  * @brief Transmit DMA descriptor
278  **/
279 
280 typedef struct
281 {
282  uint32_t ctrl;
283  uint32_t start;
284  uint32_t next;
285  uint32_t status;
287 
288 
289 /**
290  * @brief Receive DMA descriptor
291  **/
292 
293 typedef struct
294 {
295  uint32_t ctrl;
296  uint32_t start;
297  uint32_t next;
298  uint32_t status;
300 
301 
302 //STR912 Ethernet MAC driver
303 extern const NicDriver str912EthDriver;
304 
305 //STR912 Ethernet MAC related functions
307 void str912EthInitGpio(NetInterface *interface);
308 void str912EthInitDmaDesc(NetInterface *interface);
309 
310 void str912EthTick(NetInterface *interface);
311 
312 void str912EthEnableIrq(NetInterface *interface);
313 void str912EthDisableIrq(NetInterface *interface);
314 void str912EthEventHandler(NetInterface *interface);
315 
317  const NetBuffer *buffer, size_t offset);
318 
320 
323 
324 void str912EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
325 uint16_t str912EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
326 
327 uint32_t str912EthCalcCrc(const void *data, size_t length);
328 
329 //C++ guard
330 #ifdef __cplusplus
331  }
332 #endif
333 
334 #endif
void str912EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t str912EthInit(NetInterface *interface)
STR912 Ethernet MAC initialization.
void str912EthTick(NetInterface *interface)
STR912 Ethernet MAC timer handler.
void str912EthInitGpio(NetInterface *interface)
const NicDriver str912EthDriver
STR912 Ethernet MAC driver.
void str912EthEventHandler(NetInterface *interface)
STR912 Ethernet MAC event handler.
uint32_t str912EthCalcCrc(const void *data, size_t length)
CRC calculation.
void str912EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
Transmit DMA descriptor.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void str912EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t regAddr
void str912EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t str912EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t
Error codes.
Definition: error.h:40
Receive DMA descriptor.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t str912EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t str912EthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t length
Definition: dtls_misc.h:140
error_t str912EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint16_t str912EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Network interface controller abstraction layer.