str912_eth_driver.c
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1 /**
2  * @file str912_eth_driver.c
3  * @brief STR9 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "91x_lib.h"
34 #include "core/net.h"
36 #include "debug.h"
37 
38 //Underlying network interface
39 static NetInterface *nicDriverInterface;
40 
41 //IAR EWARM compiler?
42 #if defined(__ICCARM__)
43 
44 //Transmit buffer
45 #pragma data_alignment = 4
47 //Receive buffer
48 #pragma data_alignment = 4
50 //Transmit DMA descriptors
51 #pragma data_alignment = 4
53 //Receive DMA descriptors
54 #pragma data_alignment = 4
56 
57 //Keil MDK-ARM or GCC compiler?
58 #else
59 
60 //Transmit buffer
62  __attribute__((aligned(4)));
63 //Receive buffer
65  __attribute__((aligned(4)));
66 //Transmit DMA descriptors
68  __attribute__((aligned(4)));
69 //Receive DMA descriptors
71  __attribute__((aligned(4)));
72 
73 #endif
74 
75 //Pointer to the current TX DMA descriptor
76 static Str912TxDmaDesc *txCurDmaDesc;
77 //Pointer to the current RX DMA descriptor
78 static Str912RxDmaDesc *rxCurDmaDesc;
79 
80 
81 /**
82  * @brief STR912 Ethernet MAC driver
83  **/
84 
86 {
88  ETH_MTU,
99  TRUE,
100  TRUE,
101  TRUE,
102  FALSE
103 };
104 
105 
106 /**
107  * @brief STR912 Ethernet MAC initialization
108  * @param[in] interface Underlying network interface
109  * @return Error code
110  **/
111 
113 {
114  error_t error;
115 
116  //Debug message
117  TRACE_INFO("Initializing STR912 Ethernet MAC...\r\n");
118 
119  //Save underlying network interface
120  nicDriverInterface = interface;
121 
122  //GPIO configuration
123  str912EthInitGpio(interface);
124 
125  //Enable Ethernet MAC clock
126  SCU_AHBPeriphClockConfig(__ENET, ENABLE);
127 
128  //Reset Ethernet MAC peripheral
129  SCU_AHBPeriphReset(__ENET, ENABLE);
130  SCU_AHBPeriphReset(__ENET, DISABLE);
131 
132  //MAC DMA software reset
133  ENET_DMA->SCR |= ENET_SCR_SRESET;
134  ENET_DMA->SCR &= ~ENET_SCR_SRESET;
135 
136  //Use default MAC configuration
137  ENET_MAC->MCR = ENET_MCR_AFM_1 | ENET_MCR_RVFF |
139 
140  //Adjust HCLK divider depending on system clock frequency
141  if(SCU_GetHCLKFreqValue() > 50000)
142  ENET_MAC->MCR |= ENET_MCR_PS_1;
143 
144  //PHY transceiver initialization
145  error = interface->phyDriver->init(interface);
146  //Failed to initialize PHY transceiver?
147  if(error)
148  return error;
149 
150  //Set the MAC address
151  ENET_MAC->MAL = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
152  ENET_MAC->MAH = interface->macAddr.w[2];
153 
154  //Initialize hash table
155  ENET_MAC->MCLA = 0;
156  ENET_MAC->MCHA = 0;
157 
158  //DMA configuration
159  //ENET_DMA->SCR = 0;
160 
161  //Force a DMA abort
162  ENET_DMA->TXSTR |= ENET_TXSTR_DMA_EN;
163  ENET_DMA->RXSTR |= ENET_RXSTR_DMA_EN;
164 
165  //Set descriptor fetch delay
167  ENET_DMA->RXSTR = ENET_RXSTR_DFETCH_DLY_DEFAULT;
168 
169  //Initialize DMA descriptor lists
170  str912EthInitDmaDesc(interface);
171 
172  //Clear interrupt flags
174  //Configure DMA interrupts as desired
176 
177  //Configure Ethernet interrupt priority
178  VIC_Config(ENET_ITLine, VIC_IRQ, STR912_ETH_IRQ_PRIORITY);
179 
180  //Enable MAC transmission and reception
181  ENET_MAC->MCR |= ENET_MCR_TE | ENET_MCR_RE;
182  //Instruct the DMA to poll the receive descriptor list
183  ENET_DMA->RXSTR |= ENET_RXSTR_START_FETCH;
184 
185  //Accept any packets from the upper layer
186  osSetEvent(&interface->nicTxEvent);
187 
188  //Successful initialization
189  return NO_ERROR;
190 }
191 
192 
193 //STR-E912 evaluation board?
194 #if defined(USE_STR_E912)
195 
196 /**
197  * @brief GPIO configuration
198  * @param[in] interface Underlying network interface
199  **/
200 
201 void str912EthInitGpio(NetInterface *interface)
202 {
203  GPIO_InitTypeDef GPIO_InitStructure;
204 
205  //Enable GPIO clocks
206  SCU_APBPeriphClockConfig(__GPIO0, ENABLE);
207  SCU_APBPeriphClockConfig(__GPIO1, ENABLE);
208  SCU_APBPeriphClockConfig(__GPIO5, ENABLE);
209 
210  //Enable MII_PHYCLK clock
211  SCU_PHYCLKConfig(ENABLE);
212 
213  //Configure MII_TX_CLK (P0.0), MII_RXD0 (P0.2), MII_RXD1 (P0.3), MII_RXD2 (P0.4),
214  //MII_RXD3 (P0.5), MII_RX_CLK (P0.6) and MII_RX_DV (P0.7)
215  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_3 |
216  GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
217 
218  GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
219  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
220  GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
221  GPIO_Init(GPIO0, &GPIO_InitStructure);
222 
223  //Configure MII_RX_ER (P1.0), MII_COL (P1.5) and MII_CRS (P1.6)
224  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_5 | GPIO_Pin_6;
225  GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
226  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
227  GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
228  GPIO_Init(GPIO1, &GPIO_InitStructure);
229 
230  //Configure MII_TXD0 (P1.1), MII_TXD1 (P1.2), MII_TXD2 (P1.3),
231  //MII_TXD3 (P1.4) and MII_MDC (P1.7)
232  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |
233  GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_7;
234 
235  GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
236  GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
237  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
238  GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
239  GPIO_Init(GPIO1, &GPIO_InitStructure);
240 
241  //Configure MII_PHYCLK (P5.2) and MII_TX_EN (P5.3)
242  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
243  GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
244  GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
245  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
246  GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
247  GPIO_Init(GPIO5, &GPIO_InitStructure);
248 }
249 
250 #endif
251 
252 
253 /**
254  * @brief Initialize DMA descriptor lists
255  * @param[in] interface Underlying network interface
256  **/
257 
259 {
260  uint_t i;
261 
262  //Initialize TX DMA descriptor list
263  for(i = 0; i < STR912_ETH_TX_BUFFER_COUNT; i++)
264  {
265  //Control word
267  //Transmit buffer address
268  txDmaDesc[i].start = (uint32_t) txBuffer[i];
269  //Next descriptor address
270  txDmaDesc[i].next = (uint32_t) &txDmaDesc[i + 1] | ENET_TDES_NEXT_NPOL_EN;
271  //Status word
272  txDmaDesc[i].status = 0;
273  }
274 
275  //The last descriptor is chained to the first entry
276  txDmaDesc[i - 1].next = (uint32_t) &txDmaDesc[0] | ENET_TDES_NEXT_NPOL_EN;
277  //Point to the very first descriptor
278  txCurDmaDesc = &txDmaDesc[0];
279 
280  //Initialize RX DMA descriptor list
281  for(i = 0; i < STR912_ETH_RX_BUFFER_COUNT; i++)
282  {
283  //Control word
285  //Receive buffer address
286  rxDmaDesc[i].start = (uint32_t) rxBuffer[i];
287  //Next descriptor address
288  rxDmaDesc[i].next = (uint32_t) &rxDmaDesc[i + 1] | ENET_RDES_NEXT_NPOL_EN;
289  //Status word
290  rxDmaDesc[i].status = ENET_RDES_STATUS_VALID;
291  }
292 
293  //The last descriptor is chained to the first entry
294  rxDmaDesc[i - 1].next = (uint32_t) &rxDmaDesc[0] | ENET_RDES_NEXT_NPOL_EN;
295  //Point to the very first descriptor
296  rxCurDmaDesc = &rxDmaDesc[0];
297 
298  //Start location of the TX descriptor list
299  ENET_DMA->TXNDAR = (uint32_t) txDmaDesc | ENET_TDES_NEXT_NPOL_EN;
300  //Start location of the RX descriptor list
301  ENET_DMA->RXNDAR = (uint32_t) rxDmaDesc | ENET_RDES_NEXT_NPOL_EN;
302 }
303 
304 
305 /**
306  * @brief STR912 Ethernet MAC timer handler
307  *
308  * This routine is periodically called by the TCP/IP stack to
309  * handle periodic operations such as polling the link state
310  *
311  * @param[in] interface Underlying network interface
312  **/
313 
314 void str912EthTick(NetInterface *interface)
315 {
316  //Handle periodic operations
317  interface->phyDriver->tick(interface);
318 }
319 
320 
321 /**
322  * @brief Enable interrupts
323  * @param[in] interface Underlying network interface
324  **/
325 
327 {
328  //Enable Ethernet MAC interrupts
329  VIC_ITCmd(ENET_ITLine, ENABLE);
330  //Enable Ethernet PHY interrupts
331  interface->phyDriver->enableIrq(interface);
332 }
333 
334 
335 /**
336  * @brief Disable interrupts
337  * @param[in] interface Underlying network interface
338  **/
339 
341 {
342  //Disable Ethernet MAC interrupts
343  VIC_ITCmd(ENET_ITLine, DISABLE);
344  //Disable Ethernet PHY interrupts
345  interface->phyDriver->disableIrq(interface);
346 }
347 
348 
349 /**
350  * @brief STR912 Ethernet MAC interrupt service routine
351  **/
352 
353 void ENET_IRQHandler(void)
354 {
355  bool_t flag;
356  uint32_t status;
357 
358  //Enter interrupt service routine
359  osEnterIsr();
360 
361  //This flag will be set if a higher priority task must be woken
362  flag = FALSE;
363 
364  //Read DMA status register
365  status = ENET_DMA->ISR;
366 
367  //A packet has been transmitted?
368  if(status & ENET_ISR_TX_CURR_DONE)
369  {
370  //Clear TX_CURR_DONE interrupt flag
371  ENET_DMA->ISR = ENET_ISR_TX_CURR_DONE;
372 
373  //Check whether the TX buffer is available for writing
374  if(!(txCurDmaDesc->status & ENET_TDES_STATUS_VALID))
375  {
376  //Notify the TCP/IP stack that the transmitter is ready to send
377  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
378  }
379  }
380 
381  //A packet has been received?
382  if(status & ENET_ISR_RX_CURR_DONE)
383  {
384  //Disable RX_CURR_DONE interrupt
385  ENET_DMA->IER &= ~ENET_IER_RX_CURR_DONE_EN;
386 
387  //Set event flag
388  nicDriverInterface->nicEvent = TRUE;
389  //Notify the TCP/IP stack of the event
390  flag |= osSetEventFromIsr(&netEvent);
391  }
392 
393  //Leave interrupt service routine
394  osExitIsr(flag);
395 }
396 
397 
398 /**
399  * @brief STR912 Ethernet MAC event handler
400  * @param[in] interface Underlying network interface
401  **/
402 
404 {
405  error_t error;
406 
407  //Packet received?
408  if(ENET_DMA->ISR & ENET_ISR_RX_CURR_DONE)
409  {
410  //Clear interrupt flag
411  ENET_DMA->ISR = ENET_ISR_RX_CURR_DONE;
412 
413  //Process all pending packets
414  do
415  {
416  //Read incoming packet
417  error = str912EthReceivePacket(interface);
418 
419  //No more data in the receive buffer?
420  } while(error != ERROR_BUFFER_EMPTY);
421  }
422 
423  //Re-enable DMA interrupts
425 }
426 
427 
428 /**
429  * @brief Send a packet
430  * @param[in] interface Underlying network interface
431  * @param[in] buffer Multi-part buffer containing the data to send
432  * @param[in] offset Offset to the first data byte
433  * @return Error code
434  **/
435 
437  const NetBuffer *buffer, size_t offset)
438 {
439  size_t length;
440 
441  //Retrieve the length of the packet
442  length = netBufferGetLength(buffer) - offset;
443 
444  //Check the frame length
446  {
447  //The transmitter can accept another packet
448  osSetEvent(&interface->nicTxEvent);
449  //Report an error
450  return ERROR_INVALID_LENGTH;
451  }
452 
453  //Make sure the current buffer is available for writing
454  if(txCurDmaDesc->status & ENET_TDES_STATUS_VALID)
455  return ERROR_FAILURE;
456 
457  //Copy user data to the transmit buffer
458  netBufferRead((uint8_t *) (txCurDmaDesc->start & ENET_TDES_START_ADDR),
459  buffer, offset, length);
460 
461  //Write the number of bytes to send
462  txCurDmaDesc->ctrl = ENET_TDES_CTRL_NXT_EN | length;
463  //Give the ownership of the descriptor to the DMA
464  txCurDmaDesc->status = ENET_TDES_STATUS_VALID;
465 
466  //Instruct the DMA to poll the transmit descriptor list
467  ENET_DMA->TXSTR |= ENET_TXSTR_START_FETCH;
468 
469  //Point to the next descriptor in the list
470  txCurDmaDesc = (Str912TxDmaDesc *) (txCurDmaDesc->next & ENET_TDES_NEXT_ADDR);
471 
472  //Check whether the next buffer is available for writing
473  if(!(txCurDmaDesc->status & ENET_TDES_STATUS_VALID))
474  {
475  //The transmitter can accept another packet
476  osSetEvent(&interface->nicTxEvent);
477  }
478 
479  //Data successfully written
480  return NO_ERROR;
481 }
482 
483 
484 /**
485  * @brief Receive a packet
486  * @param[in] interface Underlying network interface
487  * @return Error code
488  **/
489 
491 {
492  error_t error;
493  size_t n;
494  uint8_t *p;
495 
496  //The current buffer is available for reading?
497  if(!(rxCurDmaDesc->status & ENET_RDES_STATUS_VALID))
498  {
499  //Make sure no error occurred
500  if(!(rxCurDmaDesc->status & ENET_RDES_STATUS_ERROR))
501  {
502  //Point to the received frame
503  p = (uint8_t *) (rxCurDmaDesc->start & ENET_RDES_START_ADDR);
504 
505  //Retrieve the length of the frame
506  n = rxCurDmaDesc->status & ENET_RDES_STATUS_FL;
507  //Limit the number of data to read
509 
510  //Pass the packet to the upper layer
511  nicProcessPacket(interface, p, n);
512 
513  //Valid packet received
514  error = NO_ERROR;
515  }
516  else
517  {
518  //The received packet contains an error
519  error = ERROR_INVALID_PACKET;
520  }
521 
522  //Give the ownership of the descriptor back to the DMA
523  rxCurDmaDesc->status = ENET_RDES_STATUS_VALID;
524  //Point to the next descriptor in the list
525  rxCurDmaDesc = (Str912RxDmaDesc *) (rxCurDmaDesc->next & ENET_RDES_NEXT_ADDR);
526  }
527  else
528  {
529  //No more data in the receive buffer
530  error = ERROR_BUFFER_EMPTY;
531  }
532 
533  //Instruct the DMA to poll the receive descriptor list
534  ENET_DMA->RXSTR |= ENET_RXSTR_START_FETCH;
535 
536  //Return status code
537  return error;
538 }
539 
540 
541 /**
542  * @brief Configure MAC address filtering
543  * @param[in] interface Underlying network interface
544  * @return Error code
545  **/
546 
548 {
549  uint_t i;
550  uint_t k;
551  uint32_t crc;
552  uint32_t hashTable[2];
553  MacFilterEntry *entry;
554 
555  //Debug message
556  TRACE_DEBUG("Updating STR912 hash table...\r\n");
557 
558  //Clear hash table
559  hashTable[0] = 0;
560  hashTable[1] = 0;
561 
562  //The MAC address filter contains the list of MAC addresses to accept
563  //when receiving an Ethernet frame
564  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
565  {
566  //Point to the current entry
567  entry = &interface->macAddrFilter[i];
568 
569  //Valid entry?
570  if(entry->refCount > 0)
571  {
572  //Compute CRC over the current MAC address
573  crc = str912EthCalcCrc(&entry->addr, sizeof(MacAddr));
574 
575  //The upper 6 bits in the CRC register are used to index the
576  //contents of the hash table
577  k = (crc >> 26) & 0x3F;
578 
579  //Update hash table contents
580  hashTable[k / 32] |= (1 << (k % 32));
581  }
582  }
583 
584  //Write the hash table
585  ENET_MAC->MCLA = hashTable[0];
586  ENET_MAC->MCHA = hashTable[1];
587 
588  //Debug message
589  TRACE_DEBUG(" ENET_MCLA = %08" PRIX32 "\r\n", ENET_MAC->MCLA);
590  TRACE_DEBUG(" ENET_MCHA = %08" PRIX32 "\r\n", ENET_MAC->MCHA);
591 
592  //Successful processing
593  return NO_ERROR;
594 }
595 
596 
597 /**
598  * @brief Adjust MAC configuration parameters for proper operation
599  * @param[in] interface Underlying network interface
600  * @return Error code
601  **/
602 
604 {
605  uint32_t config;
606 
607  //Read current MAC configuration
608  config = ENET_MAC->MCR;
609 
610  //Half-duplex or full-duplex mode?
611  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
612  {
613  //Full-duplex mode
614  config |= ENET_MCR_FDM;
615  //Enable the reception path during transmission
616  config &= ~ENET_MCR_DRO;
617  }
618  else
619  {
620  //Half-duplex mode
621  config &= ~ENET_MCR_FDM;
622  //Disable the reception path during transmission
623  config |= ENET_MCR_DRO;
624  }
625 
626  //Update MAC configuration register
627  ENET_MAC->MCR = config;
628 
629  //Successful processing
630  return NO_ERROR;
631 }
632 
633 
634 /**
635  * @brief Write PHY register
636  * @param[in] phyAddr PHY address
637  * @param[in] regAddr Register address
638  * @param[in] data Register value
639  **/
640 
641 void str912EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
642 {
643  uint32_t value;
644 
645  //Set up a write operation
647  //PHY address
648  value |= (phyAddr << 11) & ENET_MIIA_PADDR;
649  //Register address
650  value |= (regAddr << 6) & ENET_MIIA_RADDR;
651 
652  //Data to be written in the PHY register
653  ENET_MAC->MIID = data & ENET_MIID_RDATA;
654 
655  //Start a write operation
656  ENET_MAC->MIIA = value;
657  //Wait for the write to complete
658  while(ENET_MAC->MIIA & ENET_MIIA_BUSY);
659 }
660 
661 
662 /**
663  * @brief Read PHY register
664  * @param[in] phyAddr PHY address
665  * @param[in] regAddr Register address
666  * @return Register value
667  **/
668 
669 uint16_t str912EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
670 {
671  uint32_t value;
672 
673  //Set up a read operation
675  //PHY address
676  value |= (phyAddr << 11) & ENET_MIIA_PADDR;
677  //Register address
678  value |= (regAddr << 6) & ENET_MIIA_RADDR;
679 
680  //Start a read operation
681  ENET_MAC->MIIA = value;
682  //Wait for the read to complete
683  while(ENET_MAC->MIIA & ENET_MIIA_BUSY);
684 
685  //Return PHY register contents
686  return ENET_MAC->MIID & ENET_MIID_RDATA;
687 }
688 
689 
690 /**
691  * @brief CRC calculation
692  * @param[in] data Pointer to the data over which to calculate the CRC
693  * @param[in] length Number of bytes to process
694  * @return Resulting CRC value
695  **/
696 
697 uint32_t str912EthCalcCrc(const void *data, size_t length)
698 {
699  uint_t i;
700  uint_t j;
701 
702  //Point to the data over which to calculate the CRC
703  const uint8_t *p = (uint8_t *) data;
704  //CRC preset value
705  uint32_t crc = 0xFFFFFFFF;
706 
707  //Loop through data
708  for(i = 0; i < length; i++)
709  {
710  //The message is processed bit by bit
711  for(j = 0; j < 8; j++)
712  {
713  //Update CRC value
714  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
715  crc = (crc << 1) ^ 0x04C11DB7;
716  else
717  crc = crc << 1;
718  }
719  }
720 
721  //Return CRC value
722  return crc;
723 }
#define ENET_TXSTR_UNDER_RUN
#define txDmaDesc
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ENET_MCR_AFM_1
#define ENET_SCR_SRESET
void str912EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define ENET_MCR_DCE
TCP/IP stack core.
#define ENET_MCR_RE
#define ENET_MCR_TE
Debugging facilities.
#define ENET_TXSTR_DFETCH_DLY_DEFAULT
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define ENET_RDES_NEXT_ADDR
error_t str912EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ENET_MCR_BL_1
Generic error code.
Definition: error.h:43
void str912EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define STR912_ETH_IRQ_PRIORITY
#define rxDmaDesc
#define ENET_MCR_PS_1
#define txBuffer
#define ENET_MIIA_RADDR
uint32_t str912EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define STR912_ETH_TX_BUFFER_COUNT
#define STR912_ETH_RX_BUFFER_SIZE
#define ENET_RDES_CTRL_NXT_EN
#define ENET_TDES_START_ADDR
error_t str912EthReceivePacket(NetInterface *interface)
Receive a packet.
#define ENET_RDES_STATUS_ERROR
void str912EthInitGpio(NetInterface *interface)
#define ENET_ISR_TX_CURR_DONE
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define STR912_ETH_TX_BUFFER_SIZE
#define ENET_RDES_STATUS_FL
#define ENET_RDES_STATUS_VALID
#define STR912_ETH_RX_BUFFER_COUNT
error_t str912EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ENET_TDES_CTRL_NXT_EN
#define ENET_RDES_NEXT_NPOL_EN
#define ENET_IER_RX_CURR_DONE_EN
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
Transmit DMA descriptor.
NIC driver.
Definition: nic.h:161
void ENET_IRQHandler(void)
STR912 Ethernet MAC interrupt service routine.
#define ENET_RXSTR_START_FETCH
#define ENET_MCR_FDM
#define ENET_MIIA_WR
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
void str912EthEventHandler(NetInterface *interface)
STR912 Ethernet MAC event handler.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
error_t str912EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void str912EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
uint16_t str912EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Receive DMA descriptor.
unsigned int uint_t
Definition: compiler_port.h:43
#define ENET_MCR_DRO
__start_packed struct @112 MacAddr
MAC address.
#define ENET_IER_TX_CURR_DONE_EN
#define ENET_TDES_STATUS_VALID
uint8_t data[]
Definition: dtls_misc.h:167
#define ENET_RXSTR_DFETCH_DLY_DEFAULT
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
#define ENET_ISR_RX_CURR_DONE
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define ENET_MCR_RVBE
STR9 Ethernet MAC controller.
#define ENET_TDES_NEXT_NPOL_EN
#define osExitIsr(flag)
#define osEnterIsr()
#define ENET_RXSTR_DMA_EN
void str912EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define ENET_TXSTR_DMA_EN
error_t str912EthInit(NetInterface *interface)
STR912 Ethernet MAC initialization.
#define ENET_MIID_RDATA
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define ENET_TDES_NEXT_ADDR
const NicDriver str912EthDriver
STR912 Ethernet MAC driver.
#define ENET_MCR_RVFF
#define FALSE
Definition: os_port.h:44
#define ENET_MIIA_BUSY
int bool_t
Definition: compiler_port.h:47
void str912EthTick(NetInterface *interface)
STR912 Ethernet MAC timer handler.
#define ENET_TXSTR_START_FETCH
#define ENET_RDES_START_ADDR
#define ENET_MIIA_PADDR
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98