str912_eth_driver.c
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1 /**
2  * @file str912_eth_driver.c
3  * @brief STR9 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "91x_lib.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit DMA descriptors
53 #pragma data_alignment = 4
55 //Receive DMA descriptors
56 #pragma data_alignment = 4
58 
59 //Keil MDK-ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
64  __attribute__((aligned(4)));
65 //Receive buffer
67  __attribute__((aligned(4)));
68 //Transmit DMA descriptors
70  __attribute__((aligned(4)));
71 //Receive DMA descriptors
73  __attribute__((aligned(4)));
74 
75 #endif
76 
77 //Pointer to the current TX DMA descriptor
78 static Str912TxDmaDesc *txCurDmaDesc;
79 //Pointer to the current RX DMA descriptor
80 static Str912RxDmaDesc *rxCurDmaDesc;
81 
82 
83 /**
84  * @brief STR912 Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief STR912 Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117 
118  //Debug message
119  TRACE_INFO("Initializing STR912 Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //GPIO configuration
125  str912EthInitGpio(interface);
126 
127  //Enable Ethernet MAC clock
128  SCU_AHBPeriphClockConfig(__ENET, ENABLE);
129 
130  //Reset Ethernet MAC peripheral
131  SCU_AHBPeriphReset(__ENET, ENABLE);
132  SCU_AHBPeriphReset(__ENET, DISABLE);
133 
134  //MAC DMA software reset
135  ENET_DMA->SCR |= ENET_SCR_SRESET;
136  ENET_DMA->SCR &= ~ENET_SCR_SRESET;
137 
138  //Use default MAC configuration
139  ENET_MAC->MCR = ENET_MCR_AFM_1 | ENET_MCR_RVFF |
141 
142  //Adjust HCLK divider depending on system clock frequency
143  if(SCU_GetHCLKFreqValue() > 50000)
144  ENET_MAC->MCR |= ENET_MCR_PS_1;
145 
146  //PHY transceiver initialization
147  error = interface->phyDriver->init(interface);
148  //Failed to initialize PHY transceiver?
149  if(error)
150  return error;
151 
152  //Set the MAC address of the station
153  ENET_MAC->MAL = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
154  ENET_MAC->MAH = interface->macAddr.w[2];
155 
156  //Initialize hash table
157  ENET_MAC->MCLA = 0;
158  ENET_MAC->MCHA = 0;
159 
160  //DMA configuration
161  //ENET_DMA->SCR = 0;
162 
163  //Force a DMA abort
164  ENET_DMA->TXSTR |= ENET_TXSTR_DMA_EN;
165  ENET_DMA->RXSTR |= ENET_RXSTR_DMA_EN;
166 
167  //Set descriptor fetch delay
169  ENET_DMA->RXSTR = ENET_RXSTR_DFETCH_DLY_DEFAULT;
170 
171  //Initialize DMA descriptor lists
172  str912EthInitDmaDesc(interface);
173 
174  //Clear interrupt flags
176  //Configure DMA interrupts as desired
178 
179  //Configure Ethernet interrupt priority
180  VIC_Config(ENET_ITLine, VIC_IRQ, STR912_ETH_IRQ_PRIORITY);
181 
182  //Enable MAC transmission and reception
183  ENET_MAC->MCR |= ENET_MCR_TE | ENET_MCR_RE;
184  //Instruct the DMA to poll the receive descriptor list
185  ENET_DMA->RXSTR |= ENET_RXSTR_START_FETCH;
186 
187  //Accept any packets from the upper layer
188  osSetEvent(&interface->nicTxEvent);
189 
190  //Successful initialization
191  return NO_ERROR;
192 }
193 
194 
195 //STR-E912 evaluation board?
196 #if defined(USE_STR_E912)
197 
198 /**
199  * @brief GPIO configuration
200  * @param[in] interface Underlying network interface
201  **/
202 
203 void str912EthInitGpio(NetInterface *interface)
204 {
205  GPIO_InitTypeDef GPIO_InitStructure;
206 
207  //Enable GPIO clocks
208  SCU_APBPeriphClockConfig(__GPIO0, ENABLE);
209  SCU_APBPeriphClockConfig(__GPIO1, ENABLE);
210  SCU_APBPeriphClockConfig(__GPIO5, ENABLE);
211 
212  //Enable MII_PHYCLK clock
213  SCU_PHYCLKConfig(ENABLE);
214 
215  //Configure MII_TX_CLK (P0.0), MII_RXD0 (P0.2), MII_RXD1 (P0.3), MII_RXD2 (P0.4),
216  //MII_RXD3 (P0.5), MII_RX_CLK (P0.6) and MII_RX_DV (P0.7)
217  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_3 |
218  GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
219 
220  GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
221  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
222  GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
223  GPIO_Init(GPIO0, &GPIO_InitStructure);
224 
225  //Configure MII_RX_ER (P1.0), MII_COL (P1.5) and MII_CRS (P1.6)
226  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_5 | GPIO_Pin_6;
227  GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
228  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
229  GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
230  GPIO_Init(GPIO1, &GPIO_InitStructure);
231 
232  //Configure MII_TXD0 (P1.1), MII_TXD1 (P1.2), MII_TXD2 (P1.3),
233  //MII_TXD3 (P1.4) and MII_MDC (P1.7)
234  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |
235  GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_7;
236 
237  GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
238  GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
239  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
240  GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
241  GPIO_Init(GPIO1, &GPIO_InitStructure);
242 
243  //Configure MII_PHYCLK (P5.2) and MII_TX_EN (P5.3)
244  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
245  GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
246  GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
247  GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
248  GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
249  GPIO_Init(GPIO5, &GPIO_InitStructure);
250 }
251 
252 #endif
253 
254 
255 /**
256  * @brief Initialize DMA descriptor lists
257  * @param[in] interface Underlying network interface
258  **/
259 
261 {
262  uint_t i;
263 
264  //Initialize TX DMA descriptor list
265  for(i = 0; i < STR912_ETH_TX_BUFFER_COUNT; i++)
266  {
267  //Control word
269  //Transmit buffer address
270  txDmaDesc[i].start = (uint32_t) txBuffer[i];
271  //Next descriptor address
272  txDmaDesc[i].next = (uint32_t) &txDmaDesc[i + 1] | ENET_TDES_NEXT_NPOL_EN;
273  //Status word
274  txDmaDesc[i].status = 0;
275  }
276 
277  //The last descriptor is chained to the first entry
278  txDmaDesc[i - 1].next = (uint32_t) &txDmaDesc[0] | ENET_TDES_NEXT_NPOL_EN;
279  //Point to the very first descriptor
280  txCurDmaDesc = &txDmaDesc[0];
281 
282  //Initialize RX DMA descriptor list
283  for(i = 0; i < STR912_ETH_RX_BUFFER_COUNT; i++)
284  {
285  //Control word
287  //Receive buffer address
288  rxDmaDesc[i].start = (uint32_t) rxBuffer[i];
289  //Next descriptor address
290  rxDmaDesc[i].next = (uint32_t) &rxDmaDesc[i + 1] | ENET_RDES_NEXT_NPOL_EN;
291  //Status word
292  rxDmaDesc[i].status = ENET_RDES_STATUS_VALID;
293  }
294 
295  //The last descriptor is chained to the first entry
296  rxDmaDesc[i - 1].next = (uint32_t) &rxDmaDesc[0] | ENET_RDES_NEXT_NPOL_EN;
297  //Point to the very first descriptor
298  rxCurDmaDesc = &rxDmaDesc[0];
299 
300  //Start location of the TX descriptor list
301  ENET_DMA->TXNDAR = (uint32_t) txDmaDesc | ENET_TDES_NEXT_NPOL_EN;
302  //Start location of the RX descriptor list
303  ENET_DMA->RXNDAR = (uint32_t) rxDmaDesc | ENET_RDES_NEXT_NPOL_EN;
304 }
305 
306 
307 /**
308  * @brief STR912 Ethernet MAC timer handler
309  *
310  * This routine is periodically called by the TCP/IP stack to
311  * handle periodic operations such as polling the link state
312  *
313  * @param[in] interface Underlying network interface
314  **/
315 
316 void str912EthTick(NetInterface *interface)
317 {
318  //Handle periodic operations
319  interface->phyDriver->tick(interface);
320 }
321 
322 
323 /**
324  * @brief Enable interrupts
325  * @param[in] interface Underlying network interface
326  **/
327 
329 {
330  //Enable Ethernet MAC interrupts
331  VIC_ITCmd(ENET_ITLine, ENABLE);
332  //Enable Ethernet PHY interrupts
333  interface->phyDriver->enableIrq(interface);
334 }
335 
336 
337 /**
338  * @brief Disable interrupts
339  * @param[in] interface Underlying network interface
340  **/
341 
343 {
344  //Disable Ethernet MAC interrupts
345  VIC_ITCmd(ENET_ITLine, DISABLE);
346  //Disable Ethernet PHY interrupts
347  interface->phyDriver->disableIrq(interface);
348 }
349 
350 
351 /**
352  * @brief STR912 Ethernet MAC interrupt service routine
353  **/
354 
355 void ENET_IRQHandler(void)
356 {
357  bool_t flag;
358  uint32_t status;
359 
360  //Interrupt service routine prologue
361  osEnterIsr();
362 
363  //This flag will be set if a higher priority task must be woken
364  flag = FALSE;
365 
366  //Read DMA status register
367  status = ENET_DMA->ISR;
368 
369  //A packet has been transmitted?
370  if(status & ENET_ISR_TX_CURR_DONE)
371  {
372  //Clear TX_CURR_DONE interrupt flag
373  ENET_DMA->ISR = ENET_ISR_TX_CURR_DONE;
374 
375  //Check whether the TX buffer is available for writing
376  if(!(txCurDmaDesc->status & ENET_TDES_STATUS_VALID))
377  {
378  //Notify the TCP/IP stack that the transmitter is ready to send
379  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
380  }
381  }
382 
383  //A packet has been received?
384  if(status & ENET_ISR_RX_CURR_DONE)
385  {
386  //Disable RX_CURR_DONE interrupt
387  ENET_DMA->IER &= ~ENET_IER_RX_CURR_DONE_EN;
388 
389  //Set event flag
390  nicDriverInterface->nicEvent = TRUE;
391  //Notify the TCP/IP stack of the event
392  flag |= osSetEventFromIsr(&netEvent);
393  }
394 
395  //Interrupt service routine epilogue
396  osExitIsr(flag);
397 }
398 
399 
400 /**
401  * @brief STR912 Ethernet MAC event handler
402  * @param[in] interface Underlying network interface
403  **/
404 
406 {
407  error_t error;
408 
409  //Packet received?
410  if(ENET_DMA->ISR & ENET_ISR_RX_CURR_DONE)
411  {
412  //Clear interrupt flag
413  ENET_DMA->ISR = ENET_ISR_RX_CURR_DONE;
414 
415  //Process all pending packets
416  do
417  {
418  //Read incoming packet
419  error = str912EthReceivePacket(interface);
420 
421  //No more data in the receive buffer?
422  } while(error != ERROR_BUFFER_EMPTY);
423  }
424 
425  //Re-enable DMA interrupts
427 }
428 
429 
430 /**
431  * @brief Send a packet
432  * @param[in] interface Underlying network interface
433  * @param[in] buffer Multi-part buffer containing the data to send
434  * @param[in] offset Offset to the first data byte
435  * @return Error code
436  **/
437 
439  const NetBuffer *buffer, size_t offset)
440 {
441  size_t length;
442 
443  //Retrieve the length of the packet
444  length = netBufferGetLength(buffer) - offset;
445 
446  //Check the frame length
448  {
449  //The transmitter can accept another packet
450  osSetEvent(&interface->nicTxEvent);
451  //Report an error
452  return ERROR_INVALID_LENGTH;
453  }
454 
455  //Make sure the current buffer is available for writing
456  if(txCurDmaDesc->status & ENET_TDES_STATUS_VALID)
457  return ERROR_FAILURE;
458 
459  //Copy user data to the transmit buffer
460  netBufferRead((uint8_t *) (txCurDmaDesc->start & ENET_TDES_START_ADDR),
461  buffer, offset, length);
462 
463  //Write the number of bytes to send
464  txCurDmaDesc->ctrl = ENET_TDES_CTRL_NXT_EN | length;
465  //Give the ownership of the descriptor to the DMA
466  txCurDmaDesc->status = ENET_TDES_STATUS_VALID;
467 
468  //Instruct the DMA to poll the transmit descriptor list
469  ENET_DMA->TXSTR |= ENET_TXSTR_START_FETCH;
470 
471  //Point to the next descriptor in the list
472  txCurDmaDesc = (Str912TxDmaDesc *) (txCurDmaDesc->next & ENET_TDES_NEXT_ADDR);
473 
474  //Check whether the next buffer is available for writing
475  if(!(txCurDmaDesc->status & ENET_TDES_STATUS_VALID))
476  {
477  //The transmitter can accept another packet
478  osSetEvent(&interface->nicTxEvent);
479  }
480 
481  //Data successfully written
482  return NO_ERROR;
483 }
484 
485 
486 /**
487  * @brief Receive a packet
488  * @param[in] interface Underlying network interface
489  * @return Error code
490  **/
491 
493 {
494  error_t error;
495  size_t n;
496  uint8_t *p;
497 
498  //The current buffer is available for reading?
499  if(!(rxCurDmaDesc->status & ENET_RDES_STATUS_VALID))
500  {
501  //Make sure no error occurred
502  if(!(rxCurDmaDesc->status & ENET_RDES_STATUS_ERROR))
503  {
504  //Point to the received frame
505  p = (uint8_t *) (rxCurDmaDesc->start & ENET_RDES_START_ADDR);
506 
507  //Retrieve the length of the frame
508  n = rxCurDmaDesc->status & ENET_RDES_STATUS_FL;
509  //Limit the number of data to read
511 
512  //Pass the packet to the upper layer
513  nicProcessPacket(interface, p, n);
514 
515  //Valid packet received
516  error = NO_ERROR;
517  }
518  else
519  {
520  //The received packet contains an error
521  error = ERROR_INVALID_PACKET;
522  }
523 
524  //Give the ownership of the descriptor back to the DMA
525  rxCurDmaDesc->status = ENET_RDES_STATUS_VALID;
526  //Point to the next descriptor in the list
527  rxCurDmaDesc = (Str912RxDmaDesc *) (rxCurDmaDesc->next & ENET_RDES_NEXT_ADDR);
528  }
529  else
530  {
531  //No more data in the receive buffer
532  error = ERROR_BUFFER_EMPTY;
533  }
534 
535  //Instruct the DMA to poll the receive descriptor list
536  ENET_DMA->RXSTR |= ENET_RXSTR_START_FETCH;
537 
538  //Return status code
539  return error;
540 }
541 
542 
543 /**
544  * @brief Configure MAC address filtering
545  * @param[in] interface Underlying network interface
546  * @return Error code
547  **/
548 
550 {
551  uint_t i;
552  uint_t k;
553  uint32_t crc;
554  uint32_t hashTable[2];
555  MacFilterEntry *entry;
556 
557  //Debug message
558  TRACE_DEBUG("Updating MAC filter...\r\n");
559 
560  //Set the MAC address of the station
561  ENET_MAC->MAL = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
562  ENET_MAC->MAH = interface->macAddr.w[2];
563 
564  //Clear hash table
565  hashTable[0] = 0;
566  hashTable[1] = 0;
567 
568  //The MAC address filter contains the list of MAC addresses to accept
569  //when receiving an Ethernet frame
570  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
571  {
572  //Point to the current entry
573  entry = &interface->macAddrFilter[i];
574 
575  //Valid entry?
576  if(entry->refCount > 0)
577  {
578  //Compute CRC over the current MAC address
579  crc = str912EthCalcCrc(&entry->addr, sizeof(MacAddr));
580 
581  //The upper 6 bits in the CRC register are used to index the
582  //contents of the hash table
583  k = (crc >> 26) & 0x3F;
584 
585  //Update hash table contents
586  hashTable[k / 32] |= (1 << (k % 32));
587  }
588  }
589 
590  //Write the hash table
591  ENET_MAC->MCLA = hashTable[0];
592  ENET_MAC->MCHA = hashTable[1];
593 
594  //Debug message
595  TRACE_DEBUG(" ENET_MCLA = %08" PRIX32 "\r\n", ENET_MAC->MCLA);
596  TRACE_DEBUG(" ENET_MCHA = %08" PRIX32 "\r\n", ENET_MAC->MCHA);
597 
598  //Successful processing
599  return NO_ERROR;
600 }
601 
602 
603 /**
604  * @brief Adjust MAC configuration parameters for proper operation
605  * @param[in] interface Underlying network interface
606  * @return Error code
607  **/
608 
610 {
611  uint32_t config;
612 
613  //Read current MAC configuration
614  config = ENET_MAC->MCR;
615 
616  //Half-duplex or full-duplex mode?
617  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
618  {
619  //Full-duplex mode
620  config |= ENET_MCR_FDM;
621  //Enable the reception path during transmission
622  config &= ~ENET_MCR_DRO;
623  }
624  else
625  {
626  //Half-duplex mode
627  config &= ~ENET_MCR_FDM;
628  //Disable the reception path during transmission
629  config |= ENET_MCR_DRO;
630  }
631 
632  //Update MAC configuration register
633  ENET_MAC->MCR = config;
634 
635  //Successful processing
636  return NO_ERROR;
637 }
638 
639 
640 /**
641  * @brief Write PHY register
642  * @param[in] opcode Access type (2 bits)
643  * @param[in] phyAddr PHY address (5 bits)
644  * @param[in] regAddr Register address (5 bits)
645  * @param[in] data Register value
646  **/
647 
648 void str912EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
649  uint8_t regAddr, uint16_t data)
650 {
651  uint32_t temp;
652 
653  //Valid opcode?
654  if(opcode == SMI_OPCODE_WRITE)
655  {
656  //Set up a write operation
657  temp = ENET_MIIA_WR | ENET_MIIA_BUSY;
658  //PHY address
659  temp |= (phyAddr << 11) & ENET_MIIA_PADDR;
660  //Register address
661  temp |= (regAddr << 6) & ENET_MIIA_RADDR;
662 
663  //Data to be written in the PHY register
664  ENET_MAC->MIID = data & ENET_MIID_RDATA;
665 
666  //Start a write operation
667  ENET_MAC->MIIA = temp;
668  //Wait for the write to complete
669  while(ENET_MAC->MIIA & ENET_MIIA_BUSY)
670  {
671  }
672  }
673  else
674  {
675  //The MAC peripheral only supports standard Clause 22 opcodes
676  }
677 }
678 
679 
680 /**
681  * @brief Read PHY register
682  * @param[in] opcode Access type (2 bits)
683  * @param[in] phyAddr PHY address (5 bits)
684  * @param[in] regAddr Register address (5 bits)
685  * @return Register value
686  **/
687 
688 uint16_t str912EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
689  uint8_t regAddr)
690 {
691  uint16_t data;
692  uint32_t temp;
693 
694  //Valid opcode?
695  if(opcode == SMI_OPCODE_READ)
696  {
697  //Set up a read operation
698  temp = ENET_MIIA_BUSY;
699  //PHY address
700  temp |= (phyAddr << 11) & ENET_MIIA_PADDR;
701  //Register address
702  temp |= (regAddr << 6) & ENET_MIIA_RADDR;
703 
704  //Start a read operation
705  ENET_MAC->MIIA = temp;
706  //Wait for the read to complete
707  while(ENET_MAC->MIIA & ENET_MIIA_BUSY)
708  {
709  }
710 
711  //Get register value
712  data = ENET_MAC->MIID & ENET_MIID_RDATA;
713  }
714  else
715  {
716  //The MAC peripheral only supports standard Clause 22 opcodes
717  data = 0;
718  }
719 
720  //Return the value of the PHY register
721  return data;
722 }
723 
724 
725 /**
726  * @brief CRC calculation
727  * @param[in] data Pointer to the data over which to calculate the CRC
728  * @param[in] length Number of bytes to process
729  * @return Resulting CRC value
730  **/
731 
732 uint32_t str912EthCalcCrc(const void *data, size_t length)
733 {
734  uint_t i;
735  uint_t j;
736 
737  //Point to the data over which to calculate the CRC
738  const uint8_t *p = (uint8_t *) data;
739  //CRC preset value
740  uint32_t crc = 0xFFFFFFFF;
741 
742  //Loop through data
743  for(i = 0; i < length; i++)
744  {
745  //The message is processed bit by bit
746  for(j = 0; j < 8; j++)
747  {
748  //Update CRC value
749  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
750  crc = (crc << 1) ^ 0x04C11DB7;
751  else
752  crc = crc << 1;
753  }
754  }
755 
756  //Return CRC value
757  return crc;
758 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define ENET_MCR_RVFF
error_t str912EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ENET_MIIA_BUSY
uint8_t length
Definition: dtls_misc.h:149
#define ENET_MCR_TE
error_t str912EthInit(NetInterface *interface)
STR912 Ethernet MAC initialization.
uint8_t opcode
Definition: dns_common.h:172
#define STR912_ETH_IRQ_PRIORITY
int bool_t
Definition: compiler_port.h:49
#define ENET_MCR_PS_1
uint16_t str912EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define ENET_RDES_START_ADDR
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
#define ENET_TXSTR_UNDER_RUN
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define ENET_SCR_SRESET
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
uint32_t str912EthCalcCrc(const void *data, size_t length)
CRC calculation.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
void str912EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define STR912_ETH_RX_BUFFER_SIZE
#define ENET_TXSTR_DFETCH_DLY_DEFAULT
#define ENET_RDES_NEXT_ADDR
#define ENET_TDES_START_ADDR
#define STR912_ETH_TX_BUFFER_SIZE
#define ENET_RDES_STATUS_ERROR
#define ENET_ISR_TX_CURR_DONE
#define osExitIsr(flag)
#define ENET_MCR_BL_1
void str912EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define SMI_OPCODE_WRITE
Definition: nic.h:62
error_t str912EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ENET_TDES_CTRL_NXT_EN
#define ENET_MIIA_RADDR
#define FALSE
Definition: os_port.h:46
#define ENET_IER_RX_CURR_DONE_EN
#define STR912_ETH_RX_BUFFER_COUNT
error_t
Error codes.
Definition: error.h:42
#define STR912_ETH_TX_BUFFER_COUNT
void str912EthInitGpio(NetInterface *interface)
error_t str912EthReceivePacket(NetInterface *interface)
Receive a packet.
#define ENET_RDES_CTRL_NXT_EN
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define txBuffer
@ ERROR_INVALID_PACKET
Definition: error.h:138
#define NetInterface
Definition: net.h:36
void ENET_IRQHandler(void)
STR912 Ethernet MAC interrupt service routine.
MacAddr addr
MAC address.
Definition: ethernet.h:222
@ ERROR_INVALID_LENGTH
Definition: error.h:109
#define ENET_RDES_STATUS_VALID
void str912EthEventHandler(NetInterface *interface)
STR912 Ethernet MAC event handler.
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define ENET_RDES_STATUS_FL
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
#define ENET_RDES_NEXT_NPOL_EN
#define rxBuffer
#define ENET_MCR_FDM
#define ENET_MIIA_WR
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define ENET_ISR_RX_CURR_DONE
error_t str912EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ENET_RXSTR_START_FETCH
uint16_t regAddr
Transmit DMA descriptor.
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
#define osEnterIsr()
#define ENET_MIID_RDATA
#define ENET_TXSTR_DMA_EN
#define ENET_RXSTR_DMA_EN
#define rxDmaDesc
void str912EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define ENET_TXSTR_START_FETCH
void str912EthTick(NetInterface *interface)
STR912 Ethernet MAC timer handler.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define ENET_TDES_NEXT_ADDR
#define txDmaDesc
#define ENET_MCR_DRO
#define ENET_IER_TX_CURR_DONE_EN
#define ENET_TDES_STATUS_VALID
const NicDriver str912EthDriver
STR912 Ethernet MAC driver.
Receive DMA descriptor.
#define ENET_RXSTR_DFETCH_DLY_DEFAULT
STR9 Ethernet MAC controller.
void str912EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ENET_MIIA_PADDR
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
#define ENET_TDES_NEXT_NPOL_EN
NIC driver.
Definition: nic.h:179
#define ENET_MCR_RVBE
#define ENET_MCR_AFM_1
#define ENET_MCR_DCE
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define ENET_MCR_RE
__start_packed struct @108 MacAddr
MAC address.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79