Infineon XMC4500 Ethernet MAC driver. More...

#include "core/nic.h"

Data Structures
struct	Xmc4500TxDmaDesc
	Transmit DMA descriptor. More...

struct	Xmc4500RxDmaDesc
	Receive DMA descriptor. More...

Macros
#define	XMC4500_ETH_TX_BUFFER_COUNT 3

#define	XMC4500_ETH_TX_BUFFER_SIZE 1536

#define	XMC4500_ETH_RX_BUFFER_COUNT 6

#define	XMC4500_ETH_RX_BUFFER_SIZE 1536

#define	XMC4500_ETH_IRQ_PRIORITY_GROUPING 1

#define	XMC4500_ETH_IRQ_GROUP_PRIORITY 48

#define	XMC4500_ETH_IRQ_SUB_PRIORITY 0

#define	XMC4500_ETH_RAM_SECTION "ETH_RAM"

#define	ETH_CON_MDIO_A (0 << ETH_CON_MDIO_Pos)

#define	ETH_CON_MDIO_B (1 << ETH_CON_MDIO_Pos)

#define	ETH_CON_MDIO_C (2 << ETH_CON_MDIO_Pos)

#define	ETH_CON_MDIO_D (3 << ETH_CON_MDIO_Pos)

#define	ETH_CON_CLK_TX_A (0 << ETH_CON_CLK_TX_Pos)

#define	ETH_CON_CLK_TX_B (1 << ETH_CON_CLK_TX_Pos)

#define	ETH_CON_CLK_TX_C (2 << ETH_CON_CLK_TX_Pos)

#define	ETH_CON_CLK_TX_D (3 << ETH_CON_CLK_TX_Pos)

#define	ETH_CON_COL_A (0 << ETH_CON_COL_Pos)

#define	ETH_CON_COL_B (1 << ETH_CON_COL_Pos)

#define	ETH_CON_COL_C (2 << ETH_CON_COL_Pos)

#define	ETH_CON_COL_D (3 << ETH_CON_COL_Pos)

#define	ETH_CON_RXER_A (0 << ETH_CON_RXER_Pos)

#define	ETH_CON_RXER_B (1 << ETH_CON_RXER_Pos)

#define	ETH_CON_RXER_C (2 << ETH_CON_RXER_Pos)

#define	ETH_CON_RXER_D (3 << ETH_CON_RXER_Pos)

#define	ETH_CON_CRS_A (0 << ETH_CON_CRS_Pos)

#define	ETH_CON_CRS_B (1 << ETH_CON_CRS_Pos)

#define	ETH_CON_CRS_C (2 << ETH_CON_CRS_Pos)

#define	ETH_CON_CRS_D (3 << ETH_CON_CRS_Pos)

#define	ETH_CON_CRS_DV_A (0 << ETH_CON_CRS_DV_Pos)

#define	ETH_CON_CRS_DV_B (1 << ETH_CON_CRS_DV_Pos)

#define	ETH_CON_CRS_DV_C (2 << ETH_CON_CRS_DV_Pos)

#define	ETH_CON_CRS_DV_D (3 << ETH_CON_CRS_DV_Pos)

#define	ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos)

#define	ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos)

#define	ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos)

#define	ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos)

#define	ETH_CON_RXD3_A (0 << ETH_CON_RXD3_Pos)

#define	ETH_CON_RXD3_B (1 << ETH_CON_RXD3_Pos)

#define	ETH_CON_RXD3_C (2 << ETH_CON_RXD3_Pos)

#define	ETH_CON_RXD3_D (3 << ETH_CON_RXD3_Pos)

#define	ETH_CON_RXD2_A (0 << ETH_CON_RXD2_Pos)

#define	ETH_CON_RXD2_B (1 << ETH_CON_RXD2_Pos)

#define	ETH_CON_RXD2_C (2 << ETH_CON_RXD2_Pos)

#define	ETH_CON_RXD2_D (3 << ETH_CON_RXD2_Pos)

#define	ETH_CON_RXD1_A (0 << ETH_CON_RXD1_Pos)

#define	ETH_CON_RXD1_B (1 << ETH_CON_RXD1_Pos)

#define	ETH_CON_RXD1_C (2 << ETH_CON_RXD1_Pos)

#define	ETH_CON_RXD1_D (3 << ETH_CON_RXD1_Pos)

#define	ETH_CON_RXD0_A (0 << ETH_CON_RXD0_Pos)

#define	ETH_CON_RXD0_B (1 << ETH_CON_RXD0_Pos)

#define	ETH_CON_RXD0_C (2 << ETH_CON_RXD0_Pos)

#define	ETH_CON_RXD0_D (3 << ETH_CON_RXD0_Pos)

#define	ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15)

#define	ETH_GMII_ADDRESS_CR_DIV42 (0 << ETH_GMII_ADDRESS_CR_Pos)

#define	ETH_GMII_ADDRESS_CR_DIV62 (1 << ETH_GMII_ADDRESS_CR_Pos)

#define	ETH_GMII_ADDRESS_CR_DIV16 (2 << ETH_GMII_ADDRESS_CR_Pos)

#define	ETH_GMII_ADDRESS_CR_DIV26 (3 << ETH_GMII_ADDRESS_CR_Pos)

#define	ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos)

#define	ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos)

#define	ETH_BUS_MODE_RPBL_1 (1 << ETH_BUS_MODE_RPBL_Pos)

#define	ETH_BUS_MODE_RPBL_2 (2 << ETH_BUS_MODE_RPBL_Pos)

#define	ETH_BUS_MODE_RPBL_4 (4 << ETH_BUS_MODE_RPBL_Pos)

#define	ETH_BUS_MODE_RPBL_8 (8 << ETH_BUS_MODE_RPBL_Pos)

#define	ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos)

#define	ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos)

#define	ETH_BUS_MODE_PR_1_1 (0 << ETH_BUS_MODE_PR_Pos)

#define	ETH_BUS_MODE_PR_2_1 (1 << ETH_BUS_MODE_PR_Pos)

#define	ETH_BUS_MODE_PR_3_1 (2 << ETH_BUS_MODE_PR_Pos)

#define	ETH_BUS_MODE_PR_4_1 (3 << ETH_BUS_MODE_PR_Pos)

#define	ETH_BUS_MODE_PBL_1 (1 << ETH_BUS_MODE_PBL_Pos)

#define	ETH_BUS_MODE_PBL_2 (2 << ETH_BUS_MODE_PBL_Pos)

#define	ETH_BUS_MODE_PBL_4 (4 << ETH_BUS_MODE_PBL_Pos)

#define	ETH_BUS_MODE_PBL_8 (8 << ETH_BUS_MODE_PBL_Pos)

#define	ETH_BUS_MODE_PBL_16 (16 << ETH_BUS_MODE_PBL_Pos)

#define	ETH_BUS_MODE_PBL_32 (32 << ETH_BUS_MODE_PBL_Pos)

#define	ETH_TDES0_OWN 0x80000000

#define	ETH_TDES0_IC 0x40000000

#define	ETH_TDES0_LS 0x20000000

#define	ETH_TDES0_FS 0x10000000

#define	ETH_TDES0_DC 0x08000000

#define	ETH_TDES0_DP 0x04000000

#define	ETH_TDES0_TTSE 0x02000000

#define	ETH_TDES0_CIC 0x00C00000

#define	ETH_TDES0_TER 0x00200000

#define	ETH_TDES0_TCH 0x00100000

#define	ETH_TDES0_TTSS 0x00020000

#define	ETH_TDES0_IHE 0x00010000

#define	ETH_TDES0_ES 0x00008000

#define	ETH_TDES0_JT 0x00004000

#define	ETH_TDES0_FF 0x00002000

#define	ETH_TDES0_IPE 0x00001000

#define	ETH_TDES0_LCA 0x00000800

#define	ETH_TDES0_NC 0x00000400

#define	ETH_TDES0_LCO 0x00000200

#define	ETH_TDES0_EC 0x00000100

#define	ETH_TDES0_VF 0x00000080

#define	ETH_TDES0_CC 0x00000078

#define	ETH_TDES0_ED 0x00000004

#define	ETH_TDES0_UF 0x00000002

#define	ETH_TDES0_DB 0x00000001

#define	ETH_TDES1_TBS2 0x1FFF0000

#define	ETH_TDES1_TBS1 0x00001FFF

#define	ETH_TDES2_TBAP1 0xFFFFFFFF

#define	ETH_TDES3_TBAP2 0xFFFFFFFF

#define	ETH_RDES0_OWN 0x80000000

#define	ETH_RDES0_AFM 0x40000000

#define	ETH_RDES0_FL 0x3FFF0000

#define	ETH_RDES0_ES 0x00008000

#define	ETH_RDES0_DE 0x00004000

#define	ETH_RDES0_SAF 0x00002000

#define	ETH_RDES0_LE 0x00001000

#define	ETH_RDES0_OE 0x00000800

#define	ETH_RDES0_VLAN 0x00000400

#define	ETH_RDES0_FS 0x00000200

#define	ETH_RDES0_LS 0x00000100

#define	ETH_RDES0_IPCE_GF 0x00000080

#define	ETH_RDES0_LCO 0x00000040

#define	ETH_RDES0_FT 0x00000020

#define	ETH_RDES0_RWT 0x00000010

#define	ETH_RDES0_RE 0x00000008

#define	ETH_RDES0_DBE 0x00000004

#define	ETH_RDES0_CE 0x00000002

#define	ETH_RDES0_PCE 0x00000001

#define	ETH_RDES1_DIC 0x80000000

#define	ETH_RDES1_RBS2 0x1FFF0000

#define	ETH_RDES1_RER 0x00008000

#define	ETH_RDES1_RCH 0x00004000

#define	ETH_RDES1_RBS1 0x00001FFF

#define	ETH_RDES2_RBAP1 0xFFFFFFFF

#define	ETH_RDES3_RBAP2 0xFFFFFFFF

Functions
error_t	xmc4500EthInit (NetInterface *interface)
	XMC4500 Ethernet MAC initialization. More...

void	xmc4500EthInitGpio (NetInterface *interface)
	GPIO configuration. More...

void	xmc4500EthInitDmaDesc (NetInterface *interface)
	Initialize DMA descriptor lists. More...

void	xmc4500EthTick (NetInterface *interface)
	XMC4500 Ethernet MAC timer handler. More...

void	xmc4500EthEnableIrq (NetInterface *interface)
	Enable interrupts. More...

void	xmc4500EthDisableIrq (NetInterface *interface)
	Disable interrupts. More...

void	xmc4500EthEventHandler (NetInterface *interface)
	XMC4500 Ethernet MAC event handler. More...

error_t	xmc4500EthSendPacket (NetInterface interface, const NetBuffer buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...

error_t	xmc4500EthReceivePacket (NetInterface *interface)
	Receive a packet. More...

error_t	xmc4500EthUpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...

error_t	xmc4500EthUpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...

void	xmc4500EthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...

uint16_t	xmc4500EthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

uint32_t	xmc4500EthCalcCrc (const void *data, size_t length)
	CRC calculation. More...

Variables
const NicDriver	xmc4500EthDriver
	XMC4500 Ethernet MAC driver. More...

Detailed Description

Infineon XMC4500 Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author: Oryx Embedded SARL (www.oryx-embedded.com)

Version: 2.4.4

Definition in file xmc4500_eth_driver.h.

Macro Definition Documentation

◆ ETH_BUS_MODE_PBL_1

#define ETH_BUS_MODE_PBL_1 (1 << ETH_BUS_MODE_PBL_Pos)

Definition at line 171 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PBL_16

#define ETH_BUS_MODE_PBL_16 (16 << ETH_BUS_MODE_PBL_Pos)

Definition at line 175 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PBL_2

#define ETH_BUS_MODE_PBL_2 (2 << ETH_BUS_MODE_PBL_Pos)

Definition at line 172 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PBL_32

#define ETH_BUS_MODE_PBL_32 (32 << ETH_BUS_MODE_PBL_Pos)

Definition at line 176 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PBL_4

#define ETH_BUS_MODE_PBL_4 (4 << ETH_BUS_MODE_PBL_Pos)

Definition at line 173 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PBL_8

#define ETH_BUS_MODE_PBL_8 (8 << ETH_BUS_MODE_PBL_Pos)

Definition at line 174 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PR_1_1

#define ETH_BUS_MODE_PR_1_1 (0 << ETH_BUS_MODE_PR_Pos)

Definition at line 166 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PR_2_1

#define ETH_BUS_MODE_PR_2_1 (1 << ETH_BUS_MODE_PR_Pos)

Definition at line 167 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PR_3_1

#define ETH_BUS_MODE_PR_3_1 (2 << ETH_BUS_MODE_PR_Pos)

Definition at line 168 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_PR_4_1

#define ETH_BUS_MODE_PR_4_1 (3 << ETH_BUS_MODE_PR_Pos)

Definition at line 169 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_RPBL_1

#define ETH_BUS_MODE_RPBL_1 (1 << ETH_BUS_MODE_RPBL_Pos)

Definition at line 159 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_RPBL_16

#define ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos)

Definition at line 163 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_RPBL_2

#define ETH_BUS_MODE_RPBL_2 (2 << ETH_BUS_MODE_RPBL_Pos)

Definition at line 160 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_RPBL_32

#define ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos)

Definition at line 164 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_RPBL_4

#define ETH_BUS_MODE_RPBL_4 (4 << ETH_BUS_MODE_RPBL_Pos)

Definition at line 161 of file xmc4500_eth_driver.h.

◆ ETH_BUS_MODE_RPBL_8

#define ETH_BUS_MODE_RPBL_8 (8 << ETH_BUS_MODE_RPBL_Pos)

Definition at line 162 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_RMII_A

#define ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos)

Definition at line 122 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_RMII_B

#define ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos)

Definition at line 123 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_RMII_C

#define ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos)

Definition at line 124 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_RMII_D

#define ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos)

Definition at line 125 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_TX_A

#define ETH_CON_CLK_TX_A (0 << ETH_CON_CLK_TX_Pos)

Definition at line 97 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_TX_B

#define ETH_CON_CLK_TX_B (1 << ETH_CON_CLK_TX_Pos)

Definition at line 98 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_TX_C

#define ETH_CON_CLK_TX_C (2 << ETH_CON_CLK_TX_Pos)

Definition at line 99 of file xmc4500_eth_driver.h.

◆ ETH_CON_CLK_TX_D

#define ETH_CON_CLK_TX_D (3 << ETH_CON_CLK_TX_Pos)

Definition at line 100 of file xmc4500_eth_driver.h.

◆ ETH_CON_COL_A

#define ETH_CON_COL_A (0 << ETH_CON_COL_Pos)

Definition at line 102 of file xmc4500_eth_driver.h.

◆ ETH_CON_COL_B

#define ETH_CON_COL_B (1 << ETH_CON_COL_Pos)

Definition at line 103 of file xmc4500_eth_driver.h.

◆ ETH_CON_COL_C

#define ETH_CON_COL_C (2 << ETH_CON_COL_Pos)

Definition at line 104 of file xmc4500_eth_driver.h.

◆ ETH_CON_COL_D

#define ETH_CON_COL_D (3 << ETH_CON_COL_Pos)

Definition at line 105 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_A

#define ETH_CON_CRS_A (0 << ETH_CON_CRS_Pos)

Definition at line 112 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_B

#define ETH_CON_CRS_B (1 << ETH_CON_CRS_Pos)

Definition at line 113 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_C

#define ETH_CON_CRS_C (2 << ETH_CON_CRS_Pos)

Definition at line 114 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_D

#define ETH_CON_CRS_D (3 << ETH_CON_CRS_Pos)

Definition at line 115 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_DV_A

#define ETH_CON_CRS_DV_A (0 << ETH_CON_CRS_DV_Pos)

Definition at line 117 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_DV_B

#define ETH_CON_CRS_DV_B (1 << ETH_CON_CRS_DV_Pos)

Definition at line 118 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_DV_C

#define ETH_CON_CRS_DV_C (2 << ETH_CON_CRS_DV_Pos)

Definition at line 119 of file xmc4500_eth_driver.h.

◆ ETH_CON_CRS_DV_D

#define ETH_CON_CRS_DV_D (3 << ETH_CON_CRS_DV_Pos)

Definition at line 120 of file xmc4500_eth_driver.h.

◆ ETH_CON_MDIO_A

#define ETH_CON_MDIO_A (0 << ETH_CON_MDIO_Pos)

Definition at line 92 of file xmc4500_eth_driver.h.

◆ ETH_CON_MDIO_B

#define ETH_CON_MDIO_B (1 << ETH_CON_MDIO_Pos)

Definition at line 93 of file xmc4500_eth_driver.h.

◆ ETH_CON_MDIO_C

#define ETH_CON_MDIO_C (2 << ETH_CON_MDIO_Pos)

Definition at line 94 of file xmc4500_eth_driver.h.

◆ ETH_CON_MDIO_D

#define ETH_CON_MDIO_D (3 << ETH_CON_MDIO_Pos)

Definition at line 95 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD0_A

#define ETH_CON_RXD0_A (0 << ETH_CON_RXD0_Pos)

Definition at line 142 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD0_B

#define ETH_CON_RXD0_B (1 << ETH_CON_RXD0_Pos)

Definition at line 143 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD0_C

#define ETH_CON_RXD0_C (2 << ETH_CON_RXD0_Pos)

Definition at line 144 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD0_D

#define ETH_CON_RXD0_D (3 << ETH_CON_RXD0_Pos)

Definition at line 145 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD1_A

#define ETH_CON_RXD1_A (0 << ETH_CON_RXD1_Pos)

Definition at line 137 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD1_B

#define ETH_CON_RXD1_B (1 << ETH_CON_RXD1_Pos)

Definition at line 138 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD1_C

#define ETH_CON_RXD1_C (2 << ETH_CON_RXD1_Pos)

Definition at line 139 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD1_D

#define ETH_CON_RXD1_D (3 << ETH_CON_RXD1_Pos)

Definition at line 140 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD2_A

#define ETH_CON_RXD2_A (0 << ETH_CON_RXD2_Pos)

Definition at line 132 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD2_B

#define ETH_CON_RXD2_B (1 << ETH_CON_RXD2_Pos)

Definition at line 133 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD2_C

#define ETH_CON_RXD2_C (2 << ETH_CON_RXD2_Pos)

Definition at line 134 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD2_D

#define ETH_CON_RXD2_D (3 << ETH_CON_RXD2_Pos)

Definition at line 135 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD3_A

#define ETH_CON_RXD3_A (0 << ETH_CON_RXD3_Pos)

Definition at line 127 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD3_B

#define ETH_CON_RXD3_B (1 << ETH_CON_RXD3_Pos)

Definition at line 128 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD3_C

#define ETH_CON_RXD3_C (2 << ETH_CON_RXD3_Pos)

Definition at line 129 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXD3_D

#define ETH_CON_RXD3_D (3 << ETH_CON_RXD3_Pos)

Definition at line 130 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXER_A

#define ETH_CON_RXER_A (0 << ETH_CON_RXER_Pos)

Definition at line 107 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXER_B

#define ETH_CON_RXER_B (1 << ETH_CON_RXER_Pos)

Definition at line 108 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXER_C

#define ETH_CON_RXER_C (2 << ETH_CON_RXER_Pos)

Definition at line 109 of file xmc4500_eth_driver.h.

◆ ETH_CON_RXER_D

#define ETH_CON_RXER_D (3 << ETH_CON_RXER_Pos)

Definition at line 110 of file xmc4500_eth_driver.h.

◆ ETH_GMII_ADDRESS_CR_DIV102

#define ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos)

Definition at line 155 of file xmc4500_eth_driver.h.

◆ ETH_GMII_ADDRESS_CR_DIV124

#define ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos)

Definition at line 156 of file xmc4500_eth_driver.h.

◆ ETH_GMII_ADDRESS_CR_DIV16

#define ETH_GMII_ADDRESS_CR_DIV16 (2 << ETH_GMII_ADDRESS_CR_Pos)

Definition at line 153 of file xmc4500_eth_driver.h.

◆ ETH_GMII_ADDRESS_CR_DIV26

#define ETH_GMII_ADDRESS_CR_DIV26 (3 << ETH_GMII_ADDRESS_CR_Pos)

Definition at line 154 of file xmc4500_eth_driver.h.

◆ ETH_GMII_ADDRESS_CR_DIV42

#define ETH_GMII_ADDRESS_CR_DIV42 (0 << ETH_GMII_ADDRESS_CR_Pos)

Definition at line 151 of file xmc4500_eth_driver.h.

◆ ETH_GMII_ADDRESS_CR_DIV62

#define ETH_GMII_ADDRESS_CR_DIV62 (1 << ETH_GMII_ADDRESS_CR_Pos)

Definition at line 152 of file xmc4500_eth_driver.h.

◆ ETH_MAC_CONFIGURATION_RESERVED15_Msk

#define ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15)

Definition at line 148 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_AFM

#define ETH_RDES0_AFM 0x40000000

Definition at line 211 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_CE

#define ETH_RDES0_CE 0x00000002

Definition at line 227 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_DBE

#define ETH_RDES0_DBE 0x00000004

Definition at line 226 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_DE

#define ETH_RDES0_DE 0x00004000

Definition at line 214 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_ES

#define ETH_RDES0_ES 0x00008000

Definition at line 213 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_FL

#define ETH_RDES0_FL 0x3FFF0000

Definition at line 212 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_FS

#define ETH_RDES0_FS 0x00000200

Definition at line 219 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_FT

#define ETH_RDES0_FT 0x00000020

Definition at line 223 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_IPCE_GF

#define ETH_RDES0_IPCE_GF 0x00000080

Definition at line 221 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_LCO

#define ETH_RDES0_LCO 0x00000040

Definition at line 222 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_LE

#define ETH_RDES0_LE 0x00001000

Definition at line 216 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_LS

#define ETH_RDES0_LS 0x00000100

Definition at line 220 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_OE

#define ETH_RDES0_OE 0x00000800

Definition at line 217 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_OWN

#define ETH_RDES0_OWN 0x80000000

Definition at line 210 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_PCE

#define ETH_RDES0_PCE 0x00000001

Definition at line 228 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_RE

#define ETH_RDES0_RE 0x00000008

Definition at line 225 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_RWT

#define ETH_RDES0_RWT 0x00000010

Definition at line 224 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_SAF

#define ETH_RDES0_SAF 0x00002000

Definition at line 215 of file xmc4500_eth_driver.h.

◆ ETH_RDES0_VLAN

#define ETH_RDES0_VLAN 0x00000400

Definition at line 218 of file xmc4500_eth_driver.h.

◆ ETH_RDES1_DIC

#define ETH_RDES1_DIC 0x80000000

Definition at line 229 of file xmc4500_eth_driver.h.

◆ ETH_RDES1_RBS1

#define ETH_RDES1_RBS1 0x00001FFF

Definition at line 233 of file xmc4500_eth_driver.h.

◆ ETH_RDES1_RBS2

#define ETH_RDES1_RBS2 0x1FFF0000

Definition at line 230 of file xmc4500_eth_driver.h.

◆ ETH_RDES1_RCH

#define ETH_RDES1_RCH 0x00004000

Definition at line 232 of file xmc4500_eth_driver.h.

◆ ETH_RDES1_RER

#define ETH_RDES1_RER 0x00008000

Definition at line 231 of file xmc4500_eth_driver.h.

◆ ETH_RDES2_RBAP1

#define ETH_RDES2_RBAP1 0xFFFFFFFF

Definition at line 234 of file xmc4500_eth_driver.h.

◆ ETH_RDES3_RBAP2

#define ETH_RDES3_RBAP2 0xFFFFFFFF

Definition at line 235 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_CC

#define ETH_TDES0_CC 0x00000078

Definition at line 200 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_CIC

#define ETH_TDES0_CIC 0x00C00000

Definition at line 186 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_DB

#define ETH_TDES0_DB 0x00000001

Definition at line 203 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_DC

#define ETH_TDES0_DC 0x08000000

Definition at line 183 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_DP

#define ETH_TDES0_DP 0x04000000

Definition at line 184 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_EC

#define ETH_TDES0_EC 0x00000100

Definition at line 198 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_ED

#define ETH_TDES0_ED 0x00000004

Definition at line 201 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_ES

#define ETH_TDES0_ES 0x00008000

Definition at line 191 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_FF

#define ETH_TDES0_FF 0x00002000

Definition at line 193 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_FS

#define ETH_TDES0_FS 0x10000000

Definition at line 182 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_IC

#define ETH_TDES0_IC 0x40000000

Definition at line 180 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_IHE

#define ETH_TDES0_IHE 0x00010000

Definition at line 190 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_IPE

#define ETH_TDES0_IPE 0x00001000

Definition at line 194 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_JT

#define ETH_TDES0_JT 0x00004000

Definition at line 192 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_LCA

#define ETH_TDES0_LCA 0x00000800

Definition at line 195 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_LCO

#define ETH_TDES0_LCO 0x00000200

Definition at line 197 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_LS

#define ETH_TDES0_LS 0x20000000

Definition at line 181 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_NC

#define ETH_TDES0_NC 0x00000400

Definition at line 196 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_OWN

#define ETH_TDES0_OWN 0x80000000

Definition at line 179 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_TCH

#define ETH_TDES0_TCH 0x00100000

Definition at line 188 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_TER

#define ETH_TDES0_TER 0x00200000

Definition at line 187 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_TTSE

#define ETH_TDES0_TTSE 0x02000000

Definition at line 185 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_TTSS

#define ETH_TDES0_TTSS 0x00020000

Definition at line 189 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_UF

#define ETH_TDES0_UF 0x00000002

Definition at line 202 of file xmc4500_eth_driver.h.

◆ ETH_TDES0_VF

#define ETH_TDES0_VF 0x00000080

Definition at line 199 of file xmc4500_eth_driver.h.

◆ ETH_TDES1_TBS1

#define ETH_TDES1_TBS1 0x00001FFF

Definition at line 205 of file xmc4500_eth_driver.h.

◆ ETH_TDES1_TBS2

#define ETH_TDES1_TBS2 0x1FFF0000

Definition at line 204 of file xmc4500_eth_driver.h.

◆ ETH_TDES2_TBAP1

#define ETH_TDES2_TBAP1 0xFFFFFFFF

Definition at line 206 of file xmc4500_eth_driver.h.

◆ ETH_TDES3_TBAP2

#define ETH_TDES3_TBAP2 0xFFFFFFFF

Definition at line 207 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_IRQ_GROUP_PRIORITY

#define XMC4500_ETH_IRQ_GROUP_PRIORITY 48

Definition at line 74 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_IRQ_PRIORITY_GROUPING

#define XMC4500_ETH_IRQ_PRIORITY_GROUPING 1

Definition at line 67 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_IRQ_SUB_PRIORITY

#define XMC4500_ETH_IRQ_SUB_PRIORITY 0

Definition at line 81 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_RAM_SECTION

#define XMC4500_ETH_RAM_SECTION "ETH_RAM"

Definition at line 88 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_RX_BUFFER_COUNT

#define XMC4500_ETH_RX_BUFFER_COUNT 6

Definition at line 53 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_RX_BUFFER_SIZE

#define XMC4500_ETH_RX_BUFFER_SIZE 1536

Definition at line 60 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_TX_BUFFER_COUNT

#define XMC4500_ETH_TX_BUFFER_COUNT 3

Definition at line 39 of file xmc4500_eth_driver.h.

◆ XMC4500_ETH_TX_BUFFER_SIZE

#define XMC4500_ETH_TX_BUFFER_SIZE 1536

Definition at line 46 of file xmc4500_eth_driver.h.

Function Documentation

◆ xmc4500EthCalcCrc()

uint32_t xmc4500EthCalcCrc	(	const void *	data,
		size_t	length
	)

CRC calculation.

Parameters

[in]	data	Pointer to the data over which to calculate the CRC
[in]	length	Number of bytes to process

Returns: Resulting CRC value

Definition at line 905 of file xmc4500_eth_driver.c.

◆ xmc4500EthDisableIrq()

void xmc4500EthDisableIrq ( NetInterface * interface )

Disable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 418 of file xmc4500_eth_driver.c.

◆ xmc4500EthEnableIrq()

void xmc4500EthEnableIrq ( NetInterface * interface )

Enable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 390 of file xmc4500_eth_driver.c.

◆ xmc4500EthEventHandler()

void xmc4500EthEventHandler ( NetInterface * interface )

XMC4500 Ethernet MAC event handler.

Parameters

[in] interface Underlying network interface

Definition at line 498 of file xmc4500_eth_driver.c.

◆ xmc4500EthInit()

error_t xmc4500EthInit ( NetInterface * interface )

XMC4500 Ethernet MAC initialization.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 118 of file xmc4500_eth_driver.c.

◆ xmc4500EthInitDmaDesc()

void xmc4500EthInitDmaDesc ( NetInterface * interface )

Initialize DMA descriptor lists.

Parameters

[in] interface Underlying network interface

Definition at line 309 of file xmc4500_eth_driver.c.

◆ xmc4500EthInitGpio()

void xmc4500EthInitGpio ( NetInterface * interface )

GPIO configuration.

Parameters

[in] interface Underlying network interface

Definition at line 248 of file xmc4500_eth_driver.c.

◆ xmc4500EthReadPhyReg()

uint16_t xmc4500EthReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns: Register value

Definition at line 859 of file xmc4500_eth_driver.c.

◆ xmc4500EthReceivePacket()

error_t xmc4500EthReceivePacket ( NetInterface * interface )

Receive a packet.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 582 of file xmc4500_eth_driver.c.

◆ xmc4500EthSendPacket()

error_t xmc4500EthSendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns: Error code

Definition at line 523 of file xmc4500_eth_driver.c.

◆ xmc4500EthTick()

void xmc4500EthTick ( NetInterface * interface )

XMC4500 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in] interface Underlying network interface

Definition at line 365 of file xmc4500_eth_driver.c.

◆ xmc4500EthUpdateMacAddrFilter()

error_t xmc4500EthUpdateMacAddrFilter ( NetInterface * interface )

Configure MAC address filtering.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 652 of file xmc4500_eth_driver.c.

◆ xmc4500EthUpdateMacConfig()

error_t xmc4500EthUpdateMacConfig ( NetInterface * interface )

Adjust MAC configuration parameters for proper operation.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 774 of file xmc4500_eth_driver.c.

◆ xmc4500EthWritePhyReg()

void xmc4500EthWritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 817 of file xmc4500_eth_driver.c.

Variable Documentation

◆ xmc4500EthDriver

const NicDriver xmc4500EthDriver

extern

XMC4500 Ethernet MAC driver.

Definition at line 91 of file xmc4500_eth_driver.c.

Data Structures

Macros

Functions

Variables

Detailed Description

License

Macro Definition Documentation

◆ ETH_BUS_MODE_PBL_1

◆ ETH_BUS_MODE_PBL_16

◆ ETH_BUS_MODE_PBL_2

◆ ETH_BUS_MODE_PBL_32

◆ ETH_BUS_MODE_PBL_4

◆ ETH_BUS_MODE_PBL_8

◆ ETH_BUS_MODE_PR_1_1

◆ ETH_BUS_MODE_PR_2_1

◆ ETH_BUS_MODE_PR_3_1

◆ ETH_BUS_MODE_PR_4_1

◆ ETH_BUS_MODE_RPBL_1

◆ ETH_BUS_MODE_RPBL_16

◆ ETH_BUS_MODE_RPBL_2

◆ ETH_BUS_MODE_RPBL_32

◆ ETH_BUS_MODE_RPBL_4

◆ ETH_BUS_MODE_RPBL_8

◆ ETH_CON_CLK_RMII_A

◆ ETH_CON_CLK_RMII_B

◆ ETH_CON_CLK_RMII_C

◆ ETH_CON_CLK_RMII_D

◆ ETH_CON_CLK_TX_A

◆ ETH_CON_CLK_TX_B

◆ ETH_CON_CLK_TX_C

◆ ETH_CON_CLK_TX_D

◆ ETH_CON_COL_A

◆ ETH_CON_COL_B

◆ ETH_CON_COL_C

◆ ETH_CON_COL_D

◆ ETH_CON_CRS_A

◆ ETH_CON_CRS_B

◆ ETH_CON_CRS_C

◆ ETH_CON_CRS_D

◆ ETH_CON_CRS_DV_A

◆ ETH_CON_CRS_DV_B

◆ ETH_CON_CRS_DV_C

◆ ETH_CON_CRS_DV_D

◆ ETH_CON_MDIO_A

◆ ETH_CON_MDIO_B

◆ ETH_CON_MDIO_C

◆ ETH_CON_MDIO_D

◆ ETH_CON_RXD0_A

◆ ETH_CON_RXD0_B

◆ ETH_CON_RXD0_C

◆ ETH_CON_RXD0_D

◆ ETH_CON_RXD1_A

◆ ETH_CON_RXD1_B

◆ ETH_CON_RXD1_C

◆ ETH_CON_RXD1_D

◆ ETH_CON_RXD2_A

◆ ETH_CON_RXD2_B

◆ ETH_CON_RXD2_C

◆ ETH_CON_RXD2_D

◆ ETH_CON_RXD3_A

◆ ETH_CON_RXD3_B

◆ ETH_CON_RXD3_C

◆ ETH_CON_RXD3_D

◆ ETH_CON_RXER_A

◆ ETH_CON_RXER_B

◆ ETH_CON_RXER_C

◆ ETH_CON_RXER_D

◆ ETH_GMII_ADDRESS_CR_DIV102

◆ ETH_GMII_ADDRESS_CR_DIV124

◆ ETH_GMII_ADDRESS_CR_DIV16

◆ ETH_GMII_ADDRESS_CR_DIV26

◆ ETH_GMII_ADDRESS_CR_DIV42

◆ ETH_GMII_ADDRESS_CR_DIV62

◆ ETH_MAC_CONFIGURATION_RESERVED15_Msk

◆ ETH_RDES0_AFM

◆ ETH_RDES0_CE

◆ ETH_RDES0_DBE

◆ ETH_RDES0_DE

◆ ETH_RDES0_ES

◆ ETH_RDES0_FL