xmc4500_eth_driver.c
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1 /**
2  * @file xmc4500_eth_driver.c
3  * @brief Infineon XMC4500 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "xmc4500.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
48 #pragma location = XMC4500_ETH_RAM_SECTION
50 //Receive buffer
51 #pragma data_alignment = 4
52 #pragma location = XMC4500_ETH_RAM_SECTION
54 //Transmit DMA descriptors
55 #pragma data_alignment = 4
56 #pragma location = XMC4500_ETH_RAM_SECTION
58 //Receive DMA descriptors
59 #pragma data_alignment = 4
60 #pragma location = XMC4500_ETH_RAM_SECTION
62 
63 //Keil MDK-ARM or GCC compiler?
64 #else
65 
66 //Transmit buffer
68  __attribute__((aligned(4), __section__(XMC4500_ETH_RAM_SECTION)));
69 //Receive buffer
71  __attribute__((aligned(4), __section__(XMC4500_ETH_RAM_SECTION)));
72 //Transmit DMA descriptors
74  __attribute__((aligned(4), __section__(XMC4500_ETH_RAM_SECTION)));
75 //Receive DMA descriptors
77  __attribute__((aligned(4), __section__(XMC4500_ETH_RAM_SECTION)));
78 
79 #endif
80 
81 //Pointer to the current TX DMA descriptor
82 static Xmc4500TxDmaDesc *txCurDmaDesc;
83 //Pointer to the current RX DMA descriptor
84 static Xmc4500RxDmaDesc *rxCurDmaDesc;
85 
86 
87 /**
88  * @brief XMC4500 Ethernet MAC driver
89  **/
90 
92 {
94  ETH_MTU,
105  TRUE,
106  TRUE,
107  TRUE,
108  FALSE
109 };
110 
111 
112 /**
113  * @brief XMC4500 Ethernet MAC initialization
114  * @param[in] interface Underlying network interface
115  * @return Error code
116  **/
117 
119 {
120  error_t error;
121 
122  //Debug message
123  TRACE_INFO("Initializing XMC4500 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Disable parity error trap
129  SCU_PARITY->PETE = 0;
130  //Disable unaligned access trap
131  PPB->CCR &= ~PPB_CCR_UNALIGN_TRP_Msk;
132 
133  //Enable ETH0 peripheral clock
134  SCU_CLK->CLKSET = SCU_CLK_CLKSET_ETH0CEN_Msk;
135 
136  //GPIO configuration
137  xmc4500EthInitGpio(interface);
138 
139  //Reset ETH0 peripheral
140  SCU_RESET->PRSET2 = SCU_RESET_PRSET2_ETH0RS_Msk;
141  SCU_RESET->PRCLR2 = SCU_RESET_PRCLR2_ETH0RS_Msk;
142 
143  //Reset DMA controller
144  ETH0->BUS_MODE |= ETH_BUS_MODE_SWR_Msk;
145  //Wait for the reset to complete
146  while((ETH0->BUS_MODE & ETH_BUS_MODE_SWR_Msk) != 0)
147  {
148  }
149 
150  //Adjust MDC clock range depending on ETH clock frequency
151  ETH0->GMII_ADDRESS = ETH_GMII_ADDRESS_CR_DIV62;
152 
153  //Valid Ethernet PHY or switch driver?
154  if(interface->phyDriver != NULL)
155  {
156  //Ethernet PHY initialization
157  error = interface->phyDriver->init(interface);
158  }
159  else if(interface->switchDriver != NULL)
160  {
161  //Ethernet switch initialization
162  error = interface->switchDriver->init(interface);
163  }
164  else
165  {
166  //The interface is not properly configured
167  error = ERROR_FAILURE;
168  }
169 
170  //Any error to report?
171  if(error)
172  {
173  return error;
174  }
175 
176  //Use default MAC configuration
177  ETH0->MAC_CONFIGURATION = ETH_MAC_CONFIGURATION_RESERVED15_Msk |
178  ETH_MAC_CONFIGURATION_DO_Msk;
179 
180  //Set the MAC address of the station
181  ETH0->MAC_ADDRESS0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
182  ETH0->MAC_ADDRESS0_HIGH = interface->macAddr.w[2];
183 
184  //The MAC supports 3 additional addresses for unicast perfect filtering
185  ETH0->MAC_ADDRESS1_LOW = 0;
186  ETH0->MAC_ADDRESS1_HIGH = 0;
187  ETH0->MAC_ADDRESS2_LOW = 0;
188  ETH0->MAC_ADDRESS2_HIGH = 0;
189  ETH0->MAC_ADDRESS3_LOW = 0;
190  ETH0->MAC_ADDRESS3_HIGH = 0;
191 
192  //Initialize hash table
193  ETH0->HASH_TABLE_LOW = 0;
194  ETH0->HASH_TABLE_HIGH = 0;
195 
196  //Configure the receive filter
197  ETH0->MAC_FRAME_FILTER = ETH_MAC_FRAME_FILTER_HPF_Msk | ETH_MAC_FRAME_FILTER_HMC_Msk;
198  //Disable flow control
199  ETH0->FLOW_CONTROL = 0;
200  //Enable store and forward mode
201  ETH0->OPERATION_MODE = ETH_OPERATION_MODE_RSF_Msk | ETH_OPERATION_MODE_TSF_Msk;
202 
203  //Configure DMA bus mode
204  ETH0->BUS_MODE = ETH_BUS_MODE_AAL_Msk | ETH_BUS_MODE_USP_Msk |
206 
207  //Initialize DMA descriptor lists
208  xmc4500EthInitDmaDesc(interface);
209 
210  //Prevent interrupts from being generated when statistic counters reach
211  //half their maximum value
212  ETH0->MMC_TRANSMIT_INTERRUPT_MASK = 0xFFFFFFFF;
213  ETH0->MMC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF;
214  ETH0->MMC_IPC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF;
215 
216  //Disable MAC interrupts
217  ETH0->INTERRUPT_MASK = ETH_INTERRUPT_MASK_TSIM_Msk | ETH_INTERRUPT_MASK_PMTIM_Msk;
218 
219  //Enable the desired DMA interrupts
220  ETH0->INTERRUPT_ENABLE = ETH_INTERRUPT_ENABLE_NIE_Msk |
221  ETH_INTERRUPT_ENABLE_RIE_Msk | ETH_INTERRUPT_ENABLE_TIE_Msk;
222 
223  //Set priority grouping (6 bits for pre-emption priority, no bits for subpriority)
224  NVIC_SetPriorityGrouping(XMC4500_ETH_IRQ_PRIORITY_GROUPING);
225 
226  //Configure Ethernet interrupt priority
227  NVIC_SetPriority(ETH0_0_IRQn, NVIC_EncodePriority(XMC4500_ETH_IRQ_PRIORITY_GROUPING,
229 
230  //Enable MAC transmission and reception
231  ETH0->MAC_CONFIGURATION |= ETH_MAC_CONFIGURATION_TE_Msk | ETH_MAC_CONFIGURATION_RE_Msk;
232  //Enable DMA transmission and reception
233  ETH0->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk | ETH_OPERATION_MODE_SR_Msk;
234 
235  //Accept any packets from the upper layer
236  osSetEvent(&interface->nicTxEvent);
237 
238  //Successful initialization
239  return NO_ERROR;
240 }
241 
242 
243 /**
244  * @brief GPIO configuration
245  * @param[in] interface Underlying network interface
246  **/
247 
248 __weak_func void xmc4500EthInitGpio(NetInterface *interface)
249 {
250 //XMC4500 Relax Kit?
251 #if defined(USE_KIT_XMC4500_RELAX)
252  uint32_t temp;
253 
254  //Configure ETH0.MDIO (P2.0), ETH0.RXD0A (P2.2) and ETH0.RXD1A (P2.3)
255  temp = PORT2->IOCR0;
256  temp &= ~(PORT2_IOCR0_PC0_Msk | PORT2_IOCR0_PC2_Msk | PORT2_IOCR0_PC3_Msk);
257  temp |= (0UL << PORT2_IOCR0_PC0_Pos) | (0UL << PORT2_IOCR0_PC2_Pos) | (0UL << PORT2_IOCR0_PC3_Pos);
258  PORT2->IOCR0 = temp;
259 
260  //Configure ETH0.RXERA (P2.4), ETH0.TX_EN (P2.5) and ETH0.MDC (P2.7)
261  temp = PORT2->IOCR4;
262  temp &= ~(PORT2_IOCR4_PC4_Msk | PORT2_IOCR4_PC5_Msk | PORT2_IOCR4_PC7_Msk);
263  temp |= (0UL << PORT2_IOCR4_PC4_Pos) | (17UL << PORT2_IOCR4_PC5_Pos) | (17UL << PORT2_IOCR4_PC7_Pos);
264  PORT2->IOCR4 = temp;
265 
266  //Configure ETH0.TXD0 (P2.8) and ETH0.TXD1 (P2.9)
267  temp = PORT2->IOCR8;
268  temp &= ~(PORT2_IOCR8_PC8_Msk | PORT2_IOCR8_PC9_Msk);
269  temp |= (17UL << PORT2_IOCR8_PC8_Pos) | (17UL << PORT2_IOCR8_PC9_Pos);
270  PORT2->IOCR8 = temp;
271 
272  //Configure ETH0.CLK_RMIIC (P15.8) and ETH0.CRS_DVC (P15.9)
273  temp = PORT15->IOCR8;
274  temp &= ~(PORT15_IOCR8_PC8_Msk | PORT15_IOCR8_PC9_Msk);
275  temp |= (0UL << PORT15_IOCR8_PC8_Pos) | (0UL << PORT15_IOCR8_PC9_Pos);
276  PORT15->IOCR8 = temp;
277 
278  //Assign ETH_MDIO (P2.0) to HW0
279  temp = PORT2->HWSEL & ~PORT2_HWSEL_HW0_Msk;
280  PORT2->HWSEL = temp | (1UL << PORT2_HWSEL_HW0_Pos);
281 
282  //Select output driver strength for ETH0.TX_EN (P2.5)
283  temp = PORT2->PDR0;
284  temp &= ~PORT2_PDR0_PD5_Msk;
285  temp |= (0UL << PORT2_PDR0_PD5_Pos);
286  PORT2->PDR0 = temp;
287 
288  //Select output driver strength for ETH0.TXD0 (P2.8) and ETH0.TXD1 (P2.9)
289  temp = PORT2->PDR1;
290  temp &= ~(PORT2_PDR1_PD8_Msk | PORT2_PDR1_PD9_Msk);
291  temp |= (0UL << PORT2_PDR1_PD8_Pos) | (0UL << PORT2_PDR1_PD9_Pos);
292  PORT2->PDR1 = temp;
293 
294  //Use ETH0.CLK_RMIIC (P15.8) and ETH0.CRS_DVC (P15.9) as digital inputs
295  PORT15->PDISC &= ~(PORT15_PDISC_PDIS8_Msk | PORT15_PDISC_PDIS9_Msk);
296 
297  //Select RMII operation mode
298  ETH0_CON->CON = ETH_CON_INFSEL_Msk | ETH_CON_MDIO_B | ETH_CON_RXER_A |
300 #endif
301 }
302 
303 
304 /**
305  * @brief Initialize DMA descriptor lists
306  * @param[in] interface Underlying network interface
307  **/
308 
310 {
311  uint_t i;
312 
313  //Initialize TX DMA descriptor list
314  for(i = 0; i < XMC4500_ETH_TX_BUFFER_COUNT; i++)
315  {
316  //Use chain structure rather than ring structure
317  txDmaDesc[i].tdes0 = ETH_TDES0_IC | ETH_TDES0_TCH;
318  //Initialize transmit buffer size
319  txDmaDesc[i].tdes1 = 0;
320  //Transmit buffer address
321  txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
322  //Next descriptor address
323  txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
324  }
325 
326  //The last descriptor is chained to the first entry
327  txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
328  //Point to the very first descriptor
329  txCurDmaDesc = &txDmaDesc[0];
330 
331  //Initialize RX DMA descriptor list
332  for(i = 0; i < XMC4500_ETH_RX_BUFFER_COUNT; i++)
333  {
334  //The descriptor is initially owned by the DMA
335  rxDmaDesc[i].rdes0 = ETH_RDES0_OWN;
336  //Use chain structure rather than ring structure
338  //Receive buffer address
339  rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
340  //Next descriptor address
341  rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
342  }
343 
344  //The last descriptor is chained to the first entry
345  rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
346  //Point to the very first descriptor
347  rxCurDmaDesc = &rxDmaDesc[0];
348 
349  //Start location of the TX descriptor list
350  ETH0->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t) txDmaDesc;
351  //Start location of the RX descriptor list
352  ETH0->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t) rxDmaDesc;
353 }
354 
355 
356 /**
357  * @brief XMC4500 Ethernet MAC timer handler
358  *
359  * This routine is periodically called by the TCP/IP stack to handle periodic
360  * operations such as polling the link state
361  *
362  * @param[in] interface Underlying network interface
363  **/
364 
365 void xmc4500EthTick(NetInterface *interface)
366 {
367  //Valid Ethernet PHY or switch driver?
368  if(interface->phyDriver != NULL)
369  {
370  //Handle periodic operations
371  interface->phyDriver->tick(interface);
372  }
373  else if(interface->switchDriver != NULL)
374  {
375  //Handle periodic operations
376  interface->switchDriver->tick(interface);
377  }
378  else
379  {
380  //Just for sanity
381  }
382 }
383 
384 
385 /**
386  * @brief Enable interrupts
387  * @param[in] interface Underlying network interface
388  **/
389 
391 {
392  //Enable Ethernet MAC interrupts
393  NVIC_EnableIRQ(ETH0_0_IRQn);
394 
395  //Valid Ethernet PHY or switch driver?
396  if(interface->phyDriver != NULL)
397  {
398  //Enable Ethernet PHY interrupts
399  interface->phyDriver->enableIrq(interface);
400  }
401  else if(interface->switchDriver != NULL)
402  {
403  //Enable Ethernet switch interrupts
404  interface->switchDriver->enableIrq(interface);
405  }
406  else
407  {
408  //Just for sanity
409  }
410 }
411 
412 
413 /**
414  * @brief Disable interrupts
415  * @param[in] interface Underlying network interface
416  **/
417 
419 {
420  //Disable Ethernet MAC interrupts
421  NVIC_DisableIRQ(ETH0_0_IRQn);
422 
423  //Valid Ethernet PHY or switch driver?
424  if(interface->phyDriver != NULL)
425  {
426  //Disable Ethernet PHY interrupts
427  interface->phyDriver->disableIrq(interface);
428  }
429  else if(interface->switchDriver != NULL)
430  {
431  //Disable Ethernet switch interrupts
432  interface->switchDriver->disableIrq(interface);
433  }
434  else
435  {
436  //Just for sanity
437  }
438 }
439 
440 
441 /**
442  * @brief XMC4500 Ethernet MAC interrupt service routine
443  **/
444 
446 {
447  bool_t flag;
448  uint32_t status;
449 
450  //Interrupt service routine prologue
451  osEnterIsr();
452 
453  //This flag will be set if a higher priority task must be woken
454  flag = FALSE;
455 
456  //Read DMA status register
457  status = ETH0->STATUS;
458 
459  //Packet transmitted?
460  if((status & ETH_STATUS_TI_Msk) != 0)
461  {
462  //Clear TI interrupt flag
463  ETH0->STATUS = ETH_STATUS_TI_Msk;
464 
465  //Check whether the TX buffer is available for writing
466  if((txCurDmaDesc->tdes0 & ETH_TDES0_OWN) == 0)
467  {
468  //Notify the TCP/IP stack that the transmitter is ready to send
469  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
470  }
471  }
472 
473  //Packet received?
474  if((status & ETH_STATUS_RI_Msk) != 0)
475  {
476  //Clear RI interrupt flag
477  ETH0->STATUS = ETH_STATUS_RI_Msk;
478 
479  //Set event flag
480  nicDriverInterface->nicEvent = TRUE;
481  //Notify the TCP/IP stack of the event
482  flag |= osSetEventFromIsr(&netEvent);
483  }
484 
485  //Clear NIS interrupt flag
486  ETH0->STATUS = ETH_STATUS_NIS_Msk;
487 
488  //Interrupt service routine epilogue
489  osExitIsr(flag);
490 }
491 
492 
493 /**
494  * @brief XMC4500 Ethernet MAC event handler
495  * @param[in] interface Underlying network interface
496  **/
497 
499 {
500  error_t error;
501 
502  //Process all pending packets
503  do
504  {
505  //Read incoming packet
506  error = xmc4500EthReceivePacket(interface);
507 
508  //No more data in the receive buffer?
509  } while(error != ERROR_BUFFER_EMPTY);
510 }
511 
512 
513 /**
514  * @brief Send a packet
515  * @param[in] interface Underlying network interface
516  * @param[in] buffer Multi-part buffer containing the data to send
517  * @param[in] offset Offset to the first data byte
518  * @param[in] ancillary Additional options passed to the stack along with
519  * the packet
520  * @return Error code
521  **/
522 
524  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
525 {
526  size_t length;
527 
528  //Retrieve the length of the packet
529  length = netBufferGetLength(buffer) - offset;
530 
531  //Check the frame length
533  {
534  //The transmitter can accept another packet
535  osSetEvent(&interface->nicTxEvent);
536  //Report an error
537  return ERROR_INVALID_LENGTH;
538  }
539 
540  //Make sure the current buffer is available for writing
541  if((txCurDmaDesc->tdes0 & ETH_TDES0_OWN) != 0)
542  {
543  return ERROR_FAILURE;
544  }
545 
546  //Copy user data to the transmit buffer
547  netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
548 
549  //Write the number of bytes to send
550  txCurDmaDesc->tdes1 = length & ETH_TDES1_TBS1;
551  //Set LS and FS flags as the data fits in a single buffer
552  txCurDmaDesc->tdes0 |= ETH_TDES0_LS | ETH_TDES0_FS;
553  //Give the ownership of the descriptor to the DMA
554  txCurDmaDesc->tdes0 |= ETH_TDES0_OWN;
555 
556  //Clear TU flag to resume processing
557  ETH0->STATUS = ETH_STATUS_TU_Msk;
558  //Instruct the DMA to poll the transmit descriptor list
559  ETH0->TRANSMIT_POLL_DEMAND = 0;
560 
561  //Point to the next descriptor in the list
562  txCurDmaDesc = (Xmc4500TxDmaDesc *) txCurDmaDesc->tdes3;
563 
564  //Check whether the next buffer is available for writing
565  if((txCurDmaDesc->tdes0 & ETH_TDES0_OWN) == 0)
566  {
567  //The transmitter can accept another packet
568  osSetEvent(&interface->nicTxEvent);
569  }
570 
571  //Data successfully written
572  return NO_ERROR;
573 }
574 
575 
576 /**
577  * @brief Receive a packet
578  * @param[in] interface Underlying network interface
579  * @return Error code
580  **/
581 
583 {
584  error_t error;
585  size_t n;
586  NetRxAncillary ancillary;
587 
588  //Current buffer available for reading?
589  if((rxCurDmaDesc->rdes0 & ETH_RDES0_OWN) == 0)
590  {
591  //FS and LS flags should be set
592  if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) != 0 &&
593  (rxCurDmaDesc->rdes0 & ETH_RDES0_LS) != 0)
594  {
595  //Make sure no error occurred
596  if((rxCurDmaDesc->rdes0 & ETH_RDES0_ES) == 0)
597  {
598  //Retrieve the length of the frame
599  n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
600  //Limit the number of data to read
602 
603  //Additional options can be passed to the stack along with the packet
604  ancillary = NET_DEFAULT_RX_ANCILLARY;
605 
606  //Pass the packet to the upper layer
607  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n,
608  &ancillary);
609 
610  //Valid packet received
611  error = NO_ERROR;
612  }
613  else
614  {
615  //The received packet contains an error
616  error = ERROR_INVALID_PACKET;
617  }
618  }
619  else
620  {
621  //The packet is not valid
622  error = ERROR_INVALID_PACKET;
623  }
624 
625  //Give the ownership of the descriptor back to the DMA
626  rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
627  //Point to the next descriptor in the list
628  rxCurDmaDesc = (Xmc4500RxDmaDesc *) rxCurDmaDesc->rdes3;
629  }
630  else
631  {
632  //No more data in the receive buffer
633  error = ERROR_BUFFER_EMPTY;
634  }
635 
636  //Clear RU flag to resume processing
637  ETH0->STATUS = ETH_STATUS_RU_Msk;
638  //Instruct the DMA to poll the receive descriptor list
639  ETH0->RECEIVE_POLL_DEMAND = 0;
640 
641  //Return status code
642  return error;
643 }
644 
645 
646 /**
647  * @brief Configure MAC address filtering
648  * @param[in] interface Underlying network interface
649  * @return Error code
650  **/
651 
653 {
654  uint_t i;
655  uint_t j;
656  uint_t k;
657  uint32_t crc;
658  uint32_t hashTable[2];
659  MacAddr unicastMacAddr[3];
660  MacFilterEntry *entry;
661 
662  //Debug message
663  TRACE_DEBUG("Updating MAC filter...\r\n");
664 
665  //Set the MAC address of the station
666  ETH0->MAC_ADDRESS0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
667  ETH0->MAC_ADDRESS0_HIGH = interface->macAddr.w[2];
668 
669  //The MAC supports 3 additional addresses for unicast perfect filtering
670  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
671  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
672  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
673 
674  //The hash table is used for multicast address filtering
675  hashTable[0] = 0;
676  hashTable[1] = 0;
677 
678  //The MAC address filter contains the list of MAC addresses to accept
679  //when receiving an Ethernet frame
680  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
681  {
682  //Point to the current entry
683  entry = &interface->macAddrFilter[i];
684 
685  //Valid entry?
686  if(entry->refCount > 0)
687  {
688  //Multicast address?
689  if(macIsMulticastAddr(&entry->addr))
690  {
691  //Compute CRC over the current MAC address
692  crc = xmc4500EthCalcCrc(&entry->addr, sizeof(MacAddr));
693 
694  //The upper 6 bits in the CRC register are used to index the
695  //contents of the hash table
696  k = (crc >> 26) & 0x3F;
697 
698  //Update hash table contents
699  hashTable[k / 32] |= (1 << (k % 32));
700  }
701  else
702  {
703  //Up to 3 additional MAC addresses can be specified
704  if(j < 3)
705  {
706  //Save the unicast address
707  unicastMacAddr[j++] = entry->addr;
708  }
709  }
710  }
711  }
712 
713  //Configure the first unicast address filter
714  if(j >= 1)
715  {
716  //When the AE bit is set, the entry is used for perfect filtering
717  ETH0->MAC_ADDRESS1_LOW = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
718  ETH0->MAC_ADDRESS1_HIGH = unicastMacAddr[0].w[2] | ETH_MAC_ADDRESS1_HIGH_AE_Msk;
719  }
720  else
721  {
722  //When the AE bit is cleared, the entry is ignored
723  ETH0->MAC_ADDRESS1_LOW = 0;
724  ETH0->MAC_ADDRESS1_HIGH = 0;
725  }
726 
727  //Configure the second unicast address filter
728  if(j >= 2)
729  {
730  //When the AE bit is set, the entry is used for perfect filtering
731  ETH0->MAC_ADDRESS2_LOW = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
732  ETH0->MAC_ADDRESS2_HIGH = unicastMacAddr[1].w[2] | ETH_MAC_ADDRESS2_HIGH_AE_Msk;
733  }
734  else
735  {
736  //When the AE bit is cleared, the entry is ignored
737  ETH0->MAC_ADDRESS2_LOW = 0;
738  ETH0->MAC_ADDRESS2_HIGH = 0;
739  }
740 
741  //Configure the third unicast address filter
742  if(j >= 3)
743  {
744  //When the AE bit is set, the entry is used for perfect filtering
745  ETH0->MAC_ADDRESS3_LOW = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
746  ETH0->MAC_ADDRESS3_HIGH = unicastMacAddr[2].w[2] | ETH_MAC_ADDRESS3_HIGH_AE_Msk;
747  }
748  else
749  {
750  //When the AE bit is cleared, the entry is ignored
751  ETH0->MAC_ADDRESS3_LOW = 0;
752  ETH0->MAC_ADDRESS3_HIGH = 0;
753  }
754 
755  //Configure the multicast hash table
756  ETH0->HASH_TABLE_LOW = hashTable[0];
757  ETH0->HASH_TABLE_HIGH = hashTable[1];
758 
759  //Debug message
760  TRACE_DEBUG(" HASH_TABLE_LOW = %08" PRIX32 "\r\n", ETH0->HASH_TABLE_LOW);
761  TRACE_DEBUG(" HASH_TABLE_HIGH = %08" PRIX32 "\r\n", ETH0->HASH_TABLE_HIGH);
762 
763  //Successful processing
764  return NO_ERROR;
765 }
766 
767 
768 /**
769  * @brief Adjust MAC configuration parameters for proper operation
770  * @param[in] interface Underlying network interface
771  * @return Error code
772  **/
773 
775 {
776  uint32_t config;
777 
778  //Read current MAC configuration
779  config = ETH0->MAC_CONFIGURATION;
780 
781  //10BASE-T or 100BASE-TX operation mode?
782  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
783  {
784  config |= ETH_MAC_CONFIGURATION_FES_Msk;
785  }
786  else
787  {
788  config &= ~ETH_MAC_CONFIGURATION_FES_Msk;
789  }
790 
791  //Half-duplex or full-duplex mode?
792  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
793  {
794  config |= ETH_MAC_CONFIGURATION_DM_Msk;
795  }
796  else
797  {
798  config &= ~ETH_MAC_CONFIGURATION_DM_Msk;
799  }
800 
801  //Update MAC configuration register
802  ETH0->MAC_CONFIGURATION = config;
803 
804  //Successful processing
805  return NO_ERROR;
806 }
807 
808 
809 /**
810  * @brief Write PHY register
811  * @param[in] opcode Access type (2 bits)
812  * @param[in] phyAddr PHY address (5 bits)
813  * @param[in] regAddr Register address (5 bits)
814  * @param[in] data Register value
815  **/
816 
817 void xmc4500EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
818  uint8_t regAddr, uint16_t data)
819 {
820  uint32_t temp;
821 
822  //Valid opcode?
823  if(opcode == SMI_OPCODE_WRITE)
824  {
825  //Take care not to alter MDC clock configuration
826  temp = ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_CR_Msk;
827  //Set up a write operation
828  temp |= ETH_GMII_ADDRESS_MW_Msk | ETH_GMII_ADDRESS_MB_Msk;
829  //PHY address
830  temp |= (phyAddr << ETH_GMII_ADDRESS_PA_Pos) & ETH_GMII_ADDRESS_PA_Msk;
831  //Register address
832  temp |= (regAddr << ETH_GMII_ADDRESS_MR_Pos) & ETH_GMII_ADDRESS_MR_Msk;
833 
834  //Data to be written in the PHY register
835  ETH0->GMII_DATA = data & ETH_GMII_DATA_MD_Msk;
836 
837  //Start a write operation
838  ETH0->GMII_ADDRESS = temp;
839  //Wait for the write to complete
840  while((ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0)
841  {
842  }
843  }
844  else
845  {
846  //The MAC peripheral only supports standard Clause 22 opcodes
847  }
848 }
849 
850 
851 /**
852  * @brief Read PHY register
853  * @param[in] opcode Access type (2 bits)
854  * @param[in] phyAddr PHY address (5 bits)
855  * @param[in] regAddr Register address (5 bits)
856  * @return Register value
857  **/
858 
859 uint16_t xmc4500EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
860  uint8_t regAddr)
861 {
862  uint16_t data;
863  uint32_t temp;
864 
865  //Valid opcode?
866  if(opcode == SMI_OPCODE_READ)
867  {
868  //Take care not to alter MDC clock configuration
869  temp = ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_CR_Msk;
870  //Set up a read operation
871  temp |= ETH_GMII_ADDRESS_MB_Msk;
872  //PHY address
873  temp |= (phyAddr << ETH_GMII_ADDRESS_PA_Pos) & ETH_GMII_ADDRESS_PA_Msk;
874  //Register address
875  temp |= (regAddr << ETH_GMII_ADDRESS_MR_Pos) & ETH_GMII_ADDRESS_MR_Msk;
876 
877  //Start a read operation
878  ETH0->GMII_ADDRESS = temp;
879  //Wait for the read to complete
880  while((ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0)
881  {
882  }
883 
884  //Get register value
885  data = ETH0->GMII_DATA & ETH_GMII_DATA_MD_Msk;
886  }
887  else
888  {
889  //The MAC peripheral only supports standard Clause 22 opcodes
890  data = 0;
891  }
892 
893  //Return the value of the PHY register
894  return data;
895 }
896 
897 
898 /**
899  * @brief CRC calculation
900  * @param[in] data Pointer to the data over which to calculate the CRC
901  * @param[in] length Number of bytes to process
902  * @return Resulting CRC value
903  **/
904 
905 uint32_t xmc4500EthCalcCrc(const void *data, size_t length)
906 {
907  uint_t i;
908  uint_t j;
909  uint32_t crc;
910  const uint8_t *p;
911 
912  //Point to the data over which to calculate the CRC
913  p = (uint8_t *) data;
914  //CRC preset value
915  crc = 0xFFFFFFFF;
916 
917  //Loop through data
918  for(i = 0; i < length; i++)
919  {
920  //The message is processed bit by bit
921  for(j = 0; j < 8; j++)
922  {
923  //Update CRC value
924  if((((crc >> 31) ^ (p[i] >> j)) & 0x01) != 0)
925  {
926  crc = (crc << 1) ^ 0x04C11DB7;
927  }
928  else
929  {
930  crc = crc << 1;
931  }
932  }
933  }
934 
935  //Return CRC value
936  return ~crc;
937 }
#define txDmaDesc
#define rxBuffer
#define txBuffer
#define rxDmaDesc
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
#define ETH_TDES0_OWN
#define ETH_RDES0_FS
#define ETH_TDES0_IC
#define ETH_RDES1_RCH
#define ETH_RDES0_OWN
#define ETH_RDES0_LS
#define ETH_RDES0_FL
#define ETH_RDES0_ES
#define ETH_TDES0_LS
#define ETH_RDES1_RBS1
#define ETH_TDES0_TCH
#define ETH_TDES0_FS
#define ETH_TDES1_TBS1
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive DMA descriptor.
Transmit DMA descriptor.
uint8_t length
Definition: tcp.h:368
#define ETH_GMII_ADDRESS_CR_DIV62
#define ETH_BUS_MODE_PR_1_1
#define ETH_BUS_MODE_PBL_32
#define ETH_MAC_CONFIGURATION_RESERVED15_Msk
#define ETH_CON_MDIO_B
#define ETH_CON_RXD0_A
#define ETH_CON_CLK_RMII_C
#define ETH_CON_RXER_A
#define ETH_BUS_MODE_RPBL_32
#define ETH_CON_RXD1_A
#define ETH_CON_CRS_DV_C
void xmc4500EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
__weak_func void xmc4500EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t xmc4500EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void xmc4500EthEnableIrq(NetInterface *interface)
Enable interrupts.
void xmc4500EthEventHandler(NetInterface *interface)
XMC4500 Ethernet MAC event handler.
const NicDriver xmc4500EthDriver
XMC4500 Ethernet MAC driver.
uint16_t xmc4500EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void ETH0_0_IRQHandler(void)
XMC4500 Ethernet MAC interrupt service routine.
error_t xmc4500EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void xmc4500EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t xmc4500EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void xmc4500EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t xmc4500EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t xmc4500EthInit(NetInterface *interface)
XMC4500 Ethernet MAC initialization.
void xmc4500EthTick(NetInterface *interface)
XMC4500 Ethernet MAC timer handler.
uint32_t xmc4500EthCalcCrc(const void *data, size_t length)
CRC calculation.
Infineon XMC4500 Ethernet MAC driver.
#define XMC4500_ETH_RX_BUFFER_SIZE
#define XMC4500_ETH_TX_BUFFER_COUNT
#define XMC4500_ETH_TX_BUFFER_SIZE
#define XMC4500_ETH_RAM_SECTION
#define XMC4500_ETH_RX_BUFFER_COUNT
#define XMC4500_ETH_IRQ_SUB_PRIORITY
#define XMC4500_ETH_IRQ_GROUP_PRIORITY
#define XMC4500_ETH_IRQ_PRIORITY_GROUPING