Data Structures | Macros | Functions | Variables
zynq7000_eth_driver.h File Reference

Zynq-7000 Gigabit Ethernet MAC driver. More...

Go to the source code of this file.

Data Structures

struct  Zynq7000TxBufferDesc
 Transmit buffer descriptor. More...
 
struct  Zynq7000RxBufferDesc
 Receive buffer descriptor. More...
 

Macros

#define ZYNQ7000_ETH_TX_BUFFER_COUNT   16
 
#define ZYNQ7000_ETH_TX_BUFFER_SIZE   1536
 
#define ZYNQ7000_ETH_RX_BUFFER_COUNT   16
 
#define ZYNQ7000_ETH_RX_BUFFER_SIZE   1536
 
#define ZYNQ7000_ETH_IRQ_PRIORITY   160
 
#define ZYNQ7000_ETH_RAM_SECTION   ".ram_no_cache"
 
#define _HW_REG(address)   *((volatile uint32_t *) (address))
 
#define XSLCR_LOCK   _HW_REG(XSLCR_UNLOCK_ADDR - 4)
 
#define XSLCR_UNLOCK   _HW_REG(XSLCR_UNLOCK_ADDR)
 
#define XSLCR_GEM0_RCLK_CTRL   _HW_REG(XSLCR_GEM0_RCLK_CTRL_ADDR)
 
#define XSLCR_GEM0_CLK_CTRL   _HW_REG(XSLCR_GEM0_CLK_CTRL_ADDR)
 
#define XEMACPS_NWCTRL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCTRL_OFFSET)
 
#define XEMACPS_NWCFG   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCFG_OFFSET)
 
#define XEMACPS_NWSR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWSR_OFFSET)
 
#define XEMACPS_DMACR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_DMACR_OFFSET)
 
#define XEMACPS_TXSR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXSR_OFFSET)
 
#define XEMACPS_RXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQBASE_OFFSET)
 
#define XEMACPS_TXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQBASE_OFFSET)
 
#define XEMACPS_RXSR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSR_OFFSET)
 
#define XEMACPS_ISR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_ISR_OFFSET)
 
#define XEMACPS_IER   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IER_OFFSET)
 
#define XEMACPS_IDR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IDR_OFFSET)
 
#define XEMACPS_IMR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IMR_OFFSET)
 
#define XEMACPS_PHYMNTNC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PHYMNTNC_OFFSET)
 
#define XEMACPS_RXPAUSE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSE_OFFSET)
 
#define XEMACPS_TXPAUSE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSE_OFFSET)
 
#define XEMACPS_JUMBOMAXLEN   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_JUMBOMAXLEN_OFFSET)
 
#define XEMACPS_HASHL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHL_OFFSET)
 
#define XEMACPS_HASHH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHH_OFFSET)
 
#define XEMACPS_LADDR1L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1L_OFFSET)
 
#define XEMACPS_LADDR1H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1H_OFFSET)
 
#define XEMACPS_LADDR2L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2L_OFFSET)
 
#define XEMACPS_LADDR2H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2H_OFFSET)
 
#define XEMACPS_LADDR3L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3L_OFFSET)
 
#define XEMACPS_LADDR3H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3H_OFFSET)
 
#define XEMACPS_LADDR4L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4L_OFFSET)
 
#define XEMACPS_LADDR4H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4H_OFFSET)
 
#define XEMACPS_MATCH1   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH1_OFFSET)
 
#define XEMACPS_MATCH2   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH2_OFFSET)
 
#define XEMACPS_MATCH3   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH3_OFFSET)
 
#define XEMACPS_MATCH4   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH4_OFFSET)
 
#define XEMACPS_STRETCH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_STRETCH_OFFSET)
 
#define XEMACPS_OCTTXL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXL_OFFSET)
 
#define XEMACPS_OCTTXH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXH_OFFSET)
 
#define XEMACPS_TXCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCNT_OFFSET)
 
#define XEMACPS_TXBCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXBCCNT_OFFSET)
 
#define XEMACPS_TXMCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXMCCNT_OFFSET)
 
#define XEMACPS_TXPAUSECNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSECNT_OFFSET)
 
#define XEMACPS_TX64CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX64CNT_OFFSET)
 
#define XEMACPS_TX65CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX65CNT_OFFSET)
 
#define XEMACPS_TX128CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX128CNT_OFFSET)
 
#define XEMACPS_TX256CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX256CNT_OFFSET)
 
#define XEMACPS_TX512CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX512CNT_OFFSET)
 
#define XEMACPS_TX1024CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1024CNT_OFFSET)
 
#define XEMACPS_TX1519CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1519CNT_OFFSET)
 
#define XEMACPS_TXURUNCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXURUNCNT_OFFSET)
 
#define XEMACPS_SNGLCOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_SNGLCOLLCNT_OFFSET)
 
#define XEMACPS_MULTICOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MULTICOLLCNT_OFFSET)
 
#define XEMACPS_EXCESSCOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_EXCESSCOLLCNT_OFFSET)
 
#define XEMACPS_LATECOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LATECOLLCNT_OFFSET)
 
#define XEMACPS_TXDEFERCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXDEFERCNT_OFFSET)
 
#define XEMACPS_TXCSENSECNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCSENSECNT_OFFSET)
 
#define XEMACPS_OCTRXL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXL_OFFSET)
 
#define XEMACPS_OCTRXH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXH_OFFSET)
 
#define XEMACPS_RXCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXCNT_OFFSET)
 
#define XEMACPS_RXBROADCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXBROADCNT_OFFSET)
 
#define XEMACPS_RXMULTICNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXMULTICNT_OFFSET)
 
#define XEMACPS_RXPAUSECNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSECNT_OFFSET)
 
#define XEMACPS_RX64CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX64CNT_OFFSET)
 
#define XEMACPS_RX65CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX65CNT_OFFSET)
 
#define XEMACPS_RX128CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX128CNT_OFFSET)
 
#define XEMACPS_RX256CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX256CNT_OFFSET)
 
#define XEMACPS_RX512CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX512CNT_OFFSET)
 
#define XEMACPS_RX1024CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1024CNT_OFFSET)
 
#define XEMACPS_RX1519CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1519CNT_OFFSET)
 
#define XEMACPS_RXUNDRCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUNDRCNT_OFFSET)
 
#define XEMACPS_RXOVRCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXOVRCNT_OFFSET)
 
#define XEMACPS_RXJABCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXJABCNT_OFFSET)
 
#define XEMACPS_RXFCSCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXFCSCNT_OFFSET)
 
#define XEMACPS_RXLENGTHCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXLENGTHCNT_OFFSET)
 
#define XEMACPS_RXSYMBCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSYMBCNT_OFFSET)
 
#define XEMACPS_RXALIGNCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXALIGNCNT_OFFSET)
 
#define XEMACPS_RXRESERRCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXRESERRCNT_OFFSET)
 
#define XEMACPS_RXORCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXORCNT_OFFSET)
 
#define XEMACPS_RXIPCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXIPCCNT_OFFSET)
 
#define XEMACPS_RXTCPCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXTCPCCNT_OFFSET)
 
#define XEMACPS_RXUDPCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUDPCCNT_OFFSET)
 
#define XEMACPS_LAST   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LAST_OFFSET)
 
#define XEMACPS_1588_SEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_SEC_OFFSET)
 
#define XEMACPS_1588_NANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_NANOSEC_OFFSET)
 
#define XEMACPS_1588_ADJ   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_ADJ_OFFSET)
 
#define XEMACPS_1588_INC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_INC_OFFSET)
 
#define XEMACPS_PTP_TXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXSEC_OFFSET)
 
#define XEMACPS_PTP_TXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXNANOSEC_OFFSET)
 
#define XEMACPS_PTP_RXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXSEC_OFFSET)
 
#define XEMACPS_PTP_RXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXNANOSEC_OFFSET)
 
#define XEMACPS_PTPP_TXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXSEC_OFFSET)
 
#define XEMACPS_PTPP_TXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXNANOSEC_OFFSET)
 
#define XEMACPS_PTPP_RXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXSEC_OFFSET)
 
#define XEMACPS_PTPP_RXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXNANOSEC_OFFSET)
 
#define XEMACPS_INTQ1_STS   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_STS_OFFSET)
 
#define XEMACPS_TXQ1BASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQ1BASE_OFFSET)
 
#define XEMACPS_RXQ1BASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQ1BASE_OFFSET)
 
#define XEMACPS_MSBBUF_TXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_TXQBASE_OFFSET)
 
#define XEMACPS_MSBBUF_RXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_RXQBASE_OFFSET)
 
#define XEMACPS_INTQ1_IER   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IER_OFFSET)
 
#define XEMACPS_INTQ1_IDR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IDR_OFFSET)
 
#define XEMACPS_INTQ1_IMR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IMR_OFFSET)
 
#define XSLCR_LOCK_KEY_VALUE   0x0000767B;
 
#define XSLCR_UNLOCK_KEY_VALUE   0x0000DF0D;
 
#define XSLCR_GEM0_RCLK_CTRL_SRCSEL_MASK   0x00000010
 
#define XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK   0x00000001
 
#define XSLCR_GEM0_CLK_CTRL_DIV1_MASK   0x03F00000
 
#define XSLCR_GEM0_CLK_CTRL_DIV0_MASK   0x00003F00
 
#define XSLCR_GEM0_CLK_CTRL_SRCSEL_MASK   0x00000070
 
#define XSLCR_GEM0_CLK_CTRL_CLKACT_MASK   0x00000001
 
#define XEMACPS_TX_USED   0x80000000
 
#define XEMACPS_TX_WRAP   0x40000000
 
#define XEMACPS_TX_RLE_ERROR   0x20000000
 
#define XEMACPS_TX_UNDERRUN_ERROR   0x10000000
 
#define XEMACPS_TX_AHB_ERROR   0x08000000
 
#define XEMACPS_TX_LATE_COL_ERROR   0x04000000
 
#define XEMACPS_TX_CHECKSUM_ERROR   0x00700000
 
#define XEMACPS_TX_NO_CRC   0x00010000
 
#define XEMACPS_TX_LAST   0x00008000
 
#define XEMACPS_TX_LENGTH   0x00003FFF
 
#define XEMACPS_RX_ADDRESS   0xFFFFFFFC
 
#define XEMACPS_RX_WRAP   0x00000002
 
#define XEMACPS_RX_OWNERSHIP   0x00000001
 
#define XEMACPS_RX_BROADCAST   0x80000000
 
#define XEMACPS_RX_MULTICAST_HASH   0x40000000
 
#define XEMACPS_RX_UNICAST_HASH   0x20000000
 
#define XEMACPS_RX_SAR   0x08000000
 
#define XEMACPS_RX_SAR_MASK   0x06000000
 
#define XEMACPS_RX_TYPE_ID   0x01000000
 
#define XEMACPS_RX_SNAP   0x01000000
 
#define XEMACPS_RX_TYPE_ID_MASK   0x00C00000
 
#define XEMACPS_RX_CHECKSUM_VALID   0x00C00000
 
#define XEMACPS_RX_VLAN_TAG   0x00200000
 
#define XEMACPS_RX_PRIORITY_TAG   0x00100000
 
#define XEMACPS_RX_VLAN_PRIORITY   0x000E0000
 
#define XEMACPS_RX_CFI   0x00010000
 
#define XEMACPS_RX_EOF   0x00008000
 
#define XEMACPS_RX_SOF   0x00004000
 
#define XEMACPS_RX_LENGTH_MSB   0x00002000
 
#define XEMACPS_RX_BAD_FCS   0x00002000
 
#define XEMACPS_RX_LENGTH   0x00001FFF
 

Functions

error_t zynq7000EthInit (NetInterface *interface)
 Zynq-7000 Ethernet MAC initialization. More...
 
void zynq7000EthInitBufferDesc (NetInterface *interface)
 Initialize buffer descriptors. More...
 
void zynq7000EthTick (NetInterface *interface)
 Zynq-7000 Ethernet MAC timer handler. More...
 
void zynq7000EthEnableIrq (NetInterface *interface)
 Enable interrupts. More...
 
void zynq7000EthDisableIrq (NetInterface *interface)
 Disable interrupts. More...
 
void zynq7000EthIrqHandler (NetInterface *interface)
 Zynq-7000 Ethernet MAC interrupt service routine. More...
 
void zynq7000EthEventHandler (NetInterface *interface)
 Zynq-7000 Ethernet MAC event handler. More...
 
error_t zynq7000EthSendPacket (NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
 Send a packet. More...
 
error_t zynq7000EthReceivePacket (NetInterface *interface)
 Receive a packet. More...
 
error_t zynq7000EthUpdateMacAddrFilter (NetInterface *interface)
 Configure MAC address filtering. More...
 
error_t zynq7000EthUpdateMacConfig (NetInterface *interface)
 Adjust MAC configuration parameters for proper operation. More...
 
void zynq7000EthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
 Write PHY register. More...
 
uint16_t zynq7000EthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
 Read PHY register. More...
 

Variables

const NicDriver zynq7000EthDriver
 Zynq-7000 Ethernet MAC driver. More...
 

Detailed Description

Zynq-7000 Gigabit Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author
Oryx Embedded SARL (www.oryx-embedded.com)
Version
2.4.4

Definition in file zynq7000_eth_driver.h.

Macro Definition Documentation

◆ _HW_REG

#define _HW_REG (   address)    *((volatile uint32_t *) (address))

Definition at line 75 of file zynq7000_eth_driver.h.

◆ XEMACPS_1588_ADJ

#define XEMACPS_1588_ADJ   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_ADJ_OFFSET)

Definition at line 161 of file zynq7000_eth_driver.h.

◆ XEMACPS_1588_INC

#define XEMACPS_1588_INC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_INC_OFFSET)

Definition at line 162 of file zynq7000_eth_driver.h.

◆ XEMACPS_1588_NANOSEC

#define XEMACPS_1588_NANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_NANOSEC_OFFSET)

Definition at line 160 of file zynq7000_eth_driver.h.

◆ XEMACPS_1588_SEC

#define XEMACPS_1588_SEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_SEC_OFFSET)

Definition at line 159 of file zynq7000_eth_driver.h.

◆ XEMACPS_DMACR

#define XEMACPS_DMACR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_DMACR_OFFSET)

Definition at line 85 of file zynq7000_eth_driver.h.

◆ XEMACPS_EXCESSCOLLCNT

#define XEMACPS_EXCESSCOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_EXCESSCOLLCNT_OFFSET)

Definition at line 129 of file zynq7000_eth_driver.h.

◆ XEMACPS_HASHH

#define XEMACPS_HASHH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHH_OFFSET)

Definition at line 99 of file zynq7000_eth_driver.h.

◆ XEMACPS_HASHL

#define XEMACPS_HASHL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHL_OFFSET)

Definition at line 98 of file zynq7000_eth_driver.h.

◆ XEMACPS_IDR

#define XEMACPS_IDR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IDR_OFFSET)

Definition at line 92 of file zynq7000_eth_driver.h.

◆ XEMACPS_IER

#define XEMACPS_IER   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IER_OFFSET)

Definition at line 91 of file zynq7000_eth_driver.h.

◆ XEMACPS_IMR

#define XEMACPS_IMR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IMR_OFFSET)

Definition at line 93 of file zynq7000_eth_driver.h.

◆ XEMACPS_INTQ1_IDR

#define XEMACPS_INTQ1_IDR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IDR_OFFSET)

Definition at line 177 of file zynq7000_eth_driver.h.

◆ XEMACPS_INTQ1_IER

#define XEMACPS_INTQ1_IER   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IER_OFFSET)

Definition at line 176 of file zynq7000_eth_driver.h.

◆ XEMACPS_INTQ1_IMR

#define XEMACPS_INTQ1_IMR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IMR_OFFSET)

Definition at line 178 of file zynq7000_eth_driver.h.

◆ XEMACPS_INTQ1_STS

#define XEMACPS_INTQ1_STS   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_STS_OFFSET)

Definition at line 171 of file zynq7000_eth_driver.h.

◆ XEMACPS_ISR

#define XEMACPS_ISR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_ISR_OFFSET)

Definition at line 90 of file zynq7000_eth_driver.h.

◆ XEMACPS_JUMBOMAXLEN

#define XEMACPS_JUMBOMAXLEN   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_JUMBOMAXLEN_OFFSET)

Definition at line 97 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR1H

#define XEMACPS_LADDR1H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1H_OFFSET)

Definition at line 101 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR1L

#define XEMACPS_LADDR1L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1L_OFFSET)

Definition at line 100 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR2H

#define XEMACPS_LADDR2H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2H_OFFSET)

Definition at line 103 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR2L

#define XEMACPS_LADDR2L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2L_OFFSET)

Definition at line 102 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR3H

#define XEMACPS_LADDR3H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3H_OFFSET)

Definition at line 105 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR3L

#define XEMACPS_LADDR3L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3L_OFFSET)

Definition at line 104 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR4H

#define XEMACPS_LADDR4H   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4H_OFFSET)

Definition at line 107 of file zynq7000_eth_driver.h.

◆ XEMACPS_LADDR4L

#define XEMACPS_LADDR4L   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4L_OFFSET)

Definition at line 106 of file zynq7000_eth_driver.h.

◆ XEMACPS_LAST

#define XEMACPS_LAST   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LAST_OFFSET)

Definition at line 158 of file zynq7000_eth_driver.h.

◆ XEMACPS_LATECOLLCNT

#define XEMACPS_LATECOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LATECOLLCNT_OFFSET)

Definition at line 130 of file zynq7000_eth_driver.h.

◆ XEMACPS_MATCH1

#define XEMACPS_MATCH1   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH1_OFFSET)

Definition at line 108 of file zynq7000_eth_driver.h.

◆ XEMACPS_MATCH2

#define XEMACPS_MATCH2   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH2_OFFSET)

Definition at line 109 of file zynq7000_eth_driver.h.

◆ XEMACPS_MATCH3

#define XEMACPS_MATCH3   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH3_OFFSET)

Definition at line 110 of file zynq7000_eth_driver.h.

◆ XEMACPS_MATCH4

#define XEMACPS_MATCH4   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH4_OFFSET)

Definition at line 111 of file zynq7000_eth_driver.h.

◆ XEMACPS_MSBBUF_RXQBASE

#define XEMACPS_MSBBUF_RXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_RXQBASE_OFFSET)

Definition at line 175 of file zynq7000_eth_driver.h.

◆ XEMACPS_MSBBUF_TXQBASE

#define XEMACPS_MSBBUF_TXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_TXQBASE_OFFSET)

Definition at line 174 of file zynq7000_eth_driver.h.

◆ XEMACPS_MULTICOLLCNT

#define XEMACPS_MULTICOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MULTICOLLCNT_OFFSET)

Definition at line 128 of file zynq7000_eth_driver.h.

◆ XEMACPS_NWCFG

#define XEMACPS_NWCFG   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCFG_OFFSET)

Definition at line 83 of file zynq7000_eth_driver.h.

◆ XEMACPS_NWCTRL

#define XEMACPS_NWCTRL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCTRL_OFFSET)

Definition at line 82 of file zynq7000_eth_driver.h.

◆ XEMACPS_NWSR

#define XEMACPS_NWSR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWSR_OFFSET)

Definition at line 84 of file zynq7000_eth_driver.h.

◆ XEMACPS_OCTRXH

#define XEMACPS_OCTRXH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXH_OFFSET)

Definition at line 134 of file zynq7000_eth_driver.h.

◆ XEMACPS_OCTRXL

#define XEMACPS_OCTRXL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXL_OFFSET)

Definition at line 133 of file zynq7000_eth_driver.h.

◆ XEMACPS_OCTTXH

#define XEMACPS_OCTTXH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXH_OFFSET)

Definition at line 114 of file zynq7000_eth_driver.h.

◆ XEMACPS_OCTTXL

#define XEMACPS_OCTTXL   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXL_OFFSET)

Definition at line 113 of file zynq7000_eth_driver.h.

◆ XEMACPS_PHYMNTNC

#define XEMACPS_PHYMNTNC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PHYMNTNC_OFFSET)

Definition at line 94 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTP_RXNANOSEC

#define XEMACPS_PTP_RXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXNANOSEC_OFFSET)

Definition at line 166 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTP_RXSEC

#define XEMACPS_PTP_RXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXSEC_OFFSET)

Definition at line 165 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTP_TXNANOSEC

#define XEMACPS_PTP_TXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXNANOSEC_OFFSET)

Definition at line 164 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTP_TXSEC

#define XEMACPS_PTP_TXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXSEC_OFFSET)

Definition at line 163 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTPP_RXNANOSEC

#define XEMACPS_PTPP_RXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXNANOSEC_OFFSET)

Definition at line 170 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTPP_RXSEC

#define XEMACPS_PTPP_RXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXSEC_OFFSET)

Definition at line 169 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTPP_TXNANOSEC

#define XEMACPS_PTPP_TXNANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXNANOSEC_OFFSET)

Definition at line 168 of file zynq7000_eth_driver.h.

◆ XEMACPS_PTPP_TXSEC

#define XEMACPS_PTPP_TXSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXSEC_OFFSET)

Definition at line 167 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX1024CNT

#define XEMACPS_RX1024CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1024CNT_OFFSET)

Definition at line 144 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX128CNT

#define XEMACPS_RX128CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX128CNT_OFFSET)

Definition at line 141 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX1519CNT

#define XEMACPS_RX1519CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1519CNT_OFFSET)

Definition at line 145 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX256CNT

#define XEMACPS_RX256CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX256CNT_OFFSET)

Definition at line 142 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX512CNT

#define XEMACPS_RX512CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX512CNT_OFFSET)

Definition at line 143 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX64CNT

#define XEMACPS_RX64CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX64CNT_OFFSET)

Definition at line 139 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX65CNT

#define XEMACPS_RX65CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX65CNT_OFFSET)

Definition at line 140 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_ADDRESS

#define XEMACPS_RX_ADDRESS   0xFFFFFFFC

Definition at line 215 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_BAD_FCS

#define XEMACPS_RX_BAD_FCS   0x00002000

Definition at line 234 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_BROADCAST

#define XEMACPS_RX_BROADCAST   0x80000000

Definition at line 218 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_CFI

#define XEMACPS_RX_CFI   0x00010000

Definition at line 230 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_CHECKSUM_VALID

#define XEMACPS_RX_CHECKSUM_VALID   0x00C00000

Definition at line 226 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_EOF

#define XEMACPS_RX_EOF   0x00008000

Definition at line 231 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_LENGTH

#define XEMACPS_RX_LENGTH   0x00001FFF

Definition at line 235 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_LENGTH_MSB

#define XEMACPS_RX_LENGTH_MSB   0x00002000

Definition at line 233 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_MULTICAST_HASH

#define XEMACPS_RX_MULTICAST_HASH   0x40000000

Definition at line 219 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_OWNERSHIP

#define XEMACPS_RX_OWNERSHIP   0x00000001

Definition at line 217 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_PRIORITY_TAG

#define XEMACPS_RX_PRIORITY_TAG   0x00100000

Definition at line 228 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_SAR

#define XEMACPS_RX_SAR   0x08000000

Definition at line 221 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_SAR_MASK

#define XEMACPS_RX_SAR_MASK   0x06000000

Definition at line 222 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_SNAP

#define XEMACPS_RX_SNAP   0x01000000

Definition at line 224 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_SOF

#define XEMACPS_RX_SOF   0x00004000

Definition at line 232 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_TYPE_ID

#define XEMACPS_RX_TYPE_ID   0x01000000

Definition at line 223 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_TYPE_ID_MASK

#define XEMACPS_RX_TYPE_ID_MASK   0x00C00000

Definition at line 225 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_UNICAST_HASH

#define XEMACPS_RX_UNICAST_HASH   0x20000000

Definition at line 220 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_VLAN_PRIORITY

#define XEMACPS_RX_VLAN_PRIORITY   0x000E0000

Definition at line 229 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_VLAN_TAG

#define XEMACPS_RX_VLAN_TAG   0x00200000

Definition at line 227 of file zynq7000_eth_driver.h.

◆ XEMACPS_RX_WRAP

#define XEMACPS_RX_WRAP   0x00000002

Definition at line 216 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXALIGNCNT

#define XEMACPS_RXALIGNCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXALIGNCNT_OFFSET)

Definition at line 152 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXBROADCNT

#define XEMACPS_RXBROADCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXBROADCNT_OFFSET)

Definition at line 136 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXCNT

#define XEMACPS_RXCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXCNT_OFFSET)

Definition at line 135 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXFCSCNT

#define XEMACPS_RXFCSCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXFCSCNT_OFFSET)

Definition at line 149 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXIPCCNT

#define XEMACPS_RXIPCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXIPCCNT_OFFSET)

Definition at line 155 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXJABCNT

#define XEMACPS_RXJABCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXJABCNT_OFFSET)

Definition at line 148 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXLENGTHCNT

#define XEMACPS_RXLENGTHCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXLENGTHCNT_OFFSET)

Definition at line 150 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXMULTICNT

#define XEMACPS_RXMULTICNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXMULTICNT_OFFSET)

Definition at line 137 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXORCNT

#define XEMACPS_RXORCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXORCNT_OFFSET)

Definition at line 154 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXOVRCNT

#define XEMACPS_RXOVRCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXOVRCNT_OFFSET)

Definition at line 147 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXPAUSE

#define XEMACPS_RXPAUSE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSE_OFFSET)

Definition at line 95 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXPAUSECNT

#define XEMACPS_RXPAUSECNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSECNT_OFFSET)

Definition at line 138 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXQ1BASE

#define XEMACPS_RXQ1BASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQ1BASE_OFFSET)

Definition at line 173 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXQBASE

#define XEMACPS_RXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQBASE_OFFSET)

Definition at line 87 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXRESERRCNT

#define XEMACPS_RXRESERRCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXRESERRCNT_OFFSET)

Definition at line 153 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXSR

#define XEMACPS_RXSR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSR_OFFSET)

Definition at line 89 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXSYMBCNT

#define XEMACPS_RXSYMBCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSYMBCNT_OFFSET)

Definition at line 151 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXTCPCCNT

#define XEMACPS_RXTCPCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXTCPCCNT_OFFSET)

Definition at line 156 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXUDPCCNT

#define XEMACPS_RXUDPCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUDPCCNT_OFFSET)

Definition at line 157 of file zynq7000_eth_driver.h.

◆ XEMACPS_RXUNDRCNT

#define XEMACPS_RXUNDRCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUNDRCNT_OFFSET)

Definition at line 146 of file zynq7000_eth_driver.h.

◆ XEMACPS_SNGLCOLLCNT

#define XEMACPS_SNGLCOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_SNGLCOLLCNT_OFFSET)

Definition at line 127 of file zynq7000_eth_driver.h.

◆ XEMACPS_STRETCH

#define XEMACPS_STRETCH   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_STRETCH_OFFSET)

Definition at line 112 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX1024CNT

#define XEMACPS_TX1024CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1024CNT_OFFSET)

Definition at line 124 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX128CNT

#define XEMACPS_TX128CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX128CNT_OFFSET)

Definition at line 121 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX1519CNT

#define XEMACPS_TX1519CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1519CNT_OFFSET)

Definition at line 125 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX256CNT

#define XEMACPS_TX256CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX256CNT_OFFSET)

Definition at line 122 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX512CNT

#define XEMACPS_TX512CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX512CNT_OFFSET)

Definition at line 123 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX64CNT

#define XEMACPS_TX64CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX64CNT_OFFSET)

Definition at line 119 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX65CNT

#define XEMACPS_TX65CNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX65CNT_OFFSET)

Definition at line 120 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_AHB_ERROR

#define XEMACPS_TX_AHB_ERROR   0x08000000

Definition at line 207 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_CHECKSUM_ERROR

#define XEMACPS_TX_CHECKSUM_ERROR   0x00700000

Definition at line 209 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_LAST

#define XEMACPS_TX_LAST   0x00008000

Definition at line 211 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_LATE_COL_ERROR

#define XEMACPS_TX_LATE_COL_ERROR   0x04000000

Definition at line 208 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_LENGTH

#define XEMACPS_TX_LENGTH   0x00003FFF

Definition at line 212 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_NO_CRC

#define XEMACPS_TX_NO_CRC   0x00010000

Definition at line 210 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_RLE_ERROR

#define XEMACPS_TX_RLE_ERROR   0x20000000

Definition at line 205 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_UNDERRUN_ERROR

#define XEMACPS_TX_UNDERRUN_ERROR   0x10000000

Definition at line 206 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_USED

#define XEMACPS_TX_USED   0x80000000

Definition at line 203 of file zynq7000_eth_driver.h.

◆ XEMACPS_TX_WRAP

#define XEMACPS_TX_WRAP   0x40000000

Definition at line 204 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXBCCNT

#define XEMACPS_TXBCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXBCCNT_OFFSET)

Definition at line 116 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXCNT

#define XEMACPS_TXCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCNT_OFFSET)

Definition at line 115 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXCSENSECNT

#define XEMACPS_TXCSENSECNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCSENSECNT_OFFSET)

Definition at line 132 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXDEFERCNT

#define XEMACPS_TXDEFERCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXDEFERCNT_OFFSET)

Definition at line 131 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXMCCNT

#define XEMACPS_TXMCCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXMCCNT_OFFSET)

Definition at line 117 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXPAUSE

#define XEMACPS_TXPAUSE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSE_OFFSET)

Definition at line 96 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXPAUSECNT

#define XEMACPS_TXPAUSECNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSECNT_OFFSET)

Definition at line 118 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXQ1BASE

#define XEMACPS_TXQ1BASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQ1BASE_OFFSET)

Definition at line 172 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXQBASE

#define XEMACPS_TXQBASE   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQBASE_OFFSET)

Definition at line 88 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXSR

#define XEMACPS_TXSR   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXSR_OFFSET)

Definition at line 86 of file zynq7000_eth_driver.h.

◆ XEMACPS_TXURUNCNT

#define XEMACPS_TXURUNCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXURUNCNT_OFFSET)

Definition at line 126 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_CLK_CTRL

#define XSLCR_GEM0_CLK_CTRL   _HW_REG(XSLCR_GEM0_CLK_CTRL_ADDR)

Definition at line 81 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_CLK_CTRL_CLKACT_MASK

#define XSLCR_GEM0_CLK_CTRL_CLKACT_MASK   0x00000001

Definition at line 194 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_CLK_CTRL_DIV0_MASK

#define XSLCR_GEM0_CLK_CTRL_DIV0_MASK   0x00003F00

Definition at line 192 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_CLK_CTRL_DIV1_MASK

#define XSLCR_GEM0_CLK_CTRL_DIV1_MASK   0x03F00000

Definition at line 191 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_CLK_CTRL_SRCSEL_MASK

#define XSLCR_GEM0_CLK_CTRL_SRCSEL_MASK   0x00000070

Definition at line 193 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_RCLK_CTRL

#define XSLCR_GEM0_RCLK_CTRL   _HW_REG(XSLCR_GEM0_RCLK_CTRL_ADDR)

Definition at line 80 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK

#define XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK   0x00000001

Definition at line 188 of file zynq7000_eth_driver.h.

◆ XSLCR_GEM0_RCLK_CTRL_SRCSEL_MASK

#define XSLCR_GEM0_RCLK_CTRL_SRCSEL_MASK   0x00000010

Definition at line 187 of file zynq7000_eth_driver.h.

◆ XSLCR_LOCK

#define XSLCR_LOCK   _HW_REG(XSLCR_UNLOCK_ADDR - 4)

Definition at line 78 of file zynq7000_eth_driver.h.

◆ XSLCR_LOCK_KEY_VALUE

#define XSLCR_LOCK_KEY_VALUE   0x0000767B;

Definition at line 181 of file zynq7000_eth_driver.h.

◆ XSLCR_UNLOCK

#define XSLCR_UNLOCK   _HW_REG(XSLCR_UNLOCK_ADDR)

Definition at line 79 of file zynq7000_eth_driver.h.

◆ XSLCR_UNLOCK_KEY_VALUE

#define XSLCR_UNLOCK_KEY_VALUE   0x0000DF0D;

Definition at line 184 of file zynq7000_eth_driver.h.

◆ ZYNQ7000_ETH_IRQ_PRIORITY

#define ZYNQ7000_ETH_IRQ_PRIORITY   160

Definition at line 64 of file zynq7000_eth_driver.h.

◆ ZYNQ7000_ETH_RAM_SECTION

#define ZYNQ7000_ETH_RAM_SECTION   ".ram_no_cache"

Definition at line 71 of file zynq7000_eth_driver.h.

◆ ZYNQ7000_ETH_RX_BUFFER_COUNT

#define ZYNQ7000_ETH_RX_BUFFER_COUNT   16

Definition at line 50 of file zynq7000_eth_driver.h.

◆ ZYNQ7000_ETH_RX_BUFFER_SIZE

#define ZYNQ7000_ETH_RX_BUFFER_SIZE   1536

Definition at line 57 of file zynq7000_eth_driver.h.

◆ ZYNQ7000_ETH_TX_BUFFER_COUNT

#define ZYNQ7000_ETH_TX_BUFFER_COUNT   16

Definition at line 36 of file zynq7000_eth_driver.h.

◆ ZYNQ7000_ETH_TX_BUFFER_SIZE

#define ZYNQ7000_ETH_TX_BUFFER_SIZE   1536

Definition at line 43 of file zynq7000_eth_driver.h.

Function Documentation

◆ zynq7000EthDisableIrq()

void zynq7000EthDisableIrq ( NetInterface *  interface)

Disable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 358 of file zynq7000_eth_driver.c.

◆ zynq7000EthEnableIrq()

void zynq7000EthEnableIrq ( NetInterface *  interface)

Enable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 330 of file zynq7000_eth_driver.c.

◆ zynq7000EthEventHandler()

void zynq7000EthEventHandler ( NetInterface *  interface)

Zynq-7000 Ethernet MAC event handler.

Parameters
[in]interfaceUnderlying network interface

Definition at line 449 of file zynq7000_eth_driver.c.

◆ zynq7000EthInit()

error_t zynq7000EthInit ( NetInterface *  interface)

Zynq-7000 Ethernet MAC initialization.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 124 of file zynq7000_eth_driver.c.

◆ zynq7000EthInitBufferDesc()

void zynq7000EthInitBufferDesc ( NetInterface *  interface)

Initialize buffer descriptors.

Parameters
[in]interfaceUnderlying network interface

Definition at line 252 of file zynq7000_eth_driver.c.

◆ zynq7000EthIrqHandler()

void zynq7000EthIrqHandler ( NetInterface *  interface)

Zynq-7000 Ethernet MAC interrupt service routine.

Parameters
[in]interfaceUnderlying network interface

Definition at line 386 of file zynq7000_eth_driver.c.

◆ zynq7000EthReadPhyReg()

uint16_t zynq7000EthReadPhyReg ( uint8_t  opcode,
uint8_t  phyAddr,
uint8_t  regAddr 
)

Read PHY register.

Parameters
[in]opcodeAccess type (2 bits)
[in]phyAddrPHY address (5 bits)
[in]regAddrRegister address (5 bits)
Returns
Register value

Definition at line 871 of file zynq7000_eth_driver.c.

◆ zynq7000EthReceivePacket()

error_t zynq7000EthReceivePacket ( NetInterface *  interface)

Receive a packet.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 554 of file zynq7000_eth_driver.c.

◆ zynq7000EthSendPacket()

error_t zynq7000EthSendPacket ( NetInterface *  interface,
const NetBuffer *  buffer,
size_t  offset,
NetTxAncillary *  ancillary 
)

Send a packet.

Parameters
[in]interfaceUnderlying network interface
[in]bufferMulti-part buffer containing the data to send
[in]offsetOffset to the first data byte
[in]ancillaryAdditional options passed to the stack along with the packet
Returns
Error code

Definition at line 485 of file zynq7000_eth_driver.c.

◆ zynq7000EthTick()

void zynq7000EthTick ( NetInterface *  interface)

Zynq-7000 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters
[in]interfaceUnderlying network interface

Definition at line 305 of file zynq7000_eth_driver.c.

◆ zynq7000EthUpdateMacAddrFilter()

error_t zynq7000EthUpdateMacAddrFilter ( NetInterface *  interface)

Configure MAC address filtering.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 686 of file zynq7000_eth_driver.c.

◆ zynq7000EthUpdateMacConfig()

error_t zynq7000EthUpdateMacConfig ( NetInterface *  interface)

Adjust MAC configuration parameters for proper operation.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 753 of file zynq7000_eth_driver.c.

◆ zynq7000EthWritePhyReg()

void zynq7000EthWritePhyReg ( uint8_t  opcode,
uint8_t  phyAddr,
uint8_t  regAddr,
uint16_t  data 
)

Write PHY register.

Parameters
[in]opcodeAccess type (2 bits)
[in]phyAddrPHY address (5 bits)
[in]regAddrRegister address (5 bits)
[in]dataRegister value

Definition at line 832 of file zynq7000_eth_driver.c.

Variable Documentation

◆ zynq7000EthDriver

const NicDriver zynq7000EthDriver
extern

Zynq-7000 Ethernet MAC driver.

Definition at line 97 of file zynq7000_eth_driver.c.