zynq7000_eth_driver.h
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1 /**
2  * @file zynq7000_eth_driver.h
3  * @brief Zynq-7000 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _ZYNQ7000_ETH_DRIVER_H
30 #define _ZYNQ7000_ETH_DRIVER_H
31 
32 //Number of TX buffers
33 #ifndef ZYNQ7000_ETH_TX_BUFFER_COUNT
34  #define ZYNQ7000_ETH_TX_BUFFER_COUNT 16
35 #elif (ZYNQ7000_ETH_TX_BUFFER_COUNT < 1)
36  #error ZYNQ7000_ETH_TX_BUFFER_COUNT parameter is not valid
37 #endif
38 
39 //TX buffer size
40 #ifndef ZYNQ7000_ETH_TX_BUFFER_SIZE
41  #define ZYNQ7000_ETH_TX_BUFFER_SIZE 1536
42 #elif (ZYNQ7000_ETH_TX_BUFFER_SIZE != 1536)
43  #error ZYNQ7000_ETH_TX_BUFFER_SIZE parameter is not valid
44 #endif
45 
46 //Number of RX buffers
47 #ifndef ZYNQ7000_ETH_RX_BUFFER_COUNT
48  #define ZYNQ7000_ETH_RX_BUFFER_COUNT 16
49 #elif (ZYNQ7000_ETH_RX_BUFFER_COUNT < 1)
50  #error ZYNQ7000_ETH_RX_BUFFER_COUNT parameter is not valid
51 #endif
52 
53 //RX buffer size
54 #ifndef ZYNQ7000_ETH_RX_BUFFER_SIZE
55  #define ZYNQ7000_ETH_RX_BUFFER_SIZE 1536
56 #elif (ZYNQ7000_ETH_RX_BUFFER_SIZE != 1536)
57  #error ZYNQ7000_ETH_RX_BUFFER_SIZE parameter is not valid
58 #endif
59 
60 //Ethernet interrupt priority
61 #ifndef ZYNQ7000_ETH_IRQ_PRIORITY
62  #define ZYNQ7000_ETH_IRQ_PRIORITY 160
63 #elif (ZYNQ7000_ETH_IRQ_PRIORITY < 0)
64  #error ZYNQ7000_ETH_IRQ_PRIORITY parameter is not valid
65 #endif
66 
67 //Macro for hardware access
68 #define _HW_REG(address) *((volatile uint32_t *) (address))
69 
70 //XEMACPS registers
71 #define XSLCR_LOCK _HW_REG(XSLCR_UNLOCK_ADDR - 4)
72 #define XSLCR_UNLOCK _HW_REG(XSLCR_UNLOCK_ADDR)
73 #define XSLCR_GEM0_RCLK_CTRL _HW_REG(XSLCR_GEM0_RCLK_CTRL_ADDR)
74 #define XSLCR_GEM0_CLK_CTRL _HW_REG(XSLCR_GEM0_CLK_CTRL_ADDR)
75 #define XEMACPS_NWCTRL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCTRL_OFFSET)
76 #define XEMACPS_NWCFG _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCFG_OFFSET)
77 #define XEMACPS_NWSR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWSR_OFFSET)
78 #define XEMACPS_DMACR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_DMACR_OFFSET)
79 #define XEMACPS_TXSR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXSR_OFFSET)
80 #define XEMACPS_RXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQBASE_OFFSET)
81 #define XEMACPS_TXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQBASE_OFFSET)
82 #define XEMACPS_RXSR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSR_OFFSET)
83 #define XEMACPS_ISR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_ISR_OFFSET)
84 #define XEMACPS_IER _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IER_OFFSET)
85 #define XEMACPS_IDR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IDR_OFFSET)
86 #define XEMACPS_IMR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IMR_OFFSET)
87 #define XEMACPS_PHYMNTNC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PHYMNTNC_OFFSET)
88 #define XEMACPS_RXPAUSE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSE_OFFSET)
89 #define XEMACPS_TXPAUSE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSE_OFFSET)
90 #define XEMACPS_JUMBOMAXLEN _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_JUMBOMAXLEN_OFFSET)
91 #define XEMACPS_HASHL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHL_OFFSET)
92 #define XEMACPS_HASHH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHH_OFFSET)
93 #define XEMACPS_LADDR1L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1L_OFFSET)
94 #define XEMACPS_LADDR1H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1H_OFFSET)
95 #define XEMACPS_LADDR2L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2L_OFFSET)
96 #define XEMACPS_LADDR2H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2H_OFFSET)
97 #define XEMACPS_LADDR3L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3L_OFFSET)
98 #define XEMACPS_LADDR3H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3H_OFFSET)
99 #define XEMACPS_LADDR4L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4L_OFFSET)
100 #define XEMACPS_LADDR4H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4H_OFFSET)
101 #define XEMACPS_MATCH1 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH1_OFFSET)
102 #define XEMACPS_MATCH2 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH2_OFFSET)
103 #define XEMACPS_MATCH3 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH3_OFFSET)
104 #define XEMACPS_MATCH4 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH4_OFFSET)
105 #define XEMACPS_STRETCH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_STRETCH_OFFSET)
106 #define XEMACPS_OCTTXL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXL_OFFSET)
107 #define XEMACPS_OCTTXH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXH_OFFSET)
108 #define XEMACPS_TXCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCNT_OFFSET)
109 #define XEMACPS_TXBCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXBCCNT_OFFSET)
110 #define XEMACPS_TXMCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXMCCNT_OFFSET)
111 #define XEMACPS_TXPAUSECNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSECNT_OFFSET)
112 #define XEMACPS_TX64CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX64CNT_OFFSET)
113 #define XEMACPS_TX65CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX65CNT_OFFSET)
114 #define XEMACPS_TX128CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX128CNT_OFFSET)
115 #define XEMACPS_TX256CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX256CNT_OFFSET)
116 #define XEMACPS_TX512CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX512CNT_OFFSET)
117 #define XEMACPS_TX1024CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1024CNT_OFFSET)
118 #define XEMACPS_TX1519CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1519CNT_OFFSET)
119 #define XEMACPS_TXURUNCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXURUNCNT_OFFSET)
120 #define XEMACPS_SNGLCOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_SNGLCOLLCNT_OFFSET)
121 #define XEMACPS_MULTICOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MULTICOLLCNT_OFFSET)
122 #define XEMACPS_EXCESSCOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_EXCESSCOLLCNT_OFFSET)
123 #define XEMACPS_LATECOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LATECOLLCNT_OFFSET)
124 #define XEMACPS_TXDEFERCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXDEFERCNT_OFFSET)
125 #define XEMACPS_TXCSENSECNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCSENSECNT_OFFSET)
126 #define XEMACPS_OCTRXL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXL_OFFSET)
127 #define XEMACPS_OCTRXH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXH_OFFSET)
128 #define XEMACPS_RXCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXCNT_OFFSET)
129 #define XEMACPS_RXBROADCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXBROADCNT_OFFSET)
130 #define XEMACPS_RXMULTICNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXMULTICNT_OFFSET)
131 #define XEMACPS_RXPAUSECNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSECNT_OFFSET)
132 #define XEMACPS_RX64CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX64CNT_OFFSET)
133 #define XEMACPS_RX65CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX65CNT_OFFSET)
134 #define XEMACPS_RX128CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX128CNT_OFFSET)
135 #define XEMACPS_RX256CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX256CNT_OFFSET)
136 #define XEMACPS_RX512CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX512CNT_OFFSET)
137 #define XEMACPS_RX1024CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1024CNT_OFFSET)
138 #define XEMACPS_RX1519CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1519CNT_OFFSET)
139 #define XEMACPS_RXUNDRCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUNDRCNT_OFFSET)
140 #define XEMACPS_RXOVRCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXOVRCNT_OFFSET)
141 #define XEMACPS_RXJABCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXJABCNT_OFFSET)
142 #define XEMACPS_RXFCSCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXFCSCNT_OFFSET)
143 #define XEMACPS_RXLENGTHCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXLENGTHCNT_OFFSET)
144 #define XEMACPS_RXSYMBCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSYMBCNT_OFFSET)
145 #define XEMACPS_RXALIGNCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXALIGNCNT_OFFSET)
146 #define XEMACPS_RXRESERRCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXRESERRCNT_OFFSET)
147 #define XEMACPS_RXORCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXORCNT_OFFSET)
148 #define XEMACPS_RXIPCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXIPCCNT_OFFSET)
149 #define XEMACPS_RXTCPCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXTCPCCNT_OFFSET)
150 #define XEMACPS_RXUDPCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUDPCCNT_OFFSET)
151 #define XEMACPS_LAST _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LAST_OFFSET)
152 #define XEMACPS_1588_SEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_SEC_OFFSET)
153 #define XEMACPS_1588_NANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_NANOSEC_OFFSET)
154 #define XEMACPS_1588_ADJ _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_ADJ_OFFSET)
155 #define XEMACPS_1588_INC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_INC_OFFSET)
156 #define XEMACPS_PTP_TXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXSEC_OFFSET)
157 #define XEMACPS_PTP_TXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXNANOSEC_OFFSET)
158 #define XEMACPS_PTP_RXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXSEC_OFFSET)
159 #define XEMACPS_PTP_RXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXNANOSEC_OFFSET)
160 #define XEMACPS_PTPP_TXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXSEC_OFFSET)
161 #define XEMACPS_PTPP_TXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXNANOSEC_OFFSET)
162 #define XEMACPS_PTPP_RXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXSEC_OFFSET)
163 #define XEMACPS_PTPP_RXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXNANOSEC_OFFSET)
164 #define XEMACPS_INTQ1_STS _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_STS_OFFSET)
165 #define XEMACPS_TXQ1BASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQ1BASE_OFFSET)
166 #define XEMACPS_RXQ1BASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQ1BASE_OFFSET)
167 #define XEMACPS_MSBBUF_TXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_TXQBASE_OFFSET)
168 #define XEMACPS_MSBBUF_RXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_RXQBASE_OFFSET)
169 #define XEMACPS_INTQ1_IER _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IER_OFFSET)
170 #define XEMACPS_INTQ1_IDR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IDR_OFFSET)
171 #define XEMACPS_INTQ1_IMR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IMR_OFFSET)
172 
173 //SLCR_LOCK register
174 #define XSLCR_LOCK_KEY_VALUE 0x0000767B;
175 
176 //SLCR_UNLOCK register
177 #define XSLCR_UNLOCK_KEY_VALUE 0x0000DF0D;
178 
179 //SLCR_GEM0_RCLK_CTRL register
180 #define XSLCR_GEM0_RCLK_CTRL_SRCSEL_MASK 0x00000010
181 #define XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK 0x00000001
182 
183 //SLCR_GEM0_CLK_CTRL register
184 #define XSLCR_GEM0_CLK_CTRL_DIV1_MASK 0x03F00000
185 #define XSLCR_GEM0_CLK_CTRL_DIV0_MASK 0x00003F00
186 #define XSLCR_GEM0_CLK_CTRL_SRCSEL_MASK 0x00000070
187 #define XSLCR_GEM0_CLK_CTRL_CLKACT_MASK 0x00000001
188 
189 //PHYMNTNC register
190 #ifdef XEMACPS_PHYMNTNC_DATA_MASK
191  #undef XEMACPS_PHYMNTNC_DATA_MASK
192  #define XEMACPS_PHYMNTNC_DATA_MASK 0x0000FFFF
193 #endif
194 
195 //TX buffer descriptor flags
196 #define XEMACPS_TX_USED 0x80000000
197 #define XEMACPS_TX_WRAP 0x40000000
198 #define XEMACPS_TX_RLE_ERROR 0x20000000
199 #define XEMACPS_TX_UNDERRUN_ERROR 0x10000000
200 #define XEMACPS_TX_AHB_ERROR 0x08000000
201 #define XEMACPS_TX_LATE_COL_ERROR 0x04000000
202 #define XEMACPS_TX_CHECKSUM_ERROR 0x00700000
203 #define XEMACPS_TX_NO_CRC 0x00010000
204 #define XEMACPS_TX_LAST 0x00008000
205 #define XEMACPS_TX_LENGTH 0x00003FFF
206 
207 //RX buffer descriptor flags
208 #define XEMACPS_RX_ADDRESS 0xFFFFFFFC
209 #define XEMACPS_RX_WRAP 0x00000002
210 #define XEMACPS_RX_OWNERSHIP 0x00000001
211 #define XEMACPS_RX_BROADCAST 0x80000000
212 #define XEMACPS_RX_MULTICAST_HASH 0x40000000
213 #define XEMACPS_RX_UNICAST_HASH 0x20000000
214 #define XEMACPS_RX_SAR 0x08000000
215 #define XEMACPS_RX_SAR_MASK 0x06000000
216 #define XEMACPS_RX_TYPE_ID 0x01000000
217 #define XEMACPS_RX_SNAP 0x01000000
218 #define XEMACPS_RX_TYPE_ID_MASK 0x00C00000
219 #define XEMACPS_RX_CHECKSUM_VALID 0x00C00000
220 #define XEMACPS_RX_VLAN_TAG 0x00200000
221 #define XEMACPS_RX_PRIORITY_TAG 0x00100000
222 #define XEMACPS_RX_VLAN_PRIORITY 0x000E0000
223 #define XEMACPS_RX_CFI 0x00010000
224 #define XEMACPS_RX_EOF 0x00008000
225 #define XEMACPS_RX_SOF 0x00004000
226 #define XEMACPS_RX_LENGTH_MSB 0x00002000
227 #define XEMACPS_RX_BAD_FCS 0x00002000
228 #define XEMACPS_RX_LENGTH 0x00001FFF
229 
230 //C++ guard
231 #ifdef __cplusplus
232  extern "C" {
233 #endif
234 
235 
236 /**
237  * @brief Transmit buffer descriptor
238  **/
239 
240 typedef struct
241 {
242  uint32_t address;
243  uint32_t status;
245 
246 
247 /**
248  * @brief Receive buffer descriptor
249  **/
250 
251 typedef struct
252 {
253  uint32_t address;
254  uint32_t status;
256 
257 
258 //Zynq-7000 Ethernet MAC driver
259 extern const NicDriver zynq7000EthDriver;
260 
261 //Zynq-7000 Ethernet MAC related functions
263 void zynq7000EthInitBufferDesc(NetInterface *interface);
264 
265 void zynq7000EthTick(NetInterface *interface);
266 
267 void zynq7000EthEnableIrq(NetInterface *interface);
268 void zynq7000EthDisableIrq(NetInterface *interface);
269 void zynq7000EthIrqHandler(NetInterface *interface);
270 void zynq7000EthEventHandler(NetInterface *interface);
271 
273  const NetBuffer *buffer, size_t offset);
274 
276 
279 
280 void zynq7000EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
281 uint16_t zynq7000EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
282 
283 //C++ guard
284 #ifdef __cplusplus
285  }
286 #endif
287 
288 #endif
void zynq7000EthEventHandler(NetInterface *interface)
Zynq-7000 Ethernet MAC event handler.
void zynq7000EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t zynq7000EthInit(NetInterface *interface)
Zynq-7000 Ethernet MAC initialization.
void zynq7000EthIrqHandler(NetInterface *interface)
Zynq-7000 Ethernet MAC interrupt service routine.
void zynq7000EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t zynq7000EthReceivePacket(NetInterface *interface)
Receive a packet.
void zynq7000EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
const NicDriver zynq7000EthDriver
Zynq-7000 Ethernet MAC driver.
void zynq7000EthDisableIrq(NetInterface *interface)
Disable interrupts.
NIC driver.
Definition: nic.h:161
error_t zynq7000EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
uint16_t regAddr
uint16_t zynq7000EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void zynq7000EthTick(NetInterface *interface)
Zynq-7000 Ethernet MAC timer handler.
error_t zynq7000EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t
Error codes.
Definition: error.h:40
Transmit buffer descriptor.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t zynq7000EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive buffer descriptor.