zynq7000_eth_driver.h
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1 /**
2  * @file zynq7000_eth_driver.h
3  * @brief Zynq-7000 Gigabit Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _ZYNQ7000_ETH_DRIVER_H
32 #define _ZYNQ7000_ETH_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef ZYNQ7000_ETH_TX_BUFFER_COUNT
36  #define ZYNQ7000_ETH_TX_BUFFER_COUNT 16
37 #elif (ZYNQ7000_ETH_TX_BUFFER_COUNT < 1)
38  #error ZYNQ7000_ETH_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef ZYNQ7000_ETH_TX_BUFFER_SIZE
43  #define ZYNQ7000_ETH_TX_BUFFER_SIZE 1536
44 #elif (ZYNQ7000_ETH_TX_BUFFER_SIZE != 1536)
45  #error ZYNQ7000_ETH_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef ZYNQ7000_ETH_RX_BUFFER_COUNT
50  #define ZYNQ7000_ETH_RX_BUFFER_COUNT 16
51 #elif (ZYNQ7000_ETH_RX_BUFFER_COUNT < 1)
52  #error ZYNQ7000_ETH_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef ZYNQ7000_ETH_RX_BUFFER_SIZE
57  #define ZYNQ7000_ETH_RX_BUFFER_SIZE 1536
58 #elif (ZYNQ7000_ETH_RX_BUFFER_SIZE != 1536)
59  #error ZYNQ7000_ETH_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Ethernet interrupt priority
63 #ifndef ZYNQ7000_ETH_IRQ_PRIORITY
64  #define ZYNQ7000_ETH_IRQ_PRIORITY 160
65 #elif (ZYNQ7000_ETH_IRQ_PRIORITY < 0)
66  #error ZYNQ7000_ETH_IRQ_PRIORITY parameter is not valid
67 #endif
68 
69 //Name of the section where to place DMA buffers
70 #ifndef ZYNQ7000_ETH_RAM_SECTION
71  #define ZYNQ7000_ETH_RAM_SECTION ".ram_no_cache"
72 #endif
73 
74 //Macro for hardware access
75 #define _HW_REG(address) *((volatile uint32_t *) (address))
76 
77 //XEMACPS registers
78 #define XSLCR_LOCK _HW_REG(XSLCR_UNLOCK_ADDR - 4)
79 #define XSLCR_UNLOCK _HW_REG(XSLCR_UNLOCK_ADDR)
80 #define XSLCR_GEM0_RCLK_CTRL _HW_REG(XSLCR_GEM0_RCLK_CTRL_ADDR)
81 #define XSLCR_GEM0_CLK_CTRL _HW_REG(XSLCR_GEM0_CLK_CTRL_ADDR)
82 #define XEMACPS_NWCTRL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCTRL_OFFSET)
83 #define XEMACPS_NWCFG _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCFG_OFFSET)
84 #define XEMACPS_NWSR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWSR_OFFSET)
85 #define XEMACPS_DMACR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_DMACR_OFFSET)
86 #define XEMACPS_TXSR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXSR_OFFSET)
87 #define XEMACPS_RXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQBASE_OFFSET)
88 #define XEMACPS_TXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQBASE_OFFSET)
89 #define XEMACPS_RXSR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSR_OFFSET)
90 #define XEMACPS_ISR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_ISR_OFFSET)
91 #define XEMACPS_IER _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IER_OFFSET)
92 #define XEMACPS_IDR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IDR_OFFSET)
93 #define XEMACPS_IMR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IMR_OFFSET)
94 #define XEMACPS_PHYMNTNC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PHYMNTNC_OFFSET)
95 #define XEMACPS_RXPAUSE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSE_OFFSET)
96 #define XEMACPS_TXPAUSE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSE_OFFSET)
97 #define XEMACPS_JUMBOMAXLEN _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_JUMBOMAXLEN_OFFSET)
98 #define XEMACPS_HASHL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHL_OFFSET)
99 #define XEMACPS_HASHH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHH_OFFSET)
100 #define XEMACPS_LADDR1L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1L_OFFSET)
101 #define XEMACPS_LADDR1H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1H_OFFSET)
102 #define XEMACPS_LADDR2L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2L_OFFSET)
103 #define XEMACPS_LADDR2H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2H_OFFSET)
104 #define XEMACPS_LADDR3L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3L_OFFSET)
105 #define XEMACPS_LADDR3H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3H_OFFSET)
106 #define XEMACPS_LADDR4L _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4L_OFFSET)
107 #define XEMACPS_LADDR4H _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4H_OFFSET)
108 #define XEMACPS_MATCH1 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH1_OFFSET)
109 #define XEMACPS_MATCH2 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH2_OFFSET)
110 #define XEMACPS_MATCH3 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH3_OFFSET)
111 #define XEMACPS_MATCH4 _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH4_OFFSET)
112 #define XEMACPS_STRETCH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_STRETCH_OFFSET)
113 #define XEMACPS_OCTTXL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXL_OFFSET)
114 #define XEMACPS_OCTTXH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXH_OFFSET)
115 #define XEMACPS_TXCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCNT_OFFSET)
116 #define XEMACPS_TXBCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXBCCNT_OFFSET)
117 #define XEMACPS_TXMCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXMCCNT_OFFSET)
118 #define XEMACPS_TXPAUSECNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSECNT_OFFSET)
119 #define XEMACPS_TX64CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX64CNT_OFFSET)
120 #define XEMACPS_TX65CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX65CNT_OFFSET)
121 #define XEMACPS_TX128CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX128CNT_OFFSET)
122 #define XEMACPS_TX256CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX256CNT_OFFSET)
123 #define XEMACPS_TX512CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX512CNT_OFFSET)
124 #define XEMACPS_TX1024CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1024CNT_OFFSET)
125 #define XEMACPS_TX1519CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1519CNT_OFFSET)
126 #define XEMACPS_TXURUNCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXURUNCNT_OFFSET)
127 #define XEMACPS_SNGLCOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_SNGLCOLLCNT_OFFSET)
128 #define XEMACPS_MULTICOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MULTICOLLCNT_OFFSET)
129 #define XEMACPS_EXCESSCOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_EXCESSCOLLCNT_OFFSET)
130 #define XEMACPS_LATECOLLCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LATECOLLCNT_OFFSET)
131 #define XEMACPS_TXDEFERCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXDEFERCNT_OFFSET)
132 #define XEMACPS_TXCSENSECNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCSENSECNT_OFFSET)
133 #define XEMACPS_OCTRXL _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXL_OFFSET)
134 #define XEMACPS_OCTRXH _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXH_OFFSET)
135 #define XEMACPS_RXCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXCNT_OFFSET)
136 #define XEMACPS_RXBROADCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXBROADCNT_OFFSET)
137 #define XEMACPS_RXMULTICNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXMULTICNT_OFFSET)
138 #define XEMACPS_RXPAUSECNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSECNT_OFFSET)
139 #define XEMACPS_RX64CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX64CNT_OFFSET)
140 #define XEMACPS_RX65CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX65CNT_OFFSET)
141 #define XEMACPS_RX128CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX128CNT_OFFSET)
142 #define XEMACPS_RX256CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX256CNT_OFFSET)
143 #define XEMACPS_RX512CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX512CNT_OFFSET)
144 #define XEMACPS_RX1024CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1024CNT_OFFSET)
145 #define XEMACPS_RX1519CNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1519CNT_OFFSET)
146 #define XEMACPS_RXUNDRCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUNDRCNT_OFFSET)
147 #define XEMACPS_RXOVRCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXOVRCNT_OFFSET)
148 #define XEMACPS_RXJABCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXJABCNT_OFFSET)
149 #define XEMACPS_RXFCSCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXFCSCNT_OFFSET)
150 #define XEMACPS_RXLENGTHCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXLENGTHCNT_OFFSET)
151 #define XEMACPS_RXSYMBCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSYMBCNT_OFFSET)
152 #define XEMACPS_RXALIGNCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXALIGNCNT_OFFSET)
153 #define XEMACPS_RXRESERRCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXRESERRCNT_OFFSET)
154 #define XEMACPS_RXORCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXORCNT_OFFSET)
155 #define XEMACPS_RXIPCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXIPCCNT_OFFSET)
156 #define XEMACPS_RXTCPCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXTCPCCNT_OFFSET)
157 #define XEMACPS_RXUDPCCNT _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUDPCCNT_OFFSET)
158 #define XEMACPS_LAST _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LAST_OFFSET)
159 #define XEMACPS_1588_SEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_SEC_OFFSET)
160 #define XEMACPS_1588_NANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_NANOSEC_OFFSET)
161 #define XEMACPS_1588_ADJ _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_ADJ_OFFSET)
162 #define XEMACPS_1588_INC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_INC_OFFSET)
163 #define XEMACPS_PTP_TXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXSEC_OFFSET)
164 #define XEMACPS_PTP_TXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXNANOSEC_OFFSET)
165 #define XEMACPS_PTP_RXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXSEC_OFFSET)
166 #define XEMACPS_PTP_RXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXNANOSEC_OFFSET)
167 #define XEMACPS_PTPP_TXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXSEC_OFFSET)
168 #define XEMACPS_PTPP_TXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXNANOSEC_OFFSET)
169 #define XEMACPS_PTPP_RXSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXSEC_OFFSET)
170 #define XEMACPS_PTPP_RXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXNANOSEC_OFFSET)
171 #define XEMACPS_INTQ1_STS _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_STS_OFFSET)
172 #define XEMACPS_TXQ1BASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQ1BASE_OFFSET)
173 #define XEMACPS_RXQ1BASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQ1BASE_OFFSET)
174 #define XEMACPS_MSBBUF_TXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_TXQBASE_OFFSET)
175 #define XEMACPS_MSBBUF_RXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_RXQBASE_OFFSET)
176 #define XEMACPS_INTQ1_IER _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IER_OFFSET)
177 #define XEMACPS_INTQ1_IDR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IDR_OFFSET)
178 #define XEMACPS_INTQ1_IMR _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IMR_OFFSET)
179 
180 //SLCR_LOCK register
181 #define XSLCR_LOCK_KEY_VALUE 0x0000767B;
182 
183 //SLCR_UNLOCK register
184 #define XSLCR_UNLOCK_KEY_VALUE 0x0000DF0D;
185 
186 //SLCR_GEM0_RCLK_CTRL register
187 #define XSLCR_GEM0_RCLK_CTRL_SRCSEL_MASK 0x00000010
188 #define XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK 0x00000001
189 
190 //SLCR_GEM0_CLK_CTRL register
191 #define XSLCR_GEM0_CLK_CTRL_DIV1_MASK 0x03F00000
192 #define XSLCR_GEM0_CLK_CTRL_DIV0_MASK 0x00003F00
193 #define XSLCR_GEM0_CLK_CTRL_SRCSEL_MASK 0x00000070
194 #define XSLCR_GEM0_CLK_CTRL_CLKACT_MASK 0x00000001
195 
196 //PHYMNTNC register
197 #ifdef XEMACPS_PHYMNTNC_DATA_MASK
198  #undef XEMACPS_PHYMNTNC_DATA_MASK
199  #define XEMACPS_PHYMNTNC_DATA_MASK 0x0000FFFF
200 #endif
201 
202 //TX buffer descriptor flags
203 #define XEMACPS_TX_USED 0x80000000
204 #define XEMACPS_TX_WRAP 0x40000000
205 #define XEMACPS_TX_RLE_ERROR 0x20000000
206 #define XEMACPS_TX_UNDERRUN_ERROR 0x10000000
207 #define XEMACPS_TX_AHB_ERROR 0x08000000
208 #define XEMACPS_TX_LATE_COL_ERROR 0x04000000
209 #define XEMACPS_TX_CHECKSUM_ERROR 0x00700000
210 #define XEMACPS_TX_NO_CRC 0x00010000
211 #define XEMACPS_TX_LAST 0x00008000
212 #define XEMACPS_TX_LENGTH 0x00003FFF
213 
214 //RX buffer descriptor flags
215 #define XEMACPS_RX_ADDRESS 0xFFFFFFFC
216 #define XEMACPS_RX_WRAP 0x00000002
217 #define XEMACPS_RX_OWNERSHIP 0x00000001
218 #define XEMACPS_RX_BROADCAST 0x80000000
219 #define XEMACPS_RX_MULTICAST_HASH 0x40000000
220 #define XEMACPS_RX_UNICAST_HASH 0x20000000
221 #define XEMACPS_RX_SAR 0x08000000
222 #define XEMACPS_RX_SAR_MASK 0x06000000
223 #define XEMACPS_RX_TYPE_ID 0x01000000
224 #define XEMACPS_RX_SNAP 0x01000000
225 #define XEMACPS_RX_TYPE_ID_MASK 0x00C00000
226 #define XEMACPS_RX_CHECKSUM_VALID 0x00C00000
227 #define XEMACPS_RX_VLAN_TAG 0x00200000
228 #define XEMACPS_RX_PRIORITY_TAG 0x00100000
229 #define XEMACPS_RX_VLAN_PRIORITY 0x000E0000
230 #define XEMACPS_RX_CFI 0x00010000
231 #define XEMACPS_RX_EOF 0x00008000
232 #define XEMACPS_RX_SOF 0x00004000
233 #define XEMACPS_RX_LENGTH_MSB 0x00002000
234 #define XEMACPS_RX_BAD_FCS 0x00002000
235 #define XEMACPS_RX_LENGTH 0x00001FFF
236 
237 //C++ guard
238 #ifdef __cplusplus
239 extern "C" {
240 #endif
241 
242 
243 /**
244  * @brief Transmit buffer descriptor
245  **/
246 
247 typedef struct
248 {
249  uint32_t address;
250  uint32_t status;
252 
253 
254 /**
255  * @brief Receive buffer descriptor
256  **/
257 
258 typedef struct
259 {
260  uint32_t address;
261  uint32_t status;
263 
264 
265 //Zynq-7000 Ethernet MAC driver
266 extern const NicDriver zynq7000EthDriver;
267 
268 //Zynq-7000 Ethernet MAC related functions
270 void zynq7000EthInitBufferDesc(NetInterface *interface);
271 
272 void zynq7000EthTick(NetInterface *interface);
273 
274 void zynq7000EthEnableIrq(NetInterface *interface);
275 void zynq7000EthDisableIrq(NetInterface *interface);
276 void zynq7000EthIrqHandler(NetInterface *interface);
277 void zynq7000EthEventHandler(NetInterface *interface);
278 
280  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
281 
283 
286 
287 void zynq7000EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
288  uint8_t regAddr, uint16_t data);
289 
290 uint16_t zynq7000EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
291  uint8_t regAddr);
292 
293 //C++ guard
294 #ifdef __cplusplus
295 }
296 #endif
297 
298 #endif
void zynq7000EthEnableIrq(NetInterface *interface)
Enable interrupts.
void zynq7000EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t opcode
Definition: dns_common.h:172
uint8_t data[]
Definition: ethernet.h:209
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t zynq7000EthInit(NetInterface *interface)
Zynq-7000 Ethernet MAC initialization.
const NicDriver zynq7000EthDriver
Zynq-7000 Ethernet MAC driver.
error_t zynq7000EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive buffer descriptor.
uint16_t zynq7000EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Transmit buffer descriptor.
error_t
Error codes.
Definition: error.h:42
void zynq7000EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void zynq7000EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t zynq7000EthReceivePacket(NetInterface *interface)
Receive a packet.
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
error_t zynq7000EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void zynq7000EthTick(NetInterface *interface)
Zynq-7000 Ethernet MAC timer handler.
void zynq7000EthIrqHandler(NetInterface *interface)
Zynq-7000 Ethernet MAC interrupt service routine.
uint16_t regAddr
NIC driver.
Definition: nic.h:257
error_t zynq7000EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void zynq7000EthEventHandler(NetInterface *interface)
Zynq-7000 Ethernet MAC event handler.