tm4c129_eth_driver.h File Reference

Tiva TM4C129 Ethernet controller. More...

#include "core/nic.h"

Go to the source code of this file.

Data Structures

struct  Tm4c129TxDmaDesc
 Enhanced TX DMA descriptor. More...
 
struct  Tm4c129RxDmaDesc
 Enhanced RX DMA descriptor. More...
 

Macros

#define TM4C129_ETH_TX_BUFFER_COUNT   3
 
#define TM4C129_ETH_TX_BUFFER_SIZE   1536
 
#define TM4C129_ETH_RX_BUFFER_COUNT   6
 
#define TM4C129_ETH_RX_BUFFER_SIZE   1536
 
#define TM4C129_ETH_IRQ_PRIORITY_GROUPING   3
 
#define TM4C129_ETH_IRQ_PRIORITY   192
 
#define FLASH_CONF_R   HWREG(FLASH_CONF)
 
#define EMAC0_CFG_R   HWREG(EMAC0_BASE + EMAC_O_CFG)
 
#define EMAC0_FRAMEFLTR_R   HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR)
 
#define EMAC0_HASHTBLH_R   HWREG(EMAC0_BASE + EMAC_O_HASHTBLH)
 
#define EMAC0_HASHTBLL_R   HWREG(EMAC0_BASE + EMAC_O_HASHTBLL)
 
#define EMAC0_MIIADDR_R   HWREG(EMAC0_BASE + EMAC_O_MIIADDR)
 
#define EMAC0_MIIDATA_R   HWREG(EMAC0_BASE + EMAC_O_MIIDATA)
 
#define EMAC0_FLOWCTL_R   HWREG(EMAC0_BASE + EMAC_O_FLOWCTL)
 
#define EMAC0_VLANTG_R   HWREG(EMAC0_BASE + EMAC_O_VLANTG)
 
#define EMAC0_STATUS_R   HWREG(EMAC0_BASE + EMAC_O_STATUS)
 
#define EMAC0_RWUFF_R   HWREG(EMAC0_BASE + EMAC_O_RWUFF)
 
#define EMAC0_PMTCTLSTAT_R   HWREG(EMAC0_BASE + EMAC_O_PMTCTLSTAT)
 
#define EMAC0_RIS_R   HWREG(EMAC0_BASE + EMAC_O_RIS)
 
#define EMAC0_IM_R   HWREG(EMAC0_BASE + EMAC_O_IM)
 
#define EMAC0_ADDR0H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR0H)
 
#define EMAC0_ADDR0L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR0L)
 
#define EMAC0_ADDR1H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR1H)
 
#define EMAC0_ADDR1L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR1L)
 
#define EMAC0_ADDR2H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR2H)
 
#define EMAC0_ADDR2L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR2L)
 
#define EMAC0_ADDR3H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR3H)
 
#define EMAC0_ADDR3L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR3L)
 
#define EMAC0_WDOGTO_R   HWREG(EMAC0_BASE + EMAC_O_WDOGTO)
 
#define EMAC0_MMCCTRL_R   HWREG(EMAC0_BASE + EMAC_O_MMCCTRL)
 
#define EMAC0_MMCRXRIS_R   HWREG(EMAC0_BASE + EMAC_O_MMCRXRIS)
 
#define EMAC0_MMCTXRIS_R   HWREG(EMAC0_BASE + EMAC_O_MMCTXRIS)
 
#define EMAC0_MMCRXIM_R   HWREG(EMAC0_BASE + EMAC_O_MMCRXIM)
 
#define EMAC0_MMCTXIM_R   HWREG(EMAC0_BASE + EMAC_O_MMCTXIM)
 
#define EMAC0_TXCNTGB_R   HWREG(EMAC0_BASE + EMAC_O_TXCNTGB)
 
#define EMAC0_TXCNTSCOL_R   HWREG(EMAC0_BASE + EMAC_O_TXCNTSCOL)
 
#define EMAC0_TXCNTMCOL_R   HWREG(EMAC0_BASE + EMAC_O_TXCNTMCOL)
 
#define EMAC0_TXOCTCNTG_R   HWREG(EMAC0_BASE + EMAC_O_TXOCTCNTG)
 
#define EMAC0_RXCNTGB_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTGB)
 
#define EMAC0_RXCNTCRCERR_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTCRCERR)
 
#define EMAC0_RXCNTALGNERR_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTALGNERR)
 
#define EMAC0_RXCNTGUNI_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTGUNI)
 
#define EMAC0_VLNINCREP_R   HWREG(EMAC0_BASE + EMAC_O_VLNINCREP)
 
#define EMAC0_VLANHASH_R   HWREG(EMAC0_BASE + EMAC_O_VLANHASH)
 
#define EMAC0_TIMSTCTRL_R   HWREG(EMAC0_BASE + EMAC_O_TIMSTCTRL)
 
#define EMAC0_SUBSECINC_R   HWREG(EMAC0_BASE + EMAC_O_SUBSECINC)
 
#define EMAC0_TIMSEC_R   HWREG(EMAC0_BASE + EMAC_O_TIMSEC)
 
#define EMAC0_TIMNANO_R   HWREG(EMAC0_BASE + EMAC_O_TIMNANO)
 
#define EMAC0_TIMSECU_R   HWREG(EMAC0_BASE + EMAC_O_TIMSECU)
 
#define EMAC0_TIMNANOU_R   HWREG(EMAC0_BASE + EMAC_O_TIMNANOU)
 
#define EMAC0_TIMADD_R   HWREG(EMAC0_BASE + EMAC_O_TIMADD)
 
#define EMAC0_TARGSEC_R   HWREG(EMAC0_BASE + EMAC_O_TARGSEC)
 
#define EMAC0_TARGNANO_R   HWREG(EMAC0_BASE + EMAC_O_TARGNANO)
 
#define EMAC0_HWORDSEC_R   HWREG(EMAC0_BASE + EMAC_O_HWORDSEC)
 
#define EMAC0_TIMSTAT_R   HWREG(EMAC0_BASE + EMAC_O_TIMSTAT)
 
#define EMAC0_PPSCTRL_R   HWREG(EMAC0_BASE + EMAC_O_PPSCTRL)
 
#define EMAC0_PPS0INTVL_R   HWREG(EMAC0_BASE + EMAC_O_PPS0INTVL)
 
#define EMAC0_PPS0WIDTH_R   HWREG(EMAC0_BASE + EMAC_O_PPS0WIDTH)
 
#define EMAC0_DMABUSMOD_R   HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD)
 
#define EMAC0_TXPOLLD_R   HWREG(EMAC0_BASE + EMAC_O_TXPOLLD)
 
#define EMAC0_RXPOLLD_R   HWREG(EMAC0_BASE + EMAC_O_RXPOLLD)
 
#define EMAC0_RXDLADDR_R   HWREG(EMAC0_BASE + EMAC_O_RXDLADDR)
 
#define EMAC0_TXDLADDR_R   HWREG(EMAC0_BASE + EMAC_O_TXDLADDR)
 
#define EMAC0_DMARIS_R   HWREG(EMAC0_BASE + EMAC_O_DMARIS)
 
#define EMAC0_DMAOPMODE_R   HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE)
 
#define EMAC0_DMAIM_R   HWREG(EMAC0_BASE + EMAC_O_DMAIM)
 
#define EMAC0_MFBOC_R   HWREG(EMAC0_BASE + EMAC_O_MFBOC)
 
#define EMAC0_RXINTWDT_R   HWREG(EMAC0_BASE + EMAC_O_RXINTWDT)
 
#define EMAC0_HOSTXDESC_R   HWREG(EMAC0_BASE + EMAC_O_HOSTXDESC)
 
#define EMAC0_HOSRXDESC_R   HWREG(EMAC0_BASE + EMAC_O_HOSRXDESC)
 
#define EMAC0_HOSTXBA_R   HWREG(EMAC0_BASE + EMAC_O_HOSTXBA)
 
#define EMAC0_HOSRXBA_R   HWREG(EMAC0_BASE + EMAC_O_HOSRXBA)
 
#define EMAC0_PP_R   HWREG(EMAC0_BASE + EMAC_O_PP)
 
#define EMAC0_PC_R   HWREG(EMAC0_BASE + EMAC_O_PC)
 
#define EMAC0_CC_R   HWREG(EMAC0_BASE + EMAC_O_CC)
 
#define EMAC0_EPHYRIS_R   HWREG(EMAC0_BASE + EMAC_O_EPHYRIS)
 
#define EMAC0_EPHYIM_R   HWREG(EMAC0_BASE + EMAC_O_EPHYIM)
 
#define EMAC0_EPHYMISC_R   HWREG(EMAC0_BASE + EMAC_O_EPHYMISC)
 
#define EMAC_DMABUSMOD_RPBL_1   (1 << EMAC_DMABUSMOD_RPBL_S)
 
#define EMAC_DMABUSMOD_RPBL_2   (2 << EMAC_DMABUSMOD_RPBL_S)
 
#define EMAC_DMABUSMOD_RPBL_4   (4 << EMAC_DMABUSMOD_RPBL_S)
 
#define EMAC_DMABUSMOD_RPBL_8   (8 << EMAC_DMABUSMOD_RPBL_S)
 
#define EMAC_DMABUSMOD_RPBL_16   (16 << EMAC_DMABUSMOD_RPBL_S)
 
#define EMAC_DMABUSMOD_RPBL_32   (32 << EMAC_DMABUSMOD_RPBL_S)
 
#define EMAC_DMABUSMOD_PR_1_1   (0 << EMAC_DMABUSMOD_PR_S)
 
#define EMAC_DMABUSMOD_PR_2_1   (1 << EMAC_DMABUSMOD_PR_S)
 
#define EMAC_DMABUSMOD_PR_3_1   (2 << EMAC_DMABUSMOD_PR_S)
 
#define EMAC_DMABUSMOD_PR_4_1   (3 << EMAC_DMABUSMOD_PR_S)
 
#define EMAC_DMABUSMOD_PBL_1   (1 << EMAC_DMABUSMOD_PBL_S)
 
#define EMAC_DMABUSMOD_PBL_2   (2 << EMAC_DMABUSMOD_PBL_S)
 
#define EMAC_DMABUSMOD_PBL_4   (4 << EMAC_DMABUSMOD_PBL_S)
 
#define EMAC_DMABUSMOD_PBL_8   (8 << EMAC_DMABUSMOD_PBL_S)
 
#define EMAC_DMABUSMOD_PBL_16   (16 << EMAC_DMABUSMOD_PBL_S)
 
#define EMAC_DMABUSMOD_PBL_32   (32 << EMAC_DMABUSMOD_PBL_S)
 
#define EMAC_TDES0_OWN   0x80000000
 
#define EMAC_TDES0_IC   0x40000000
 
#define EMAC_TDES0_LS   0x20000000
 
#define EMAC_TDES0_FS   0x10000000
 
#define EMAC_TDES0_DC   0x08000000
 
#define EMAC_TDES0_DP   0x04000000
 
#define EMAC_TDES0_TTSE   0x02000000
 
#define EMAC_TDES0_CRCR   0x01000000
 
#define EMAC_TDES0_CIC   0x00C00000
 
#define EMAC_TDES0_TER   0x00200000
 
#define EMAC_TDES0_TCH   0x00100000
 
#define EMAC_TDES0_VLIC   0x000C0000
 
#define EMAC_TDES0_TTSS   0x00020000
 
#define EMAC_TDES0_IHE   0x00010000
 
#define EMAC_TDES0_ES   0x00008000
 
#define EMAC_TDES0_JT   0x00004000
 
#define EMAC_TDES0_FF   0x00002000
 
#define EMAC_TDES0_IPE   0x00001000
 
#define EMAC_TDES0_LCA   0x00000800
 
#define EMAC_TDES0_NC   0x00000400
 
#define EMAC_TDES0_LCO   0x00000200
 
#define EMAC_TDES0_EC   0x00000100
 
#define EMAC_TDES0_VF   0x00000080
 
#define EMAC_TDES0_CC   0x00000078
 
#define EMAC_TDES0_ED   0x00000004
 
#define EMAC_TDES0_UF   0x00000002
 
#define EMAC_TDES0_DB   0x00000001
 
#define EMAC_TDES1_SAIC   0xE0000000
 
#define EMAC_TDES1_TBS2   0x1FFF0000
 
#define EMAC_TDES1_TBS1   0x00001FFF
 
#define EMAC_TDES2_TBAP1   0xFFFFFFFF
 
#define EMAC_TDES3_TBAP2   0xFFFFFFFF
 
#define EMAC_TDES6_TTSL   0xFFFFFFFF
 
#define EMAC_TDES7_TTSH   0xFFFFFFFF
 
#define EMAC_RDES0_OWN   0x80000000
 
#define EMAC_RDES0_AFM   0x40000000
 
#define EMAC_RDES0_FL   0x3FFF0000
 
#define EMAC_RDES0_ES   0x00008000
 
#define EMAC_RDES0_DE   0x00004000
 
#define EMAC_RDES0_SAF   0x00002000
 
#define EMAC_RDES0_LE   0x00001000
 
#define EMAC_RDES0_OE   0x00000800
 
#define EMAC_RDES0_VLAN   0x00000400
 
#define EMAC_RDES0_FS   0x00000200
 
#define EMAC_RDES0_LS   0x00000100
 
#define EMAC_RDES0_TSA_GF   0x00000080
 
#define EMAC_RDES0_LCO   0x00000040
 
#define EMAC_RDES0_FT   0x00000020
 
#define EMAC_RDES0_RWT   0x00000010
 
#define EMAC_RDES0_RE   0x00000008
 
#define EMAC_RDES0_DBE   0x00000004
 
#define EMAC_RDES0_CE   0x00000002
 
#define EMAC_RDES0_ESA   0x00000001
 
#define EMAC_RDES1_DIC   0x80000000
 
#define EMAC_RDES1_RBS2   0x1FFF0000
 
#define EMAC_RDES1_RER   0x00008000
 
#define EMAC_RDES1_RCH   0x00004000
 
#define EMAC_RDES1_RBS1   0x00001FFF
 
#define EMAC_RDES2_RBAP1   0xFFFFFFFF
 
#define EMAC_RDES3_RBAP2   0xFFFFFFFF
 
#define EMAC_RDES4_TSD   0x00004000
 
#define EMAC_RDES4_PV   0x00002000
 
#define EMAC_RDES4_PFT   0x00001000
 
#define EMAC_RDES4_PMT   0x00000F00
 
#define EMAC_RDES4_IPV6PR   0x00000080
 
#define EMAC_RDES4_IPV4PR   0x00000040
 
#define EMAC_RDES4_IPCB   0x00000020
 
#define EMAC_RDES4_IPPE   0x00000010
 
#define EMAC_RDES4_IPHE   0x00000008
 
#define EMAC_RDES4_IPPT   0x00000007
 
#define EMAC_RDES6_RTSL   0xFFFFFFFF
 
#define EMAC_RDES7_RTSH   0xFFFFFFFF
 
#define tm4c129EthIrqHandler   EMAC0_Handler
 

Functions

error_t tm4c129EthInit (NetInterface *interface)
 TM4C129 Ethernet MAC initialization. More...
 
void tm4c129EthInitGpio (NetInterface *interface)
 GPIO configuration. More...
 
void tm4c129EthInitDmaDesc (NetInterface *interface)
 Initialize DMA descriptor lists. More...
 
void tm4c129EthTick (NetInterface *interface)
 TM4C129 Ethernet MAC timer handler. More...
 
void tm4c129EthEnableIrq (NetInterface *interface)
 Enable interrupts. More...
 
void tm4c129EthDisableIrq (NetInterface *interface)
 Disable interrupts. More...
 
void tm4c129EthEventHandler (NetInterface *interface)
 TM4C129 Ethernet MAC event handler. More...
 
error_t tm4c129EthSendPacket (NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
 Send a packet. More...
 
error_t tm4c129EthReceivePacket (NetInterface *interface)
 Receive a packet. More...
 
error_t tm4c129EthUpdateMacAddrFilter (NetInterface *interface)
 Configure MAC address filtering. More...
 
error_t tm4c129EthUpdateMacConfig (NetInterface *interface)
 Adjust MAC configuration parameters for proper operation. More...
 
void tm4c129EthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
 Write PHY register. More...
 
uint16_t tm4c129EthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
 Read PHY register. More...
 
void tm4c129EthDumpPhyReg (void)
 Dump PHY registers for debugging purpose. More...
 
uint32_t tm4c129EthCalcCrc (const void *data, size_t length)
 CRC calculation. More...
 

Variables

const NicDriver tm4c129EthDriver
 TM4C129 Ethernet MAC driver. More...
 

Detailed Description

Tiva TM4C129 Ethernet controller.

License

SPDX-License-Identifier: GPL-2.0-or-later

Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author
Oryx Embedded SARL (www.oryx-embedded.com)
Version
2.4.0

Definition in file tm4c129_eth_driver.h.

Macro Definition Documentation

◆ EMAC0_ADDR0H_R

#define EMAC0_ADDR0H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR0H)

Definition at line 99 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR0L_R

#define EMAC0_ADDR0L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR0L)

Definition at line 100 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR1H_R

#define EMAC0_ADDR1H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR1H)

Definition at line 101 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR1L_R

#define EMAC0_ADDR1L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR1L)

Definition at line 102 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR2H_R

#define EMAC0_ADDR2H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR2H)

Definition at line 103 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR2L_R

#define EMAC0_ADDR2L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR2L)

Definition at line 104 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR3H_R

#define EMAC0_ADDR3H_R   HWREG(EMAC0_BASE + EMAC_O_ADDR3H)

Definition at line 105 of file tm4c129_eth_driver.h.

◆ EMAC0_ADDR3L_R

#define EMAC0_ADDR3L_R   HWREG(EMAC0_BASE + EMAC_O_ADDR3L)

Definition at line 106 of file tm4c129_eth_driver.h.

◆ EMAC0_CC_R

#define EMAC0_CC_R   HWREG(EMAC0_BASE + EMAC_O_CC)

Definition at line 153 of file tm4c129_eth_driver.h.

◆ EMAC0_CFG_R

#define EMAC0_CFG_R   HWREG(EMAC0_BASE + EMAC_O_CFG)

Definition at line 86 of file tm4c129_eth_driver.h.

◆ EMAC0_DMABUSMOD_R

#define EMAC0_DMABUSMOD_R   HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD)

Definition at line 137 of file tm4c129_eth_driver.h.

◆ EMAC0_DMAIM_R

#define EMAC0_DMAIM_R   HWREG(EMAC0_BASE + EMAC_O_DMAIM)

Definition at line 144 of file tm4c129_eth_driver.h.

◆ EMAC0_DMAOPMODE_R

#define EMAC0_DMAOPMODE_R   HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE)

Definition at line 143 of file tm4c129_eth_driver.h.

◆ EMAC0_DMARIS_R

#define EMAC0_DMARIS_R   HWREG(EMAC0_BASE + EMAC_O_DMARIS)

Definition at line 142 of file tm4c129_eth_driver.h.

◆ EMAC0_EPHYIM_R

#define EMAC0_EPHYIM_R   HWREG(EMAC0_BASE + EMAC_O_EPHYIM)

Definition at line 155 of file tm4c129_eth_driver.h.

◆ EMAC0_EPHYMISC_R

#define EMAC0_EPHYMISC_R   HWREG(EMAC0_BASE + EMAC_O_EPHYMISC)

Definition at line 156 of file tm4c129_eth_driver.h.

◆ EMAC0_EPHYRIS_R

#define EMAC0_EPHYRIS_R   HWREG(EMAC0_BASE + EMAC_O_EPHYRIS)

Definition at line 154 of file tm4c129_eth_driver.h.

◆ EMAC0_FLOWCTL_R

#define EMAC0_FLOWCTL_R   HWREG(EMAC0_BASE + EMAC_O_FLOWCTL)

Definition at line 92 of file tm4c129_eth_driver.h.

◆ EMAC0_FRAMEFLTR_R

#define EMAC0_FRAMEFLTR_R   HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR)

Definition at line 87 of file tm4c129_eth_driver.h.

◆ EMAC0_HASHTBLH_R

#define EMAC0_HASHTBLH_R   HWREG(EMAC0_BASE + EMAC_O_HASHTBLH)

Definition at line 88 of file tm4c129_eth_driver.h.

◆ EMAC0_HASHTBLL_R

#define EMAC0_HASHTBLL_R   HWREG(EMAC0_BASE + EMAC_O_HASHTBLL)

Definition at line 89 of file tm4c129_eth_driver.h.

◆ EMAC0_HOSRXBA_R

#define EMAC0_HOSRXBA_R   HWREG(EMAC0_BASE + EMAC_O_HOSRXBA)

Definition at line 150 of file tm4c129_eth_driver.h.

◆ EMAC0_HOSRXDESC_R

#define EMAC0_HOSRXDESC_R   HWREG(EMAC0_BASE + EMAC_O_HOSRXDESC)

Definition at line 148 of file tm4c129_eth_driver.h.

◆ EMAC0_HOSTXBA_R

#define EMAC0_HOSTXBA_R   HWREG(EMAC0_BASE + EMAC_O_HOSTXBA)

Definition at line 149 of file tm4c129_eth_driver.h.

◆ EMAC0_HOSTXDESC_R

#define EMAC0_HOSTXDESC_R   HWREG(EMAC0_BASE + EMAC_O_HOSTXDESC)

Definition at line 147 of file tm4c129_eth_driver.h.

◆ EMAC0_HWORDSEC_R

#define EMAC0_HWORDSEC_R   HWREG(EMAC0_BASE + EMAC_O_HWORDSEC)

Definition at line 132 of file tm4c129_eth_driver.h.

◆ EMAC0_IM_R

#define EMAC0_IM_R   HWREG(EMAC0_BASE + EMAC_O_IM)

Definition at line 98 of file tm4c129_eth_driver.h.

◆ EMAC0_MFBOC_R

#define EMAC0_MFBOC_R   HWREG(EMAC0_BASE + EMAC_O_MFBOC)

Definition at line 145 of file tm4c129_eth_driver.h.

◆ EMAC0_MIIADDR_R

#define EMAC0_MIIADDR_R   HWREG(EMAC0_BASE + EMAC_O_MIIADDR)

Definition at line 90 of file tm4c129_eth_driver.h.

◆ EMAC0_MIIDATA_R

#define EMAC0_MIIDATA_R   HWREG(EMAC0_BASE + EMAC_O_MIIDATA)

Definition at line 91 of file tm4c129_eth_driver.h.

◆ EMAC0_MMCCTRL_R

#define EMAC0_MMCCTRL_R   HWREG(EMAC0_BASE + EMAC_O_MMCCTRL)

Definition at line 108 of file tm4c129_eth_driver.h.

◆ EMAC0_MMCRXIM_R

#define EMAC0_MMCRXIM_R   HWREG(EMAC0_BASE + EMAC_O_MMCRXIM)

Definition at line 111 of file tm4c129_eth_driver.h.

◆ EMAC0_MMCRXRIS_R

#define EMAC0_MMCRXRIS_R   HWREG(EMAC0_BASE + EMAC_O_MMCRXRIS)

Definition at line 109 of file tm4c129_eth_driver.h.

◆ EMAC0_MMCTXIM_R

#define EMAC0_MMCTXIM_R   HWREG(EMAC0_BASE + EMAC_O_MMCTXIM)

Definition at line 112 of file tm4c129_eth_driver.h.

◆ EMAC0_MMCTXRIS_R

#define EMAC0_MMCTXRIS_R   HWREG(EMAC0_BASE + EMAC_O_MMCTXRIS)

Definition at line 110 of file tm4c129_eth_driver.h.

◆ EMAC0_PC_R

#define EMAC0_PC_R   HWREG(EMAC0_BASE + EMAC_O_PC)

Definition at line 152 of file tm4c129_eth_driver.h.

◆ EMAC0_PMTCTLSTAT_R

#define EMAC0_PMTCTLSTAT_R   HWREG(EMAC0_BASE + EMAC_O_PMTCTLSTAT)

Definition at line 96 of file tm4c129_eth_driver.h.

◆ EMAC0_PP_R

#define EMAC0_PP_R   HWREG(EMAC0_BASE + EMAC_O_PP)

Definition at line 151 of file tm4c129_eth_driver.h.

◆ EMAC0_PPS0INTVL_R

#define EMAC0_PPS0INTVL_R   HWREG(EMAC0_BASE + EMAC_O_PPS0INTVL)

Definition at line 135 of file tm4c129_eth_driver.h.

◆ EMAC0_PPS0WIDTH_R

#define EMAC0_PPS0WIDTH_R   HWREG(EMAC0_BASE + EMAC_O_PPS0WIDTH)

Definition at line 136 of file tm4c129_eth_driver.h.

◆ EMAC0_PPSCTRL_R

#define EMAC0_PPSCTRL_R   HWREG(EMAC0_BASE + EMAC_O_PPSCTRL)

Definition at line 134 of file tm4c129_eth_driver.h.

◆ EMAC0_RIS_R

#define EMAC0_RIS_R   HWREG(EMAC0_BASE + EMAC_O_RIS)

Definition at line 97 of file tm4c129_eth_driver.h.

◆ EMAC0_RWUFF_R

#define EMAC0_RWUFF_R   HWREG(EMAC0_BASE + EMAC_O_RWUFF)

Definition at line 95 of file tm4c129_eth_driver.h.

◆ EMAC0_RXCNTALGNERR_R

#define EMAC0_RXCNTALGNERR_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTALGNERR)

Definition at line 119 of file tm4c129_eth_driver.h.

◆ EMAC0_RXCNTCRCERR_R

#define EMAC0_RXCNTCRCERR_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTCRCERR)

Definition at line 118 of file tm4c129_eth_driver.h.

◆ EMAC0_RXCNTGB_R

#define EMAC0_RXCNTGB_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTGB)

Definition at line 117 of file tm4c129_eth_driver.h.

◆ EMAC0_RXCNTGUNI_R

#define EMAC0_RXCNTGUNI_R   HWREG(EMAC0_BASE + EMAC_O_RXCNTGUNI)

Definition at line 120 of file tm4c129_eth_driver.h.

◆ EMAC0_RXDLADDR_R

#define EMAC0_RXDLADDR_R   HWREG(EMAC0_BASE + EMAC_O_RXDLADDR)

Definition at line 140 of file tm4c129_eth_driver.h.

◆ EMAC0_RXINTWDT_R

#define EMAC0_RXINTWDT_R   HWREG(EMAC0_BASE + EMAC_O_RXINTWDT)

Definition at line 146 of file tm4c129_eth_driver.h.

◆ EMAC0_RXPOLLD_R

#define EMAC0_RXPOLLD_R   HWREG(EMAC0_BASE + EMAC_O_RXPOLLD)

Definition at line 139 of file tm4c129_eth_driver.h.

◆ EMAC0_STATUS_R

#define EMAC0_STATUS_R   HWREG(EMAC0_BASE + EMAC_O_STATUS)

Definition at line 94 of file tm4c129_eth_driver.h.

◆ EMAC0_SUBSECINC_R

#define EMAC0_SUBSECINC_R   HWREG(EMAC0_BASE + EMAC_O_SUBSECINC)

Definition at line 124 of file tm4c129_eth_driver.h.

◆ EMAC0_TARGNANO_R

#define EMAC0_TARGNANO_R   HWREG(EMAC0_BASE + EMAC_O_TARGNANO)

Definition at line 131 of file tm4c129_eth_driver.h.

◆ EMAC0_TARGSEC_R

#define EMAC0_TARGSEC_R   HWREG(EMAC0_BASE + EMAC_O_TARGSEC)

Definition at line 130 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMADD_R

#define EMAC0_TIMADD_R   HWREG(EMAC0_BASE + EMAC_O_TIMADD)

Definition at line 129 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMNANO_R

#define EMAC0_TIMNANO_R   HWREG(EMAC0_BASE + EMAC_O_TIMNANO)

Definition at line 126 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMNANOU_R

#define EMAC0_TIMNANOU_R   HWREG(EMAC0_BASE + EMAC_O_TIMNANOU)

Definition at line 128 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMSEC_R

#define EMAC0_TIMSEC_R   HWREG(EMAC0_BASE + EMAC_O_TIMSEC)

Definition at line 125 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMSECU_R

#define EMAC0_TIMSECU_R   HWREG(EMAC0_BASE + EMAC_O_TIMSECU)

Definition at line 127 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMSTAT_R

#define EMAC0_TIMSTAT_R   HWREG(EMAC0_BASE + EMAC_O_TIMSTAT)

Definition at line 133 of file tm4c129_eth_driver.h.

◆ EMAC0_TIMSTCTRL_R

#define EMAC0_TIMSTCTRL_R   HWREG(EMAC0_BASE + EMAC_O_TIMSTCTRL)

Definition at line 123 of file tm4c129_eth_driver.h.

◆ EMAC0_TXCNTGB_R

#define EMAC0_TXCNTGB_R   HWREG(EMAC0_BASE + EMAC_O_TXCNTGB)

Definition at line 113 of file tm4c129_eth_driver.h.

◆ EMAC0_TXCNTMCOL_R

#define EMAC0_TXCNTMCOL_R   HWREG(EMAC0_BASE + EMAC_O_TXCNTMCOL)

Definition at line 115 of file tm4c129_eth_driver.h.

◆ EMAC0_TXCNTSCOL_R

#define EMAC0_TXCNTSCOL_R   HWREG(EMAC0_BASE + EMAC_O_TXCNTSCOL)

Definition at line 114 of file tm4c129_eth_driver.h.

◆ EMAC0_TXDLADDR_R

#define EMAC0_TXDLADDR_R   HWREG(EMAC0_BASE + EMAC_O_TXDLADDR)

Definition at line 141 of file tm4c129_eth_driver.h.

◆ EMAC0_TXOCTCNTG_R

#define EMAC0_TXOCTCNTG_R   HWREG(EMAC0_BASE + EMAC_O_TXOCTCNTG)

Definition at line 116 of file tm4c129_eth_driver.h.

◆ EMAC0_TXPOLLD_R

#define EMAC0_TXPOLLD_R   HWREG(EMAC0_BASE + EMAC_O_TXPOLLD)

Definition at line 138 of file tm4c129_eth_driver.h.

◆ EMAC0_VLANHASH_R

#define EMAC0_VLANHASH_R   HWREG(EMAC0_BASE + EMAC_O_VLANHASH)

Definition at line 122 of file tm4c129_eth_driver.h.

◆ EMAC0_VLANTG_R

#define EMAC0_VLANTG_R   HWREG(EMAC0_BASE + EMAC_O_VLANTG)

Definition at line 93 of file tm4c129_eth_driver.h.

◆ EMAC0_VLNINCREP_R

#define EMAC0_VLNINCREP_R   HWREG(EMAC0_BASE + EMAC_O_VLNINCREP)

Definition at line 121 of file tm4c129_eth_driver.h.

◆ EMAC0_WDOGTO_R

#define EMAC0_WDOGTO_R   HWREG(EMAC0_BASE + EMAC_O_WDOGTO)

Definition at line 107 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PBL_1

#define EMAC_DMABUSMOD_PBL_1   (1 << EMAC_DMABUSMOD_PBL_S)

Definition at line 172 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PBL_16

#define EMAC_DMABUSMOD_PBL_16   (16 << EMAC_DMABUSMOD_PBL_S)

Definition at line 176 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PBL_2

#define EMAC_DMABUSMOD_PBL_2   (2 << EMAC_DMABUSMOD_PBL_S)

Definition at line 173 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PBL_32

#define EMAC_DMABUSMOD_PBL_32   (32 << EMAC_DMABUSMOD_PBL_S)

Definition at line 177 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PBL_4

#define EMAC_DMABUSMOD_PBL_4   (4 << EMAC_DMABUSMOD_PBL_S)

Definition at line 174 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PBL_8

#define EMAC_DMABUSMOD_PBL_8   (8 << EMAC_DMABUSMOD_PBL_S)

Definition at line 175 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PR_1_1

#define EMAC_DMABUSMOD_PR_1_1   (0 << EMAC_DMABUSMOD_PR_S)

Definition at line 167 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PR_2_1

#define EMAC_DMABUSMOD_PR_2_1   (1 << EMAC_DMABUSMOD_PR_S)

Definition at line 168 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PR_3_1

#define EMAC_DMABUSMOD_PR_3_1   (2 << EMAC_DMABUSMOD_PR_S)

Definition at line 169 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_PR_4_1

#define EMAC_DMABUSMOD_PR_4_1   (3 << EMAC_DMABUSMOD_PR_S)

Definition at line 170 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_RPBL_1

#define EMAC_DMABUSMOD_RPBL_1   (1 << EMAC_DMABUSMOD_RPBL_S)

Definition at line 160 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_RPBL_16

#define EMAC_DMABUSMOD_RPBL_16   (16 << EMAC_DMABUSMOD_RPBL_S)

Definition at line 164 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_RPBL_2

#define EMAC_DMABUSMOD_RPBL_2   (2 << EMAC_DMABUSMOD_RPBL_S)

Definition at line 161 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_RPBL_32

#define EMAC_DMABUSMOD_RPBL_32   (32 << EMAC_DMABUSMOD_RPBL_S)

Definition at line 165 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_RPBL_4

#define EMAC_DMABUSMOD_RPBL_4   (4 << EMAC_DMABUSMOD_RPBL_S)

Definition at line 162 of file tm4c129_eth_driver.h.

◆ EMAC_DMABUSMOD_RPBL_8

#define EMAC_DMABUSMOD_RPBL_8   (8 << EMAC_DMABUSMOD_RPBL_S)

Definition at line 163 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_AFM

#define EMAC_RDES0_AFM   0x40000000

Definition at line 217 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_CE

#define EMAC_RDES0_CE   0x00000002

Definition at line 233 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_DBE

#define EMAC_RDES0_DBE   0x00000004

Definition at line 232 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_DE

#define EMAC_RDES0_DE   0x00004000

Definition at line 220 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_ES

#define EMAC_RDES0_ES   0x00008000

Definition at line 219 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_ESA

#define EMAC_RDES0_ESA   0x00000001

Definition at line 234 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_FL

#define EMAC_RDES0_FL   0x3FFF0000

Definition at line 218 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_FS

#define EMAC_RDES0_FS   0x00000200

Definition at line 225 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_FT

#define EMAC_RDES0_FT   0x00000020

Definition at line 229 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_LCO

#define EMAC_RDES0_LCO   0x00000040

Definition at line 228 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_LE

#define EMAC_RDES0_LE   0x00001000

Definition at line 222 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_LS

#define EMAC_RDES0_LS   0x00000100

Definition at line 226 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_OE

#define EMAC_RDES0_OE   0x00000800

Definition at line 223 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_OWN

#define EMAC_RDES0_OWN   0x80000000

Definition at line 216 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_RE

#define EMAC_RDES0_RE   0x00000008

Definition at line 231 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_RWT

#define EMAC_RDES0_RWT   0x00000010

Definition at line 230 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_SAF

#define EMAC_RDES0_SAF   0x00002000

Definition at line 221 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_TSA_GF

#define EMAC_RDES0_TSA_GF   0x00000080

Definition at line 227 of file tm4c129_eth_driver.h.

◆ EMAC_RDES0_VLAN

#define EMAC_RDES0_VLAN   0x00000400

Definition at line 224 of file tm4c129_eth_driver.h.

◆ EMAC_RDES1_DIC

#define EMAC_RDES1_DIC   0x80000000

Definition at line 235 of file tm4c129_eth_driver.h.

◆ EMAC_RDES1_RBS1

#define EMAC_RDES1_RBS1   0x00001FFF

Definition at line 239 of file tm4c129_eth_driver.h.

◆ EMAC_RDES1_RBS2

#define EMAC_RDES1_RBS2   0x1FFF0000

Definition at line 236 of file tm4c129_eth_driver.h.

◆ EMAC_RDES1_RCH

#define EMAC_RDES1_RCH   0x00004000

Definition at line 238 of file tm4c129_eth_driver.h.

◆ EMAC_RDES1_RER

#define EMAC_RDES1_RER   0x00008000

Definition at line 237 of file tm4c129_eth_driver.h.

◆ EMAC_RDES2_RBAP1

#define EMAC_RDES2_RBAP1   0xFFFFFFFF

Definition at line 240 of file tm4c129_eth_driver.h.

◆ EMAC_RDES3_RBAP2

#define EMAC_RDES3_RBAP2   0xFFFFFFFF

Definition at line 241 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_IPCB

#define EMAC_RDES4_IPCB   0x00000020

Definition at line 248 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_IPHE

#define EMAC_RDES4_IPHE   0x00000008

Definition at line 250 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_IPPE

#define EMAC_RDES4_IPPE   0x00000010

Definition at line 249 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_IPPT

#define EMAC_RDES4_IPPT   0x00000007

Definition at line 251 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_IPV4PR

#define EMAC_RDES4_IPV4PR   0x00000040

Definition at line 247 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_IPV6PR

#define EMAC_RDES4_IPV6PR   0x00000080

Definition at line 246 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_PFT

#define EMAC_RDES4_PFT   0x00001000

Definition at line 244 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_PMT

#define EMAC_RDES4_PMT   0x00000F00

Definition at line 245 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_PV

#define EMAC_RDES4_PV   0x00002000

Definition at line 243 of file tm4c129_eth_driver.h.

◆ EMAC_RDES4_TSD

#define EMAC_RDES4_TSD   0x00004000

Definition at line 242 of file tm4c129_eth_driver.h.

◆ EMAC_RDES6_RTSL

#define EMAC_RDES6_RTSL   0xFFFFFFFF

Definition at line 252 of file tm4c129_eth_driver.h.

◆ EMAC_RDES7_RTSH

#define EMAC_RDES7_RTSH   0xFFFFFFFF

Definition at line 253 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_CC

#define EMAC_TDES0_CC   0x00000078

Definition at line 203 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_CIC

#define EMAC_TDES0_CIC   0x00C00000

Definition at line 188 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_CRCR

#define EMAC_TDES0_CRCR   0x01000000

Definition at line 187 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_DB

#define EMAC_TDES0_DB   0x00000001

Definition at line 206 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_DC

#define EMAC_TDES0_DC   0x08000000

Definition at line 184 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_DP

#define EMAC_TDES0_DP   0x04000000

Definition at line 185 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_EC

#define EMAC_TDES0_EC   0x00000100

Definition at line 201 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_ED

#define EMAC_TDES0_ED   0x00000004

Definition at line 204 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_ES

#define EMAC_TDES0_ES   0x00008000

Definition at line 194 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_FF

#define EMAC_TDES0_FF   0x00002000

Definition at line 196 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_FS

#define EMAC_TDES0_FS   0x10000000

Definition at line 183 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_IC

#define EMAC_TDES0_IC   0x40000000

Definition at line 181 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_IHE

#define EMAC_TDES0_IHE   0x00010000

Definition at line 193 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_IPE

#define EMAC_TDES0_IPE   0x00001000

Definition at line 197 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_JT

#define EMAC_TDES0_JT   0x00004000

Definition at line 195 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_LCA

#define EMAC_TDES0_LCA   0x00000800

Definition at line 198 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_LCO

#define EMAC_TDES0_LCO   0x00000200

Definition at line 200 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_LS

#define EMAC_TDES0_LS   0x20000000

Definition at line 182 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_NC

#define EMAC_TDES0_NC   0x00000400

Definition at line 199 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_OWN

#define EMAC_TDES0_OWN   0x80000000

Definition at line 180 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_TCH

#define EMAC_TDES0_TCH   0x00100000

Definition at line 190 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_TER

#define EMAC_TDES0_TER   0x00200000

Definition at line 189 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_TTSE

#define EMAC_TDES0_TTSE   0x02000000

Definition at line 186 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_TTSS

#define EMAC_TDES0_TTSS   0x00020000

Definition at line 192 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_UF

#define EMAC_TDES0_UF   0x00000002

Definition at line 205 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_VF

#define EMAC_TDES0_VF   0x00000080

Definition at line 202 of file tm4c129_eth_driver.h.

◆ EMAC_TDES0_VLIC

#define EMAC_TDES0_VLIC   0x000C0000

Definition at line 191 of file tm4c129_eth_driver.h.

◆ EMAC_TDES1_SAIC

#define EMAC_TDES1_SAIC   0xE0000000

Definition at line 207 of file tm4c129_eth_driver.h.

◆ EMAC_TDES1_TBS1

#define EMAC_TDES1_TBS1   0x00001FFF

Definition at line 209 of file tm4c129_eth_driver.h.

◆ EMAC_TDES1_TBS2

#define EMAC_TDES1_TBS2   0x1FFF0000

Definition at line 208 of file tm4c129_eth_driver.h.

◆ EMAC_TDES2_TBAP1

#define EMAC_TDES2_TBAP1   0xFFFFFFFF

Definition at line 210 of file tm4c129_eth_driver.h.

◆ EMAC_TDES3_TBAP2

#define EMAC_TDES3_TBAP2   0xFFFFFFFF

Definition at line 211 of file tm4c129_eth_driver.h.

◆ EMAC_TDES6_TTSL

#define EMAC_TDES6_TTSL   0xFFFFFFFF

Definition at line 212 of file tm4c129_eth_driver.h.

◆ EMAC_TDES7_TTSH

#define EMAC_TDES7_TTSH   0xFFFFFFFF

Definition at line 213 of file tm4c129_eth_driver.h.

◆ FLASH_CONF_R

#define FLASH_CONF_R   HWREG(FLASH_CONF)

Definition at line 81 of file tm4c129_eth_driver.h.

◆ TM4C129_ETH_IRQ_PRIORITY

#define TM4C129_ETH_IRQ_PRIORITY   192

Definition at line 74 of file tm4c129_eth_driver.h.

◆ TM4C129_ETH_IRQ_PRIORITY_GROUPING

#define TM4C129_ETH_IRQ_PRIORITY_GROUPING   3

Definition at line 67 of file tm4c129_eth_driver.h.

◆ TM4C129_ETH_RX_BUFFER_COUNT

#define TM4C129_ETH_RX_BUFFER_COUNT   6

Definition at line 53 of file tm4c129_eth_driver.h.

◆ TM4C129_ETH_RX_BUFFER_SIZE

#define TM4C129_ETH_RX_BUFFER_SIZE   1536

Definition at line 60 of file tm4c129_eth_driver.h.

◆ TM4C129_ETH_TX_BUFFER_COUNT

#define TM4C129_ETH_TX_BUFFER_COUNT   3

Definition at line 39 of file tm4c129_eth_driver.h.

◆ TM4C129_ETH_TX_BUFFER_SIZE

#define TM4C129_ETH_TX_BUFFER_SIZE   1536

Definition at line 46 of file tm4c129_eth_driver.h.

◆ tm4c129EthIrqHandler

void tm4c129EthIrqHandler   EMAC0_Handler

Definition at line 256 of file tm4c129_eth_driver.h.

Function Documentation

◆ tm4c129EthCalcCrc()

uint32_t tm4c129EthCalcCrc ( const void *  data,
size_t  length 
)

CRC calculation.

Parameters
[in]dataPointer to the data over which to calculate the CRC
[in]lengthNumber of bytes to process
Returns
Resulting CRC value

Definition at line 1091 of file tm4c129_eth_driver.c.

◆ tm4c129EthDisableIrq()

void tm4c129EthDisableIrq ( NetInterface interface)

Disable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 478 of file tm4c129_eth_driver.c.

◆ tm4c129EthDumpPhyReg()

void tm4c129EthDumpPhyReg ( void  )

Dump PHY registers for debugging purpose.

Definition at line 1067 of file tm4c129_eth_driver.c.

◆ tm4c129EthEnableIrq()

void tm4c129EthEnableIrq ( NetInterface interface)

Enable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 445 of file tm4c129_eth_driver.c.

◆ tm4c129EthEventHandler()

void tm4c129EthEventHandler ( NetInterface interface)

TM4C129 Ethernet MAC event handler.

Parameters
[in]interfaceUnderlying network interface

Definition at line 578 of file tm4c129_eth_driver.c.

◆ tm4c129EthInit()

error_t tm4c129EthInit ( NetInterface interface)

TM4C129 Ethernet MAC initialization.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 124 of file tm4c129_eth_driver.c.

◆ tm4c129EthInitDmaDesc()

void tm4c129EthInitDmaDesc ( NetInterface interface)

Initialize DMA descriptor lists.

Parameters
[in]interfaceUnderlying network interface

Definition at line 351 of file tm4c129_eth_driver.c.

◆ tm4c129EthInitGpio()

void tm4c129EthInitGpio ( NetInterface interface)

GPIO configuration.

Parameters
[in]interfaceUnderlying network interface

Definition at line 314 of file tm4c129_eth_driver.c.

◆ tm4c129EthReadPhyReg()

uint16_t tm4c129EthReadPhyReg ( uint8_t  opcode,
uint8_t  phyAddr,
uint8_t  regAddr 
)

Read PHY register.

Parameters
[in]opcodeAccess type (2 bits)
[in]phyAddrPHY address (5 bits)
[in]regAddrRegister address (5 bits)
Returns
Register value

Definition at line 1024 of file tm4c129_eth_driver.c.

◆ tm4c129EthReceivePacket()

error_t tm4c129EthReceivePacket ( NetInterface interface)

Receive a packet.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 747 of file tm4c129_eth_driver.c.

◆ tm4c129EthSendPacket()

error_t tm4c129EthSendPacket ( NetInterface interface,
const NetBuffer buffer,
size_t  offset,
NetTxAncillary ancillary 
)

Send a packet.

Parameters
[in]interfaceUnderlying network interface
[in]bufferMulti-part buffer containing the data to send
[in]offsetOffset to the first data byte
[in]ancillaryAdditional options passed to the stack along with the packet
Returns
Error code

Definition at line 688 of file tm4c129_eth_driver.c.

◆ tm4c129EthTick()

void tm4c129EthTick ( NetInterface interface)

TM4C129 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters
[in]interfaceUnderlying network interface

Definition at line 420 of file tm4c129_eth_driver.c.

◆ tm4c129EthUpdateMacAddrFilter()

error_t tm4c129EthUpdateMacAddrFilter ( NetInterface interface)

Configure MAC address filtering.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 817 of file tm4c129_eth_driver.c.

◆ tm4c129EthUpdateMacConfig()

error_t tm4c129EthUpdateMacConfig ( NetInterface interface)

Adjust MAC configuration parameters for proper operation.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 939 of file tm4c129_eth_driver.c.

◆ tm4c129EthWritePhyReg()

void tm4c129EthWritePhyReg ( uint8_t  opcode,
uint8_t  phyAddr,
uint8_t  regAddr,
uint16_t  data 
)

Write PHY register.

Parameters
[in]opcodeAccess type (2 bits)
[in]phyAddrPHY address (5 bits)
[in]regAddrRegister address (5 bits)
[in]dataRegister value

Definition at line 982 of file tm4c129_eth_driver.c.

Variable Documentation

◆ tm4c129EthDriver

const NicDriver tm4c129EthDriver
extern

TM4C129 Ethernet MAC driver.

Definition at line 97 of file tm4c129_eth_driver.c.