tm4c129_eth_driver.h
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1 /**
2  * @file tm4c129_eth_driver.h
3  * @brief Tiva TM4C129 Ethernet controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _TM4C129_ETH_DRIVER_H
30 #define _TM4C129_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef TM4C129_ETH_TX_BUFFER_COUNT
37  #define TM4C129_ETH_TX_BUFFER_COUNT 3
38 #elif (TM4C129_ETH_TX_BUFFER_COUNT < 1)
39  #error TM4C129_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef TM4C129_ETH_TX_BUFFER_SIZE
44  #define TM4C129_ETH_TX_BUFFER_SIZE 1536
45 #elif (TM4C129_ETH_TX_BUFFER_SIZE != 1536)
46  #error TM4C129_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef TM4C129_ETH_RX_BUFFER_COUNT
51  #define TM4C129_ETH_RX_BUFFER_COUNT 6
52 #elif (TM4C129_ETH_RX_BUFFER_COUNT < 1)
53  #error TM4C129_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef TM4C129_ETH_RX_BUFFER_SIZE
58  #define TM4C129_ETH_RX_BUFFER_SIZE 1536
59 #elif (TM4C129_ETH_RX_BUFFER_SIZE != 1536)
60  #error TM4C129_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef TM4C129_ETH_IRQ_PRIORITY_GROUPING
65  #define TM4C129_ETH_IRQ_PRIORITY_GROUPING 3
66 #elif (TM4C129_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error TM4C129_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt priority
71 #ifndef TM4C129_ETH_IRQ_PRIORITY
72  #define TM4C129_ETH_IRQ_PRIORITY 192
73 #elif (TM4C129_ETH_IRQ_PRIORITY < 0)
74  #error TM4C129_ETH_IRQ_PRIORITY parameter is not valid
75 #endif
76 
77 //DMABUSMOD register
78 #define EMAC_DMABUSMOD_RPBL_1 (1 << EMAC_DMABUSMOD_RPBL_S)
79 #define EMAC_DMABUSMOD_RPBL_2 (2 << EMAC_DMABUSMOD_RPBL_S)
80 #define EMAC_DMABUSMOD_RPBL_4 (4 << EMAC_DMABUSMOD_RPBL_S)
81 #define EMAC_DMABUSMOD_RPBL_8 (8 << EMAC_DMABUSMOD_RPBL_S)
82 #define EMAC_DMABUSMOD_RPBL_16 (16 << EMAC_DMABUSMOD_RPBL_S)
83 #define EMAC_DMABUSMOD_RPBL_32 (32 << EMAC_DMABUSMOD_RPBL_S)
84 
85 #define EMAC_DMABUSMOD_PR_1_1 (0 << EMAC_DMABUSMOD_PR_S)
86 #define EMAC_DMABUSMOD_PR_2_1 (1 << EMAC_DMABUSMOD_PR_S)
87 #define EMAC_DMABUSMOD_PR_3_1 (2 << EMAC_DMABUSMOD_PR_S)
88 #define EMAC_DMABUSMOD_PR_4_1 (3 << EMAC_DMABUSMOD_PR_S)
89 
90 #define EMAC_DMABUSMOD_PBL_1 (1 << EMAC_DMABUSMOD_PBL_S)
91 #define EMAC_DMABUSMOD_PBL_2 (2 << EMAC_DMABUSMOD_PBL_S)
92 #define EMAC_DMABUSMOD_PBL_4 (4 << EMAC_DMABUSMOD_PBL_S)
93 #define EMAC_DMABUSMOD_PBL_8 (8 << EMAC_DMABUSMOD_PBL_S)
94 #define EMAC_DMABUSMOD_PBL_16 (16 << EMAC_DMABUSMOD_PBL_S)
95 #define EMAC_DMABUSMOD_PBL_32 (32 << EMAC_DMABUSMOD_PBL_S)
96 
97 //Transmit DMA descriptor flags
98 #define EMAC_TDES0_OWN 0x80000000
99 #define EMAC_TDES0_IC 0x40000000
100 #define EMAC_TDES0_LS 0x20000000
101 #define EMAC_TDES0_FS 0x10000000
102 #define EMAC_TDES0_DC 0x08000000
103 #define EMAC_TDES0_DP 0x04000000
104 #define EMAC_TDES0_TTSE 0x02000000
105 #define EMAC_TDES0_CRCR 0x01000000
106 #define EMAC_TDES0_CIC 0x00C00000
107 #define EMAC_TDES0_TER 0x00200000
108 #define EMAC_TDES0_TCH 0x00100000
109 #define EMAC_TDES0_VLIC 0x000C0000
110 #define EMAC_TDES0_TTSS 0x00020000
111 #define EMAC_TDES0_IHE 0x00010000
112 #define EMAC_TDES0_ES 0x00008000
113 #define EMAC_TDES0_JT 0x00004000
114 #define EMAC_TDES0_FF 0x00002000
115 #define EMAC_TDES0_IPE 0x00001000
116 #define EMAC_TDES0_LCA 0x00000800
117 #define EMAC_TDES0_NC 0x00000400
118 #define EMAC_TDES0_LCO 0x00000200
119 #define EMAC_TDES0_EC 0x00000100
120 #define EMAC_TDES0_VF 0x00000080
121 #define EMAC_TDES0_CC 0x00000078
122 #define EMAC_TDES0_ED 0x00000004
123 #define EMAC_TDES0_UF 0x00000002
124 #define EMAC_TDES0_DB 0x00000001
125 #define EMAC_TDES1_SAIC 0xE0000000
126 #define EMAC_TDES1_TBS2 0x1FFF0000
127 #define EMAC_TDES1_TBS1 0x00001FFF
128 #define EMAC_TDES2_TBAP1 0xFFFFFFFF
129 #define EMAC_TDES3_TBAP2 0xFFFFFFFF
130 #define EMAC_TDES6_TTSL 0xFFFFFFFF
131 #define EMAC_TDES7_TTSH 0xFFFFFFFF
132 
133 //Receive DMA descriptor flags
134 #define EMAC_RDES0_OWN 0x80000000
135 #define EMAC_RDES0_AFM 0x40000000
136 #define EMAC_RDES0_FL 0x3FFF0000
137 #define EMAC_RDES0_ES 0x00008000
138 #define EMAC_RDES0_DE 0x00004000
139 #define EMAC_RDES0_SAF 0x00002000
140 #define EMAC_RDES0_LE 0x00001000
141 #define EMAC_RDES0_OE 0x00000800
142 #define EMAC_RDES0_VLAN 0x00000400
143 #define EMAC_RDES0_FS 0x00000200
144 #define EMAC_RDES0_LS 0x00000100
145 #define EMAC_RDES0_TSA_GF 0x00000080
146 #define EMAC_RDES0_LCO 0x00000040
147 #define EMAC_RDES0_FT 0x00000020
148 #define EMAC_RDES0_RWT 0x00000010
149 #define EMAC_RDES0_RE 0x00000008
150 #define EMAC_RDES0_DBE 0x00000004
151 #define EMAC_RDES0_CE 0x00000002
152 #define EMAC_RDES0_ESA 0x00000001
153 #define EMAC_RDES1_DIC 0x80000000
154 #define EMAC_RDES1_RBS2 0x1FFF0000
155 #define EMAC_RDES1_RER 0x00008000
156 #define EMAC_RDES1_RCH 0x00004000
157 #define EMAC_RDES1_RBS1 0x00001FFF
158 #define EMAC_RDES2_RBAP1 0xFFFFFFFF
159 #define EMAC_RDES3_RBAP2 0xFFFFFFFF
160 #define EMAC_RDES4_TSD 0x00004000
161 #define EMAC_RDES4_PV 0x00002000
162 #define EMAC_RDES4_PFT 0x00001000
163 #define EMAC_RDES4_PMT 0x00000F00
164 #define EMAC_RDES4_IPV6PR 0x00000080
165 #define EMAC_RDES4_IPV4PR 0x00000040
166 #define EMAC_RDES4_IPCB 0x00000020
167 #define EMAC_RDES4_IPPE 0x00000010
168 #define EMAC_RDES4_IPHE 0x00000008
169 #define EMAC_RDES4_IPPT 0x00000007
170 #define EMAC_RDES6_RTSL 0xFFFFFFFF
171 #define EMAC_RDES7_RTSH 0xFFFFFFFF
172 
173 //C++ guard
174 #ifdef __cplusplus
175  extern "C" {
176 #endif
177 
178 
179 /**
180  * @brief Enhanced TX DMA descriptor
181  **/
182 
183 typedef struct
184 {
185  uint32_t tdes0;
186  uint32_t tdes1;
187  uint32_t tdes2;
188  uint32_t tdes3;
189  uint32_t tdes4;
190  uint32_t tdes5;
191  uint32_t tdes6;
192  uint32_t tdes7;
194 
195 
196 /**
197  * @brief Enhanced RX DMA descriptor
198  **/
199 
200 typedef struct
201 {
202  uint32_t rdes0;
203  uint32_t rdes1;
204  uint32_t rdes2;
205  uint32_t rdes3;
206  uint32_t rdes4;
207  uint32_t rdes5;
208  uint32_t rdes6;
209  uint32_t rdes7;
211 
212 
213 //TM4C129 Ethernet MAC driver
214 extern const NicDriver tm4c129EthDriver;
215 
216 //TM4C129 Ethernet MAC related functions
218 void tm4c129EthInitGpio(NetInterface *interface);
219 void tm4c129EthInitDmaDesc(NetInterface *interface);
220 
221 void tm4c129EthTick(NetInterface *interface);
222 
223 void tm4c129EthEnableIrq(NetInterface *interface);
224 void tm4c129EthDisableIrq(NetInterface *interface);
225 void tm4c129EthEventHandler(NetInterface *interface);
226 
228  const NetBuffer *buffer, size_t offset);
229 
231 
233 
234 void tm4c129EthWritePhyReg(uint8_t regAddr, uint16_t data);
235 uint16_t tm4c129EthReadPhyReg(uint8_t regAddr);
236 void tm4c129EthDumpPhyReg(void);
237 
238 uint32_t tm4c129EthCalcCrc(const void *data, size_t length);
239 
240 //C++ guard
241 #ifdef __cplusplus
242  }
243 #endif
244 
245 #endif
error_t tm4c129EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void tm4c129EthEnableIrq(NetInterface *interface)
Enable interrupts.
void tm4c129EthTick(NetInterface *interface)
TM4C129 Ethernet MAC timer handler.
error_t tm4c129EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void tm4c129EthInitGpio(NetInterface *interface)
uint16_t tm4c129EthReadPhyReg(uint8_t regAddr)
Read PHY register.
uint32_t tm4c129EthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t tm4c129EthReceivePacket(NetInterface *interface)
Receive a packet.
void tm4c129EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
const NicDriver tm4c129EthDriver
Tiva TM4C129 Ethernet MAC driver.
uint16_t regAddr
void tm4c129EthEventHandler(NetInterface *interface)
TM4C129 Ethernet MAC event handler.
error_t
Error codes.
Definition: error.h:40
void tm4c129EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t tm4c129EthInit(NetInterface *interface)
Tiva TM4C129 Ethernet MAC initialization.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
Enhanced RX DMA descriptor.
uint8_t length
Definition: dtls_misc.h:140
void tm4c129EthWritePhyReg(uint8_t regAddr, uint16_t data)
Write PHY register.
void tm4c129EthDumpPhyReg(void)
Dump PHY registers for debugging purpose.
Enhanced TX DMA descriptor.
Network interface controller abstraction layer.