tm4c129_eth_driver.c
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1 /**
2  * @file tm4c129_eth_driver.c
3  * @brief Tiva TM4C129 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //TM4C1294NCPDT device?
35 #if defined(PART_TM4C1294NCPDT)
36  #include "tm4c1294ncpdt.h"
37 //TM4C129XNCZAD device?
38 #elif defined(PART_TM4C129XNCZAD)
39  #include "tm4c129xnczad.h"
40 #endif
41 
42 //Dependencies
43 #include <stdint.h>
44 #include <stdbool.h>
45 #include "inc/hw_emac.h"
46 #include "inc/hw_memmap.h"
47 #include "inc/hw_types.h"
48 #include "driverlib/gpio.h"
49 #include "driverlib/interrupt.h"
50 #include "driverlib/pin_map.h"
51 #include "driverlib/sysctl.h"
52 #include "core/net.h"
54 #include "debug.h"
55 
56 //Underlying network interface
57 static NetInterface *nicDriverInterface;
58 
59 //IAR EWARM compiler?
60 #if defined(__ICCARM__)
61 
62 //Transmit buffer
63 #pragma data_alignment = 4
65 //Receive buffer
66 #pragma data_alignment = 4
68 //Transmit DMA descriptors
69 #pragma data_alignment = 4
71 //Receive DMA descriptors
72 #pragma data_alignment = 4
74 
75 //Keil MDK-ARM or GCC compiler?
76 #else
77 
78 //Transmit buffer
80  __attribute__((aligned(4)));
81 //Receive buffer
83  __attribute__((aligned(4)));
84 //Transmit DMA descriptors
86  __attribute__((aligned(4)));
87 //Receive DMA descriptors
89  __attribute__((aligned(4)));
90 
91 #endif
92 
93 //Pointer to the current TX DMA descriptor
94 static Tm4c129TxDmaDesc *txCurDmaDesc;
95 //Pointer to the current RX DMA descriptor
96 static Tm4c129RxDmaDesc *rxCurDmaDesc;
97 
98 
99 /**
100  * @brief Tiva TM4C129 Ethernet MAC driver
101  **/
102 
104 {
106  ETH_MTU,
114  NULL,
115  NULL,
116  NULL,
117  TRUE,
118  TRUE,
119  TRUE,
120  FALSE
121 };
122 
123 
124 /**
125  * @brief Tiva TM4C129 Ethernet MAC initialization
126  * @param[in] interface Underlying network interface
127  * @return Error code
128  **/
129 
131 {
132  //Debug message
133  TRACE_INFO("Initializing Tiva TM4C129 Ethernet controller...\r\n");
134 
135  //Save underlying network interface
136  nicDriverInterface = interface;
137 
138  //Enable Ethernet controller clock
139  SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
140 
141  //Reset Ethernet controller
142  SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
143  //Wait for the reset to complete
144  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
145  {
146  }
147 
148  //Enable internal PHY clock
149  SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
150 
151  //Reset internal PHY
152  SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
153  //Wait for the reset to complete
154  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0))
155  {
156  }
157 
158  //GPIO configuration
159  tm4c129EthInitGpio(interface);
160 
161  //Perform a software reset
162  EMAC0_DMABUSMOD_R |= EMAC_DMABUSMOD_SWR;
163  //Wait for the reset to complete
164  while((EMAC0_DMABUSMOD_R & EMAC_DMABUSMOD_SWR) != 0)
165  {
166  }
167 
168  //Adjust MDC clock range depending on SYSCLK frequency
169  EMAC0_MIIADDR_R = EMAC_MIIADDR_CR_100_150;
170 
171  //Reset PHY transceiver
172  tm4c129EthWritePhyReg(EPHY_BMCR, EPHY_BMCR_MIIRESET);
173  //Wait for the reset to complete
174  while(tm4c129EthReadPhyReg(EPHY_BMCR) & EPHY_BMCR_MIIRESET)
175  {
176  }
177 
178  //Dump PHY registers for debugging purpose
180 
181  //Configure LED0, LED1 and LED2
182  tm4c129EthWritePhyReg(EPHY_LEDCFG, EPHY_LEDCFG_LED0_TX |
183  EPHY_LEDCFG_LED1_RX | EPHY_LEDCFG_LED2_LINK);
184 
185  //Configure PHY interrupts as desired
186  tm4c129EthWritePhyReg(EPHY_MISR1, EPHY_MISR1_LINKSTATEN);
187  //Enable PHY interrupts
188  tm4c129EthWritePhyReg(EPHY_SCR, EPHY_SCR_INTEN);
189 
190  //Use default MAC configuration
191  EMAC0_CFG_R = EMAC_CFG_DRO;
192 
193  //Set the MAC address of the station
194  EMAC0_ADDR0L_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
195  EMAC0_ADDR0H_R = interface->macAddr.w[2];
196 
197  //The MAC supports 3 additional addresses for unicast perfect filtering
198  EMAC0_ADDR1L_R = 0;
199  EMAC0_ADDR1H_R = 0;
200  EMAC0_ADDR2L_R = 0;
201  EMAC0_ADDR2H_R = 0;
202  EMAC0_ADDR3L_R = 0;
203  EMAC0_ADDR3H_R = 0;
204 
205  //Initialize hash table
206  EMAC0_HASHTBLL_R = 0;
207  EMAC0_HASHTBLH_R = 0;
208 
209  //Configure the receive filter
210  EMAC0_FRAMEFLTR_R = EMAC_FRAMEFLTR_HPF | EMAC_FRAMEFLTR_HMC;
211  //Disable flow control
212  EMAC0_FLOWCTL_R = 0;
213  //Enable store and forward mode
214  EMAC0_DMAOPMODE_R = EMAC_DMAOPMODE_RSF | EMAC_DMAOPMODE_TSF;
215 
216  //Configure DMA bus mode
217  EMAC0_DMABUSMOD_R = EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_USP | EMAC_DMABUSMOD_RPBL_1 |
218  EMAC_DMABUSMOD_PR_1_1 | EMAC_DMABUSMOD_PBL_1 | EMAC_DMABUSMOD_ATDS;
219 
220  //Initialize DMA descriptor lists
221  tm4c129EthInitDmaDesc(interface);
222 
223  //Prevent interrupts from being generated when the transmit statistic
224  //counters reach half their maximum value
225  EMAC0_MMCTXIM_R = EMAC_MMCTXIM_OCTCNT | EMAC_MMCTXIM_MCOLLGF |
226  EMAC_MMCTXIM_SCOLLGF | EMAC_MMCTXIM_GBF;
227 
228  //Prevent interrupts from being generated when the receive statistic
229  //counters reach half their maximum value
230  EMAC0_MMCRXIM_R = EMAC_MMCRXIM_UCGF | EMAC_MMCRXIM_ALGNERR |
231  EMAC_MMCRXIM_CRCERR | EMAC_MMCRXIM_GBF;
232 
233  //Disable MAC interrupts
234  EMAC0_IM_R = EMAC_IM_TSI | EMAC_IM_PMT;
235  //Enable the desired DMA interrupts
236  EMAC0_DMAIM_R = EMAC_DMAIM_NIE | EMAC_DMAIM_RIE | EMAC_DMAIM_TIE;
237  //Enable PHY interrupts
238  EMAC0_EPHYIM_R = EMAC_EPHYIM_INT;
239 
240  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
241  IntPriorityGroupingSet(TM4C129_ETH_IRQ_PRIORITY_GROUPING);
242  //Configure Ethernet interrupt priority
243  IntPrioritySet(INT_EMAC0, TM4C129_ETH_IRQ_PRIORITY);
244 
245  //Enable MAC transmission and reception
246  EMAC0_CFG_R |= EMAC_CFG_TE | EMAC_CFG_RE;
247  //Enable DMA transmission and reception
248  EMAC0_DMAOPMODE_R |= EMAC_DMAOPMODE_ST | EMAC_DMAOPMODE_SR;
249 
250  //Accept any packets from the upper layer
251  osSetEvent(&interface->nicTxEvent);
252 
253  //Successful initialization
254  return NO_ERROR;
255 }
256 
257 
258 //DK-TM4C129X or EK-TM4C1294XL evaluation board?
259 #if defined(USE_DK_TM4C129X) || defined(USE_EK_TM4C1294XL)
260 
261 /**
262  * @brief GPIO configuration
263  * @param[in] interface Underlying network interface
264  **/
265 
266 void tm4c129EthInitGpio(NetInterface *interface)
267 {
268 //DK-TM4C129X evaluation board?
269 #if defined(USE_DK_TM4C129X)
270  //Enable GPIO clocks
271  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
272  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
273 
274  //Select the relevant alternate function for PF1, PK4 and PK6
275  GPIOPinConfigure(GPIO_PF1_EN0LED2);
276  GPIOPinConfigure(GPIO_PK4_EN0LED0);
277  GPIOPinConfigure(GPIO_PK6_EN0LED1);
278 
279  //Configure Ethernet LED pins for proper operation
280  GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_1);
281  GPIOPinTypeEthernetLED(GPIO_PORTK_BASE, GPIO_PIN_4 | GPIO_PIN_6);
282 
283 //EK-TM4C1294XL evaluation board?
284 #elif defined(USE_EK_TM4C1294XL)
285  //Enable GPIO clock
286  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
287 
288  //Select the relevant alternate function for PF0 and PF4
289  GPIOPinConfigure(GPIO_PF0_EN0LED0);
290  GPIOPinConfigure(GPIO_PF4_EN0LED1);
291 
292  //Configure Ethernet LED pins for proper operation
293  GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4);
294 #endif
295 }
296 
297 #endif
298 
299 
300 /**
301  * @brief Initialize DMA descriptor lists
302  * @param[in] interface Underlying network interface
303  **/
304 
306 {
307  uint_t i;
308 
309  //Initialize TX DMA descriptor list
310  for(i = 0; i < TM4C129_ETH_TX_BUFFER_COUNT; i++)
311  {
312  //Use chain structure rather than ring structure
314  //Initialize transmit buffer size
315  txDmaDesc[i].tdes1 = 0;
316  //Transmit buffer address
317  txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
318  //Next descriptor address
319  txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
320  //Reserved fields
321  txDmaDesc[i].tdes4 = 0;
322  txDmaDesc[i].tdes5 = 0;
323  //Transmit frame time stamp
324  txDmaDesc[i].tdes6 = 0;
325  txDmaDesc[i].tdes7 = 0;
326  }
327 
328  //The last descriptor is chained to the first entry
329  txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
330  //Point to the very first descriptor
331  txCurDmaDesc = &txDmaDesc[0];
332 
333  //Initialize RX DMA descriptor list
334  for(i = 0; i < TM4C129_ETH_RX_BUFFER_COUNT; i++)
335  {
336  //The descriptor is initially owned by the DMA
337  rxDmaDesc[i].rdes0 = EMAC_RDES0_OWN;
338  //Use chain structure rather than ring structure
340  //Receive buffer address
341  rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
342  //Next descriptor address
343  rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
344  //Extended status
345  rxDmaDesc[i].rdes4 = 0;
346  //Reserved field
347  rxDmaDesc[i].rdes5 = 0;
348  //Receive frame time stamp
349  rxDmaDesc[i].rdes6 = 0;
350  rxDmaDesc[i].rdes7 = 0;
351  }
352 
353  //The last descriptor is chained to the first entry
354  rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
355  //Point to the very first descriptor
356  rxCurDmaDesc = &rxDmaDesc[0];
357 
358  //Start location of the TX descriptor list
359  EMAC0_TXDLADDR_R = (uint32_t) txDmaDesc;
360  //Start location of the RX descriptor list
361  EMAC0_RXDLADDR_R = (uint32_t) rxDmaDesc;
362 }
363 
364 
365 /**
366  * @brief TM4C129 Ethernet MAC timer handler
367  *
368  * This routine is periodically called by the TCP/IP stack to handle periodic
369  * operations such as polling the link state
370  *
371  * @param[in] interface Underlying network interface
372  **/
373 
374 void tm4c129EthTick(NetInterface *interface)
375 {
376 }
377 
378 
379 /**
380  * @brief Enable interrupts
381  * @param[in] interface Underlying network interface
382  **/
383 
385 {
386  //Enable Ethernet MAC interrupts
387  IntEnable(INT_EMAC0);
388 }
389 
390 
391 /**
392  * @brief Disable interrupts
393  * @param[in] interface Underlying network interface
394  **/
395 
397 {
398  //Disable Ethernet MAC interrupts
399  IntDisable(INT_EMAC0);
400 }
401 
402 
403 /**
404  * @brief TM4C129 Ethernet MAC interrupt service routine
405  **/
406 
407 void EMAC0_Handler(void)
408 {
409  bool_t flag;
410  uint32_t status;
411 
412  //Interrupt service routine prologue
413  osEnterIsr();
414 
415  //This flag will be set if a higher priority task must be woken
416  flag = FALSE;
417 
418  //Read PHY status register
419  status = EMAC0_EPHYRIS_R;
420 
421  //PHY interrupt?
422  if((status & EMAC_EPHYRIS_INT) != 0)
423  {
424  //Disable PHY interrupt
425  EMAC0_EPHYIM_R &= ~EMAC_EPHYIM_INT;
426 
427  //Set event flag
428  nicDriverInterface->nicEvent = TRUE;
429  //Notify the TCP/IP stack of the event
430  flag |= osSetEventFromIsr(&netEvent);
431  }
432 
433  //Read DMA status register
434  status = EMAC0_DMARIS_R;
435 
436  //Packet transmitted?
437  if((status & EMAC_DMARIS_TI) != 0)
438  {
439  //Clear TI interrupt flag
440  EMAC0_DMARIS_R = EMAC_DMARIS_TI;
441 
442  //Check whether the TX buffer is available for writing
443  if((txCurDmaDesc->tdes0 & EMAC_TDES0_OWN) == 0)
444  {
445  //Notify the TCP/IP stack that the transmitter is ready to send
446  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
447  }
448  }
449 
450  //Packet received?
451  if((status & EMAC_DMARIS_RI) != 0)
452  {
453  //Disable RIE interrupt
454  EMAC0_DMAIM_R &= ~EMAC_DMAIM_RIE;
455 
456  //Set event flag
457  nicDriverInterface->nicEvent = TRUE;
458  //Notify the TCP/IP stack of the event
459  flag |= osSetEventFromIsr(&netEvent);
460  }
461 
462  //Clear NIS interrupt flag
463  EMAC0_DMARIS_R = EMAC_DMARIS_NIS;
464 
465  //Interrupt service routine epilogue
466  osExitIsr(flag);
467 }
468 
469 
470 /**
471  * @brief TM4C129 Ethernet MAC event handler
472  * @param[in] interface Underlying network interface
473  **/
474 
476 {
477  error_t error;
478  uint32_t status;
479 
480  //PHY interrupt?
481  if((EMAC0_EPHYRIS_R & EMAC_EPHYRIS_INT) != 0)
482  {
483  //Clear PHY interrupt flag
484  EMAC0_EPHYMISC_R = EMAC_EPHYMISC_INT;
485  //Read PHY interrupt status register
486  status = tm4c129EthReadPhyReg(EPHY_MISR1);
487 
488  //Check whether the link state has changed?
489  if((status & EPHY_MISR1_LINKSTAT) != 0)
490  {
491  //Read BMSR register
492  status = tm4c129EthReadPhyReg(EPHY_BMSR);
493 
494  //Check whether the link is up
495  if((status & EPHY_BMSR_LINKSTAT) != 0)
496  {
497  //Read PHY status register
498  status = tm4c129EthReadPhyReg(EPHY_STS);
499 
500  //Check current speed
501  if((status & EPHY_STS_SPEED) != 0)
502  {
503  //10BASE-T operation
504  interface->linkSpeed = NIC_LINK_SPEED_10MBPS;
505  //Update MAC configuration
506  EMAC0_CFG_R &= ~EMAC_CFG_FES;
507  }
508  else
509  {
510  //100BASE-TX operation
511  interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
512  //Update MAC configuration
513  EMAC0_CFG_R |= EMAC_CFG_FES;
514  }
515 
516  //Check current duplex mode
517  if((status & EPHY_STS_DUPLEX) != 0)
518  {
519  //Full-Duplex mode
520  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
521  //Update MAC configuration
522  EMAC0_CFG_R |= EMAC_CFG_DUPM;
523  }
524  else
525  {
526  //Half-Duplex mode
527  interface->duplexMode = NIC_HALF_DUPLEX_MODE;
528  //Update MAC configuration
529  EMAC0_CFG_R &= ~EMAC_CFG_DUPM;
530  }
531 
532  //Update link state
533  interface->linkState = TRUE;
534  }
535  else
536  {
537  //Update link state
538  interface->linkState = FALSE;
539  }
540 
541  //Process link state change event
542  nicNotifyLinkChange(interface);
543  }
544  }
545 
546  //Packet received?
547  if((EMAC0_DMARIS_R & EMAC_DMARIS_RI) != 0)
548  {
549  //Clear interrupt flag
550  EMAC0_DMARIS_R = EMAC_DMARIS_RI;
551 
552  //Process all pending packets
553  do
554  {
555  //Read incoming packet
556  error = tm4c129EthReceivePacket(interface);
557 
558  //No more data in the receive buffer?
559  } while(error != ERROR_BUFFER_EMPTY);
560  }
561 
562  //Re-enable DMA interrupts
563  EMAC0_DMAIM_R = EMAC_DMAIM_NIE | EMAC_DMAIM_RIE | EMAC_DMAIM_TIE;
564  //Re-enable PHY interrupts
565  EMAC0_EPHYIM_R = EMAC_EPHYIM_INT;
566 }
567 
568 
569 /**
570  * @brief Send a packet
571  * @param[in] interface Underlying network interface
572  * @param[in] buffer Multi-part buffer containing the data to send
573  * @param[in] offset Offset to the first data byte
574  * @param[in] ancillary Additional options passed to the stack along with
575  * the packet
576  * @return Error code
577  **/
578 
580  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
581 {
582  size_t length;
583 
584  //Retrieve the length of the packet
585  length = netBufferGetLength(buffer) - offset;
586 
587  //Check the frame length
589  {
590  //The transmitter can accept another packet
591  osSetEvent(&interface->nicTxEvent);
592  //Report an error
593  return ERROR_INVALID_LENGTH;
594  }
595 
596  //Make sure the current buffer is available for writing
597  if((txCurDmaDesc->tdes0 & EMAC_TDES0_OWN) != 0)
598  {
599  return ERROR_FAILURE;
600  }
601 
602  //Copy user data to the transmit buffer
603  netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
604 
605  //Write the number of bytes to send
606  txCurDmaDesc->tdes1 = length & EMAC_TDES1_TBS1;
607  //Set LS and FS flags as the data fits in a single buffer
608  txCurDmaDesc->tdes0 |= EMAC_TDES0_LS | EMAC_TDES0_FS;
609  //Give the ownership of the descriptor to the DMA
610  txCurDmaDesc->tdes0 |= EMAC_TDES0_OWN;
611 
612  //Clear TU flag to resume processing
613  EMAC0_DMARIS_R = EMAC_DMARIS_TU;
614  //Instruct the DMA to poll the transmit descriptor list
615  EMAC0_TXPOLLD_R = 0;
616 
617  //Point to the next descriptor in the list
618  txCurDmaDesc = (Tm4c129TxDmaDesc *) txCurDmaDesc->tdes3;
619 
620  //Check whether the next buffer is available for writing
621  if((txCurDmaDesc->tdes0 & EMAC_TDES0_OWN) == 0)
622  {
623  //The transmitter can accept another packet
624  osSetEvent(&interface->nicTxEvent);
625  }
626 
627  //Data successfully written
628  return NO_ERROR;
629 }
630 
631 
632 /**
633  * @brief Receive a packet
634  * @param[in] interface Underlying network interface
635  * @return Error code
636  **/
637 
639 {
640  error_t error;
641  size_t n;
642  NetRxAncillary ancillary;
643 
644  //The current buffer is available for reading?
645  if((rxCurDmaDesc->rdes0 & EMAC_RDES0_OWN) == 0)
646  {
647  //FS and LS flags should be set
648  if((rxCurDmaDesc->rdes0 & EMAC_RDES0_FS) != 0 &&
649  (rxCurDmaDesc->rdes0 & EMAC_RDES0_LS) != 0)
650  {
651  //Make sure no error occurred
652  if((rxCurDmaDesc->rdes0 & EMAC_RDES0_ES) == 0)
653  {
654  //Retrieve the length of the frame
655  n = (rxCurDmaDesc->rdes0 & EMAC_RDES0_FL) >> 16;
656  //Limit the number of data to read
658 
659  //Additional options can be passed to the stack along with the packet
660  ancillary = NET_DEFAULT_RX_ANCILLARY;
661 
662  //Pass the packet to the upper layer
663  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n,
664  &ancillary);
665 
666  //Valid packet received
667  error = NO_ERROR;
668  }
669  else
670  {
671  //The received packet contains an error
672  error = ERROR_INVALID_PACKET;
673  }
674  }
675  else
676  {
677  //The packet is not valid
678  error = ERROR_INVALID_PACKET;
679  }
680 
681  //Give the ownership of the descriptor back to the DMA
682  rxCurDmaDesc->rdes0 = EMAC_RDES0_OWN;
683  //Point to the next descriptor in the list
684  rxCurDmaDesc = (Tm4c129RxDmaDesc *) rxCurDmaDesc->rdes3;
685  }
686  else
687  {
688  //No more data in the receive buffer
689  error = ERROR_BUFFER_EMPTY;
690  }
691 
692  //Clear RU flag to resume processing
693  EMAC0_DMARIS_R = EMAC_DMARIS_RU;
694  //Instruct the DMA to poll the receive descriptor list
695  EMAC0_RXPOLLD_R = 0;
696 
697  //Return status code
698  return error;
699 }
700 
701 
702 /**
703  * @brief Configure MAC address filtering
704  * @param[in] interface Underlying network interface
705  * @return Error code
706  **/
707 
709 {
710  uint_t i;
711  uint_t j;
712  uint_t k;
713  uint32_t crc;
714  uint32_t hashTable[2];
715  MacAddr unicastMacAddr[3];
716  MacFilterEntry *entry;
717 
718  //Debug message
719  TRACE_DEBUG("Updating MAC filter...\r\n");
720 
721  //Set the MAC address of the station
722  EMAC0_ADDR0L_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
723  EMAC0_ADDR0H_R = interface->macAddr.w[2];
724 
725  //The MAC supports 3 additional addresses for unicast perfect filtering
726  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
727  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
728  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
729 
730  //The hash table is used for multicast address filtering
731  hashTable[0] = 0;
732  hashTable[1] = 0;
733 
734  //The MAC address filter contains the list of MAC addresses to accept
735  //when receiving an Ethernet frame
736  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
737  {
738  //Point to the current entry
739  entry = &interface->macAddrFilter[i];
740 
741  //Valid entry?
742  if(entry->refCount > 0)
743  {
744  //Multicast address?
745  if(macIsMulticastAddr(&entry->addr))
746  {
747  //Compute CRC over the current MAC address
748  crc = tm4c129EthCalcCrc(&entry->addr, sizeof(MacAddr));
749 
750  //The upper 6 bits in the CRC register are used to index the
751  //contents of the hash table
752  k = (crc >> 26) & 0x3F;
753 
754  //Update hash table contents
755  hashTable[k / 32] |= (1 << (k % 32));
756  }
757  else
758  {
759  //Up to 3 additional MAC addresses can be specified
760  if(j < 3)
761  {
762  //Save the unicast address
763  unicastMacAddr[j++] = entry->addr;
764  }
765  }
766  }
767  }
768 
769  //Configure the first unicast address filter
770  if(j >= 1)
771  {
772  //When the AE bit is set, the entry is used for perfect filtering
773  EMAC0_ADDR1L_R = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
774  EMAC0_ADDR1H_R = unicastMacAddr[0].w[2] | EMAC_ADDR1H_AE;
775  }
776  else
777  {
778  //When the AE bit is cleared, the entry is ignored
779  EMAC0_ADDR1L_R = 0;
780  EMAC0_ADDR1H_R = 0;
781  }
782 
783  //Configure the second unicast address filter
784  if(j >= 2)
785  {
786  //When the AE bit is set, the entry is used for perfect filtering
787  EMAC0_ADDR2L_R = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
788  EMAC0_ADDR2H_R = unicastMacAddr[1].w[2] | EMAC_ADDR2H_AE;
789  }
790  else
791  {
792  //When the AE bit is cleared, the entry is ignored
793  EMAC0_ADDR2L_R = 0;
794  EMAC0_ADDR2H_R = 0;
795  }
796 
797  //Configure the third unicast address filter
798  if(j >= 3)
799  {
800  //When the AE bit is set, the entry is used for perfect filtering
801  EMAC0_ADDR3L_R = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
802  EMAC0_ADDR3H_R = unicastMacAddr[2].w[2] | EMAC_ADDR3H_AE;
803  }
804  else
805  {
806  //When the AE bit is cleared, the entry is ignored
807  EMAC0_ADDR3L_R = 0;
808  EMAC0_ADDR3H_R = 0;
809  }
810 
811  //Configure the multicast address filter
812  EMAC0_HASHTBLL_R = hashTable[0];
813  EMAC0_HASHTBLH_R = hashTable[1];
814 
815  //Debug message
816  TRACE_DEBUG(" HASHTBLL = %08" PRIX32 "\r\n", EMAC0_HASHTBLL_R);
817  TRACE_DEBUG(" HASHTBLH = %08" PRIX32 "\r\n", EMAC0_HASHTBLH_R);
818 
819  //Successful processing
820  return NO_ERROR;
821 }
822 
823 
824 /**
825  * @brief Write PHY register
826  * @param[in] regAddr Register address
827  * @param[in] data Register value
828  **/
829 
830 void tm4c129EthWritePhyReg(uint8_t regAddr, uint16_t data)
831 {
832  uint32_t temp;
833 
834  //Take care not to alter MDC clock configuration
835  temp = EMAC0_MIIADDR_R & EMAC_MIIADDR_CR_M;
836  //Set up a write operation
837  temp |= EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
838  //The address of the integrated PHY is 0
839  temp |= (0 << EMAC_MIIADDR_PLA_S) & EMAC_MIIADDR_PLA_M;
840  //Register address
841  temp |= (regAddr << EMAC_MIIADDR_MII_S) & EMAC_MIIADDR_MII_M;
842 
843  //Data to be written in the PHY register
844  EMAC0_MIIDATA_R = data & EMAC_MIIDATA_DATA_M;
845 
846  //Start a write operation
847  EMAC0_MIIADDR_R = temp;
848  //Wait for the write to complete
849  while((EMAC0_MIIADDR_R & EMAC_MIIADDR_MIIB) != 0)
850  {
851  }
852 }
853 
854 
855 /**
856  * @brief Read PHY register
857  * @param[in] regAddr Register address
858  * @return Register value
859  **/
860 
861 uint16_t tm4c129EthReadPhyReg(uint8_t regAddr)
862 {
863  uint32_t temp;
864 
865  //Take care not to alter MDC clock configuration
866  temp = EMAC0_MIIADDR_R & EMAC_MIIADDR_CR_M;
867  //Set up a read operation
868  temp |= EMAC_MIIADDR_MIIB;
869  //The address of the integrated PHY is 0
870  temp |= (0 << EMAC_MIIADDR_PLA_S) & EMAC_MIIADDR_PLA_M;
871  //Register address
872  temp |= (regAddr << EMAC_MIIADDR_MII_S) & EMAC_MIIADDR_MII_M;
873 
874  //Start a read operation
875  EMAC0_MIIADDR_R = temp;
876  //Wait for the read to complete
877  while((EMAC0_MIIADDR_R & EMAC_MIIADDR_MIIB) != 0)
878  {
879  }
880 
881  //Return PHY register contents
882  return EMAC0_MIIDATA_R & EMAC_MIIDATA_DATA_M;
883 }
884 
885 
886 /**
887  * @brief Dump PHY registers for debugging purpose
888  **/
889 
891 {
892  uint8_t i;
893 
894  //Loop through PHY registers
895  for(i = 0; i < 32; i++)
896  {
897  //Display current PHY register
898  TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i,
900  }
901 
902  //Terminate with a line feed
903  TRACE_DEBUG("\r\n");
904 }
905 
906 
907 /**
908  * @brief CRC calculation
909  * @param[in] data Pointer to the data over which to calculate the CRC
910  * @param[in] length Number of bytes to process
911  * @return Resulting CRC value
912  **/
913 
914 uint32_t tm4c129EthCalcCrc(const void *data, size_t length)
915 {
916  uint_t i;
917  uint_t j;
918  uint32_t crc;
919  const uint8_t *p;
920 
921  //Point to the data over which to calculate the CRC
922  p = (uint8_t *) data;
923  //CRC preset value
924  crc = 0xFFFFFFFF;
925 
926  //Loop through data
927  for(i = 0; i < length; i++)
928  {
929  //The message is processed bit by bit
930  for(j = 0; j < 8; j++)
931  {
932  //Update CRC value
933  if((((crc >> 31) ^ (p[i] >> j)) & 0x01) != 0)
934  {
935  crc = (crc << 1) ^ 0x04C11DB7;
936  }
937  else
938  {
939  crc = crc << 1;
940  }
941  }
942  }
943 
944  //Return CRC value
945  return ~crc;
946 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:532
uint8_t length
Definition: coap_common.h:190
#define EMAC_TDES0_OWN
int bool_t
Definition: compiler_port.h:49
error_t tm4c129EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define netEvent
Definition: net_legacy.h:267
void tm4c129EthWritePhyReg(uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t data[]
Definition: ethernet.h:209
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
Enhanced TX DMA descriptor.
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void tm4c129EthDumpPhyReg(void)
Dump PHY registers for debugging purpose.
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define EMAC_TDES0_TCH
__start_packed struct @5 MacAddr
MAC address.
#define TM4C129_ETH_RX_BUFFER_COUNT
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define EMAC_RDES0_FL
uint16_t tm4c129EthReadPhyReg(uint8_t regAddr)
Read PHY register.
#define EMAC_DMABUSMOD_RPBL_1
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define osExitIsr(flag)
error_t tm4c129EthReceivePacket(NetInterface *interface)
Receive a packet.
void tm4c129EthEnableIrq(NetInterface *interface)
Enable interrupts.
void tm4c129EthInitGpio(NetInterface *interface)
Tiva TM4C129 Ethernet controller.
#define EMAC_RDES0_OWN
#define EMAC_TDES0_IC
#define FALSE
Definition: os_port.h:46
#define EMAC_TDES0_FS
error_t
Error codes.
Definition: error.h:42
void tm4c129EthTick(NetInterface *interface)
TM4C129 Ethernet MAC timer handler.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define EMAC_RDES0_FS
#define NetTxAncillary
Definition: net_misc.h:36
void tm4c129EthEventHandler(NetInterface *interface)
TM4C129 Ethernet MAC event handler.
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
#define EMAC_TDES0_LS
#define rxBuffer
uint32_t tm4c129EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define EMAC_RDES0_LS
#define TM4C129_ETH_TX_BUFFER_COUNT
#define EMAC_TDES1_TBS1
void tm4c129EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TM4C129_ETH_RX_BUFFER_SIZE
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
#define EMAC_RDES1_RCH
MAC filter table entry.
Definition: ethernet.h:246
error_t tm4c129EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define TM4C129_ETH_IRQ_PRIORITY
#define EMAC_DMABUSMOD_PBL_1
#define osEnterIsr()
const NicDriver tm4c129EthDriver
Tiva TM4C129 Ethernet MAC driver.
#define EMAC_DMABUSMOD_PR_1_1
void EMAC0_Handler(void)
TM4C129 Ethernet MAC interrupt service routine.
#define rxDmaDesc
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define txDmaDesc
#define TM4C129_ETH_IRQ_PRIORITY_GROUPING
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
Enhanced RX DMA descriptor.
void tm4c129EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t tm4c129EthInit(NetInterface *interface)
Tiva TM4C129 Ethernet MAC initialization.
#define EMAC_RDES0_ES
#define EMAC_RDES1_RBS1
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
Ethernet interface.
Definition: nic.h:82
#define TM4C129_ETH_TX_BUFFER_SIZE