a2fxxxm3_eth_driver.c
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1 /**
2  * @file a2fxxxm3_eth_driver.c
3  * @brief SmartFusion (A2FxxxM3) Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "a2fxxxm3.h"
36 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_regs_driver.h"
37 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_desc_driver.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //Transmit buffer
49 #pragma data_alignment = 4
51 //Receive buffer
52 #pragma data_alignment = 4
54 //Transmit DMA descriptors
55 #pragma data_alignment = 4
57 //Receive DMA descriptors
58 #pragma data_alignment = 4
60 
61 //Keil MDK-ARM or GCC compiler?
62 #else
63 
64 //Transmit buffer
66  __attribute__((aligned(4)));
67 //Receive buffer
69  __attribute__((aligned(4)));
70 //Transmit DMA descriptors
72  __attribute__((aligned(4)));
73 //Receive DMA descriptors
75  __attribute__((aligned(4)));
76 
77 #endif
78 
79 //Pointer to the current TX DMA descriptor
80 static A2fxxxm3TxDmaDesc *txCurDmaDesc;
81 //Pointer to the current RX DMA descriptor
82 static A2fxxxm3RxDmaDesc *rxCurDmaDesc;
83 
84 
85 /**
86  * @brief A2FxxxM3 Ethernet MAC driver
87  **/
88 
90 {
92  ETH_MTU,
103  TRUE,
104  TRUE,
105  TRUE,
106  FALSE
107 };
108 
109 
110 /**
111  * @brief A2FxxxM3 Ethernet MAC initialization
112  * @param[in] interface Underlying network interface
113  * @return Error code
114  **/
115 
117 {
118  error_t error;
119 
120  //Debug message
121  TRACE_INFO("Initializing A2FxxxM3 Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Perform a software reset
127  MAC->CSR0 |= CSR0_SWR_MASK;
128  //Wait for the reset to complete
129  while((MAC->CSR0 & CSR0_SWR_MASK) != 0)
130  {
131  }
132 
133  //Valid Ethernet PHY or switch driver?
134  if(interface->phyDriver != NULL)
135  {
136  //Ethernet PHY initialization
137  error = interface->phyDriver->init(interface);
138  }
139  else if(interface->switchDriver != NULL)
140  {
141  //Ethernet switch initialization
142  error = interface->switchDriver->init(interface);
143  }
144  else
145  {
146  //The interface is not properly configured
147  error = ERROR_FAILURE;
148  }
149 
150  //Any error to report?
151  if(error)
152  {
153  return error;
154  }
155 
156  //Enable store and forward mode
157  MAC->CSR6 |= CSR6_SF_MASK;
158 
159  //Initialize DMA descriptor lists
160  a2fxxxm3EthInitDmaDesc(interface);
161 
162  //Enable the desired Ethernet interrupts
163  MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
164 
165  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
166  NVIC_SetPriorityGrouping(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING);
167 
168  //Configure Ethernet interrupt priority
169  NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING,
171 
172  //Enable transmission and reception
173  MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
174 
175  //Set MAC address
176  error = a2fxxxm3EthSendSetup(interface);
177  //Any error to report?
178  if(error)
179  {
180  return error;
181  }
182 
183  //Accept any packets from the upper layer
184  osSetEvent(&interface->nicTxEvent);
185 
186  //Successful initialization
187  return NO_ERROR;
188 }
189 
190 
191 /**
192  * @brief Initialize DMA descriptor lists
193  * @param[in] interface Underlying network interface
194  **/
195 
197 {
198  uint_t i;
199 
200  //Initialize TX DMA descriptor list
201  for(i = 0; i < A2FXXXM3_ETH_TX_BUFFER_COUNT; i++)
202  {
203  //The descriptor is initially owned by the user
204  txDmaDesc[i].tdes0 = 0;
205  //Use chain structure rather than ring structure
206  txDmaDesc[i].tdes1 = TDES1_TCH;
207  //Transmit buffer address
208  txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
209  //Next descriptor address
210  txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
211  }
212 
213  //The last descriptor is chained to the first entry
214  txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
215  //Point to the very first descriptor
216  txCurDmaDesc = &txDmaDesc[0];
217 
218  //Initialize RX DMA descriptor list
219  for(i = 0; i < A2FXXXM3_ETH_RX_BUFFER_COUNT; i++)
220  {
221  //The descriptor is initially owned by the DMA
222  rxDmaDesc[i].rdes0 = RDES0_OWN;
223  //Use chain structure rather than ring structure
224  rxDmaDesc[i].rdes1 = RDES1_RCH | (A2FXXXM3_ETH_RX_BUFFER_SIZE & RDES1_RBS1_MASK);
225  //Receive buffer address
226  rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
227  //Next descriptor address
228  rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
229  }
230 
231  //The last descriptor is chained to the first entry
232  rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
233  //Point to the very first descriptor
234  rxCurDmaDesc = &rxDmaDesc[0];
235 
236  //Start location of the TX descriptor list
237  MAC->CSR4 = (uint32_t) txDmaDesc;
238  //Start location of the RX descriptor list
239  MAC->CSR3 = (uint32_t) rxDmaDesc;
240 }
241 
242 
243 /**
244  * @brief A2FxxxM3 Ethernet MAC timer handler
245  *
246  * This routine is periodically called by the TCP/IP stack to handle periodic
247  * operations such as polling the link state
248  *
249  * @param[in] interface Underlying network interface
250  **/
251 
253 {
254  //Valid Ethernet PHY or switch driver?
255  if(interface->phyDriver != NULL)
256  {
257  //Handle periodic operations
258  interface->phyDriver->tick(interface);
259  }
260  else if(interface->switchDriver != NULL)
261  {
262  //Handle periodic operations
263  interface->switchDriver->tick(interface);
264  }
265  else
266  {
267  //Just for sanity
268  }
269 }
270 
271 
272 /**
273  * @brief Enable interrupts
274  * @param[in] interface Underlying network interface
275  **/
276 
278 {
279  //Enable Ethernet MAC interrupts
280  NVIC_EnableIRQ(EthernetMAC_IRQn);
281 
282  //Valid Ethernet PHY or switch driver?
283  if(interface->phyDriver != NULL)
284  {
285  //Enable Ethernet PHY interrupts
286  interface->phyDriver->enableIrq(interface);
287  }
288  else if(interface->switchDriver != NULL)
289  {
290  //Enable Ethernet switch interrupts
291  interface->switchDriver->enableIrq(interface);
292  }
293  else
294  {
295  //Just for sanity
296  }
297 }
298 
299 
300 /**
301  * @brief Disable interrupts
302  * @param[in] interface Underlying network interface
303  **/
304 
306 {
307  //Disable Ethernet MAC interrupts
308  NVIC_DisableIRQ(EthernetMAC_IRQn);
309 
310  //Valid Ethernet PHY or switch driver?
311  if(interface->phyDriver != NULL)
312  {
313  //Disable Ethernet PHY interrupts
314  interface->phyDriver->disableIrq(interface);
315  }
316  else if(interface->switchDriver != NULL)
317  {
318  //Disable Ethernet switch interrupts
319  interface->switchDriver->disableIrq(interface);
320  }
321  else
322  {
323  //Just for sanity
324  }
325 }
326 
327 
328 /**
329  * @brief A2FxxxM3 Ethernet MAC interrupt service routine
330  **/
331 
333 {
334  bool_t flag;
335  uint32_t status;
336 
337  //Interrupt service routine prologue
338  osEnterIsr();
339 
340  //This flag will be set if a higher priority task must be woken
341  flag = FALSE;
342 
343  //Read interrupt status register
344  status = MAC->CSR5;
345 
346  //Packet transmitted?
347  if((status & CSR5_TI_MASK) != 0)
348  {
349  //Clear TI interrupt flag
350  MAC->CSR5 = CSR5_TI_MASK;
351 
352  //Check whether the TX buffer is available for writing
353  if((txCurDmaDesc->tdes0 & TDES0_OWN) == 0)
354  {
355  //Notify the TCP/IP stack that the transmitter is ready to send
356  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
357  }
358  }
359 
360  //Packet received?
361  if((status & CSR5_RI_MASK) != 0)
362  {
363  //Disable RIE interrupt
364  MAC->CSR7 &= ~CSR7_RIE_MASK;
365 
366  //Set event flag
367  nicDriverInterface->nicEvent = TRUE;
368  //Notify the TCP/IP stack of the event
369  flag |= osSetEventFromIsr(&netEvent);
370  }
371 
372  //Clear NIS interrupt flag
373  MAC->CSR5 = CSR5_NIS_MASK;
374 
375  //Interrupt service routine epilogue
376  osExitIsr(flag);
377 }
378 
379 
380 /**
381  * @brief A2FxxxM3 Ethernet MAC event handler
382  * @param[in] interface Underlying network interface
383  **/
384 
386 {
387  error_t error;
388 
389  //Packet received?
390  if((MAC->CSR5 & CSR5_RI_MASK) != 0)
391  {
392  //Clear interrupt flag
393  MAC->CSR5 = CSR5_RI_MASK;
394 
395  //Process all pending packets
396  do
397  {
398  //Read incoming packet
399  error = a2fxxxm3EthReceivePacket(interface);
400 
401  //No more data in the receive buffer?
402  } while(error != ERROR_BUFFER_EMPTY);
403  }
404 
405  //Re-enable Ethernet interrupts
406  MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
407 }
408 
409 
410 /**
411  * @brief Send a setup frame
412  * @param[in] interface Underlying network interface
413  * @return Error code
414  **/
415 
417 {
418  A2fxxxm3HashTableSetupFrame *setupFrame;
419 
420  //Make sure the current buffer is available for writing
421  if((txCurDmaDesc->tdes0 & TDES0_OWN) != 0)
422  {
423  return ERROR_FAILURE;
424  }
425 
426  //Point to the buffer where to format the setup frame
427  setupFrame = (A2fxxxm3HashTableSetupFrame *) txCurDmaDesc->tdes2;
428 
429  //Clear contents
430  osMemset(setupFrame, 0, sizeof(A2fxxxm3HashTableSetupFrame));
431 
432  //Set MAC address
433  setupFrame->physicalAddr[0] = interface->macAddr.w[0];
434  setupFrame->physicalAddr[1] = interface->macAddr.w[1];
435  setupFrame->physicalAddr[2] = interface->macAddr.w[2];
436 
437  //Write the number of bytes to send
438  txCurDmaDesc->tdes1 = sizeof(A2fxxxm3HashTableSetupFrame) & TDES1_TBS1_MASK;
439  //The SET flag indicates that this is a setup frame descriptor
440  txCurDmaDesc->tdes1 |= TDES1_SET | TDES1_TCH | TDES1_FT0;
441  //Give the ownership of the descriptor to the DMA
442  txCurDmaDesc->tdes0 |= TDES0_OWN;
443 
444  //Instruct the DMA to poll the transmit descriptor list
445  MAC->CSR1 = 1;
446 
447  //Point to the next descriptor in the list
448  txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
449 
450  //Data successfully written
451  return NO_ERROR;
452 }
453 
454 
455 /**
456  * @brief Send a packet
457  * @param[in] interface Underlying network interface
458  * @param[in] buffer Multi-part buffer containing the data to send
459  * @param[in] offset Offset to the first data byte
460  * @param[in] ancillary Additional options passed to the stack along with
461  * the packet
462  * @return Error code
463  **/
464 
466  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
467 {
468  size_t length;
469 
470  //Retrieve the length of the packet
471  length = netBufferGetLength(buffer) - offset;
472 
473  //Check the frame length
475  {
476  //The transmitter can accept another packet
477  osSetEvent(&interface->nicTxEvent);
478  //Report an error
479  return ERROR_INVALID_LENGTH;
480  }
481 
482  //Make sure the current buffer is available for writing
483  if((txCurDmaDesc->tdes0 & TDES0_OWN) != 0)
484  {
485  return ERROR_FAILURE;
486  }
487 
488  //Copy user data to the transmit buffer
489  netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
490 
491  //Write the number of bytes to send
492  txCurDmaDesc->tdes1 = length & TDES1_TBS1_MASK;
493  //Set LS and FS flags as the data fits in a single buffer
494  txCurDmaDesc->tdes1 |= TDES1_IC | TDES1_LS | TDES1_FS | TDES1_TCH;
495  //Give the ownership of the descriptor to the DMA
496  txCurDmaDesc->tdes0 |= TDES0_OWN;
497 
498  //Instruct the DMA to poll the transmit descriptor list
499  MAC->CSR1 = 1;
500 
501  //Point to the next descriptor in the list
502  txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
503 
504  //Check whether the next buffer is available for writing
505  if((txCurDmaDesc->tdes0 & TDES0_OWN) == 0)
506  {
507  //The transmitter can accept another packet
508  osSetEvent(&interface->nicTxEvent);
509  }
510 
511  //Data successfully written
512  return NO_ERROR;
513 }
514 
515 
516 /**
517  * @brief Receive a packet
518  * @param[in] interface Underlying network interface
519  * @return Error code
520  **/
521 
523 {
524  error_t error;
525  size_t n;
526  NetRxAncillary ancillary;
527 
528  //The current buffer is available for reading?
529  if((rxCurDmaDesc->rdes0 & RDES0_OWN) == 0)
530  {
531  //FS and LS flags should be set
532  if((rxCurDmaDesc->rdes0 & RDES0_FS) != 0 &&
533  (rxCurDmaDesc->rdes0 & RDES0_LS) != 0)
534  {
535  //Make sure no error occurred
536  if((rxCurDmaDesc->rdes0 & RDES0_ES) == 0)
537  {
538  //Retrieve the length of the frame
539  n = (rxCurDmaDesc->rdes0 >> RDES0_FL_OFFSET) & RDES0_FL_MASK;
540  //Limit the number of data to read
542 
543  //Additional options can be passed to the stack along with the packet
544  ancillary = NET_DEFAULT_RX_ANCILLARY;
545 
546  //Pass the packet to the upper layer
547  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n,
548  &ancillary);
549 
550  //Valid packet received
551  error = NO_ERROR;
552  }
553  else
554  {
555  //The received packet contains an error
556  error = ERROR_INVALID_PACKET;
557  }
558  }
559  else
560  {
561  //The packet is not valid
562  error = ERROR_INVALID_PACKET;
563  }
564 
565  //Give the ownership of the descriptor back to the DMA
566  rxCurDmaDesc->rdes0 = RDES0_OWN;
567  //Point to the next descriptor in the list
568  rxCurDmaDesc = (A2fxxxm3RxDmaDesc *) rxCurDmaDesc->rdes3;
569  }
570  else
571  {
572  //No more data in the receive buffer
573  error = ERROR_BUFFER_EMPTY;
574  }
575 
576  //Instruct the DMA to poll the receive descriptor list
577  MAC->CSR2 = 1;
578 
579  //Return status code
580  return error;
581 }
582 
583 
584 /**
585  * @brief Configure MAC address filtering
586  * @param[in] interface Underlying network interface
587  * @return Error code
588  **/
589 
591 {
592  uint_t i;
593  bool_t acceptMulticast;
594 
595  //This flag will be set if multicast addresses should be accepted
596  acceptMulticast = FALSE;
597 
598  //The MAC address filter contains the list of MAC addresses to accept
599  //when receiving an Ethernet frame
600  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
601  {
602  //Valid entry?
603  if(interface->macAddrFilter[i].refCount > 0)
604  {
605  //Accept multicast addresses
606  acceptMulticast = TRUE;
607  //We are done
608  break;
609  }
610  }
611 
612  //Enable the reception of multicast frames if necessary
613  if(acceptMulticast)
614  {
615  MAC->CSR6 |= CSR6_PM_MASK;
616  }
617  else
618  {
619  MAC->CSR6 &= ~CSR6_PM_MASK;
620  }
621 
622  //Successful processing
623  return NO_ERROR;
624 }
625 
626 
627 /**
628  * @brief Adjust MAC configuration parameters for proper operation
629  * @param[in] interface Underlying network interface
630  * @return Error code
631  **/
632 
634 {
635  //Stop transmission
636  while(((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) != CSR5_TS_STOPPED)
637  MAC->CSR6 &= ~CSR6_ST_MASK;
638 
639  //Stop reception
640  while(((MAC->CSR5 & CSR5_RS_MASK) >> CSR5_RS_SHIFT) != CSR5_RS_STOPPED)
641  MAC->CSR6 &= ~CSR6_SR_MASK;
642 
643  //10BASE-T or 100BASE-TX operation mode?
644  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
645  {
646  MAC->CSR6 |= CSR6_TTM_MASK;
647  }
648  else
649  {
650  MAC->CSR6 &= ~CSR6_TTM_MASK;
651  }
652 
653  //Half-duplex or full-duplex mode?
654  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
655  {
656  MAC->CSR6 |= CSR6_FD_MASK;
657  }
658  else
659  {
660  MAC->CSR6 &= ~CSR6_FD_MASK;
661  }
662 
663  //Restart transmission and reception
664  MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
665 
666  //Successful processing
667  return NO_ERROR;
668 }
669 
670 
671 /**
672  * @brief Write PHY register
673  * @param[in] opcode Access type (2 bits)
674  * @param[in] phyAddr PHY address (5 bits)
675  * @param[in] regAddr Register address (5 bits)
676  * @param[in] data Register value
677  **/
678 
679 void a2fxxxm3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
680  uint8_t regAddr, uint16_t data)
681 {
682  //Synchronization pattern
684  //Start of frame
686  //Set up a write operation
688  //Write PHY address
689  a2fxxxm3EthWriteSmi(phyAddr, 5);
690  //Write register address
692  //Turnaround
694  //Write register value
696  //Release MDIO
698 }
699 
700 
701 /**
702  * @brief Read PHY register
703  * @param[in] opcode Access type (2 bits)
704  * @param[in] phyAddr PHY address (5 bits)
705  * @param[in] regAddr Register address (5 bits)
706  * @return Register value
707  **/
708 
709 uint16_t a2fxxxm3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
710  uint8_t regAddr)
711 {
712  uint16_t data;
713 
714  //Synchronization pattern
716  //Start of frame
718  //Set up a read operation
720  //Write PHY address
721  a2fxxxm3EthWriteSmi(phyAddr, 5);
722  //Write register address
724  //Turnaround to avoid contention
726  //Read register value
727  data = a2fxxxm3EthReadSmi(16);
728  //Force the PHY to release the MDIO pin
730 
731  //Return PHY register contents
732  return data;
733 }
734 
735 
736 /**
737  * @brief SMI write operation
738  * @param[in] data Raw data to be written
739  * @param[in] length Number of bits to be written
740  **/
741 
743 {
744  //Skip the most significant bits since they are meaningless
745  data <<= 32 - length;
746 
747  //Configure MDIO as an output
748  MAC->CSR9 |= CSR9_MDEN_MASK;
749 
750  //Write the specified number of bits
751  while(length--)
752  {
753  //Write MDIO
754  if((data & 0x80000000) != 0)
755  {
756  MAC->CSR9 |= CSR9_MDO_MASK;
757  }
758  else
759  {
760  MAC->CSR9 &= ~CSR9_MDO_MASK;
761  }
762 
763  //Assert MDC
764  usleep(1);
765  MAC->CSR9 |= CSR9_MDC_MASK;
766  //Deassert MDC
767  usleep(1);
768  MAC->CSR9 &= ~CSR9_MDC_MASK;
769 
770  //Rotate data
771  data <<= 1;
772  }
773 }
774 
775 
776 /**
777  * @brief SMI read operation
778  * @param[in] length Number of bits to be read
779  * @return Data resulting from the MDIO read operation
780  **/
781 
783 {
784  uint32_t data = 0;
785 
786  //Configure MDIO as an input
787  MAC->CSR9 &= ~CSR9_MDEN_MASK;
788 
789  //Read the specified number of bits
790  while(length--)
791  {
792  //Rotate data
793  data <<= 1;
794 
795  //Assert MDC
796  MAC->CSR9 |= CSR9_MDC_MASK;
797  usleep(1);
798  //Deassert MDC
799  MAC->CSR9 &= ~CSR9_MDC_MASK;
800  usleep(1);
801 
802  //Check MDIO state
803  if((MAC->CSR9 & CSR9_MDI_MASK) != 0)
804  {
805  data |= 0x01;
806  }
807  }
808 
809  //Return the received data
810  return data;
811 }
812 
813 
814 /**
815  * @brief CRC calculation
816  * @param[in] data Pointer to the data over which to calculate the CRC
817  * @param[in] length Number of bytes to process
818  * @return Resulting CRC value
819  **/
820 
821 uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
822 {
823  uint_t i;
824  uint_t j;
825  uint32_t crc;
826  const uint8_t *p;
827 
828  //Point to the data over which to calculate the CRC
829  p = (uint8_t *) data;
830  //CRC preset value
831  crc = 0xFFFFFFFF;
832 
833  //Loop through data
834  for(i = 0; i < length; i++)
835  {
836  //Update CRC value
837  crc ^= p[i];
838 
839  //The message is processed bit by bit
840  for(j = 0; j < 8; j++)
841  {
842  //Update CRC value
843  if((crc & 0x01) != 0)
844  {
845  crc = (crc >> 1) ^ 0xEDB88320;
846  }
847  else
848  {
849  crc = crc >> 1;
850  }
851  }
852  }
853 
854  //Return CRC value
855  return crc;
856 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
#define usleep(delay)
Definition: os_port.h:247
void EthernetMAC_IRQHandler(void)
A2FxxxM3 Ethernet MAC interrupt service routine.
uint8_t opcode
Definition: dns_common.h:172
error_t a2fxxxm3EthReceivePacket(NetInterface *interface)
Receive a packet.
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define A2FXXXM3_ETH_IRQ_SUB_PRIORITY
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
void a2fxxxm3EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define SMI_TA
Definition: nic.h:67
error_t a2fxxxm3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void a2fxxxm3EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define SMI_START
Definition: nic.h:63
uint32_t a2fxxxm3EthReadSmi(uint_t length)
SMI read operation.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define osExitIsr(flag)
#define A2FXXXM3_ETH_TX_BUFFER_SIZE
void a2fxxxm3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define FALSE
Definition: os_port.h:46
error_t
Error codes.
Definition: error.h:42
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
error_t a2fxxxm3EthSendSetup(NetInterface *interface)
Send a setup frame.
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
uint16_t a2fxxxm3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
const NicDriver a2fxxxm3EthDriver
A2FxxxM3 Ethernet MAC driver.
void a2fxxxm3EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
#define A2FXXXM3_ETH_RX_BUFFER_SIZE
#define A2FXXXM3_ETH_RX_BUFFER_COUNT
uint16_t regAddr
void a2fxxxm3EthEventHandler(NetInterface *interface)
A2FxxxM3 Ethernet MAC event handler.
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
#define osEnterIsr()
Transmit DMA descriptor.
SmartFusion (A2FxxxM3) Ethernet MAC driver.
Hash table setup frame.
#define rxDmaDesc
uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
CRC calculation.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define txDmaDesc
void a2fxxxm3EthTick(NetInterface *interface)
A2FxxxM3 Ethernet MAC timer handler.
#define SMI_SYNC
Definition: nic.h:62
unsigned int uint_t
Definition: compiler_port.h:45
#define osMemset(p, value, length)
Definition: os_port.h:128
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
#define CSR9_MDEN_MASK
void a2fxxxm3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t a2fxxxm3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING
error_t a2fxxxm3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t a2fxxxm3EthInit(NetInterface *interface)
A2FxxxM3 Ethernet MAC initialization.
Receive DMA descriptor.
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define A2FXXXM3_ETH_IRQ_GROUP_PRIORITY
Ethernet interface.
Definition: nic.h:82
#define A2FXXXM3_ETH_TX_BUFFER_COUNT