a2fxxxm3_eth_driver.c
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1 /**
2  * @file a2fxxxm3_eth_driver.c
3  * @brief SmartFusion (A2FxxxM3) Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "a2fxxxm3.h"
36 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_regs_driver.h"
37 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_desc_driver.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //Transmit buffer
49 #pragma data_alignment = 4
51 //Receive buffer
52 #pragma data_alignment = 4
54 //Transmit DMA descriptors
55 #pragma data_alignment = 4
57 //Receive DMA descriptors
58 #pragma data_alignment = 4
60 
61 //Keil MDK-ARM or GCC compiler?
62 #else
63 
64 //Transmit buffer
66  __attribute__((aligned(4)));
67 //Receive buffer
69  __attribute__((aligned(4)));
70 //Transmit DMA descriptors
72  __attribute__((aligned(4)));
73 //Receive DMA descriptors
75  __attribute__((aligned(4)));
76 
77 #endif
78 
79 //Pointer to the current TX DMA descriptor
80 static A2fxxxm3TxDmaDesc *txCurDmaDesc;
81 //Pointer to the current RX DMA descriptor
82 static A2fxxxm3RxDmaDesc *rxCurDmaDesc;
83 
84 
85 /**
86  * @brief A2FxxxM3 Ethernet MAC driver
87  **/
88 
90 {
92  ETH_MTU,
103  TRUE,
104  TRUE,
105  TRUE,
106  FALSE
107 };
108 
109 
110 /**
111  * @brief A2FxxxM3 Ethernet MAC initialization
112  * @param[in] interface Underlying network interface
113  * @return Error code
114  **/
115 
117 {
118  error_t error;
119 
120  //Debug message
121  TRACE_INFO("Initializing A2FxxxM3 Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Perform a software reset
127  MAC->CSR0 |= CSR0_SWR_MASK;
128  //Wait for the reset to complete
129  while(MAC->CSR0 & CSR0_SWR_MASK)
130  {
131  }
132 
133  //PHY transceiver initialization
134  error = interface->phyDriver->init(interface);
135  //Failed to initialize PHY transceiver?
136  if(error)
137  return error;
138 
139  //Enable store and forward mode
140  MAC->CSR6 |= CSR6_SF_MASK;
141 
142  //Initialize DMA descriptor lists
143  a2fxxxm3EthInitDmaDesc(interface);
144 
145  //Enable the desired Ethernet interrupts
146  MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
147 
148  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
149  NVIC_SetPriorityGrouping(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING);
150 
151  //Configure Ethernet interrupt priority
152  NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING,
154 
155  //Enable transmission and reception
156  MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
157 
158  //Set MAC address
159  error = a2fxxxm3EthSendSetup(interface);
160  //Any error to report?
161  if(error)
162  return error;
163 
164  //Accept any packets from the upper layer
165  osSetEvent(&interface->nicTxEvent);
166 
167  //Successful initialization
168  return NO_ERROR;
169 }
170 
171 
172 /**
173  * @brief Initialize DMA descriptor lists
174  * @param[in] interface Underlying network interface
175  **/
176 
178 {
179  uint_t i;
180 
181  //Initialize TX DMA descriptor list
182  for(i = 0; i < A2FXXXM3_ETH_TX_BUFFER_COUNT; i++)
183  {
184  //The descriptor is initially owned by the user
185  txDmaDesc[i].tdes0 = 0;
186  //Use chain structure rather than ring structure
187  txDmaDesc[i].tdes1 = TDES1_TCH;
188  //Transmit buffer address
189  txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
190  //Next descriptor address
191  txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
192  }
193 
194  //The last descriptor is chained to the first entry
195  txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
196  //Point to the very first descriptor
197  txCurDmaDesc = &txDmaDesc[0];
198 
199  //Initialize RX DMA descriptor list
200  for(i = 0; i < A2FXXXM3_ETH_RX_BUFFER_COUNT; i++)
201  {
202  //The descriptor is initially owned by the DMA
203  rxDmaDesc[i].rdes0 = RDES0_OWN;
204  //Use chain structure rather than ring structure
205  rxDmaDesc[i].rdes1 = RDES1_RCH | (A2FXXXM3_ETH_RX_BUFFER_SIZE & RDES1_RBS1_MASK);
206  //Receive buffer address
207  rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
208  //Next descriptor address
209  rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
210  }
211 
212  //The last descriptor is chained to the first entry
213  rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
214  //Point to the very first descriptor
215  rxCurDmaDesc = &rxDmaDesc[0];
216 
217  //Start location of the TX descriptor list
218  MAC->CSR4 = (uint32_t) txDmaDesc;
219  //Start location of the RX descriptor list
220  MAC->CSR3 = (uint32_t) rxDmaDesc;
221 }
222 
223 
224 /**
225  * @brief A2FxxxM3 Ethernet MAC timer handler
226  *
227  * This routine is periodically called by the TCP/IP stack to
228  * handle periodic operations such as polling the link state
229  *
230  * @param[in] interface Underlying network interface
231  **/
232 
234 {
235  //Handle periodic operations
236  interface->phyDriver->tick(interface);
237 }
238 
239 
240 /**
241  * @brief Enable interrupts
242  * @param[in] interface Underlying network interface
243  **/
244 
246 {
247  //Enable Ethernet MAC interrupts
248  NVIC_EnableIRQ(EthernetMAC_IRQn);
249  //Enable Ethernet PHY interrupts
250  interface->phyDriver->enableIrq(interface);
251 }
252 
253 
254 /**
255  * @brief Disable interrupts
256  * @param[in] interface Underlying network interface
257  **/
258 
260 {
261  //Disable Ethernet MAC interrupts
262  NVIC_DisableIRQ(EthernetMAC_IRQn);
263  //Disable Ethernet PHY interrupts
264  interface->phyDriver->disableIrq(interface);
265 }
266 
267 
268 /**
269  * @brief A2FxxxM3 Ethernet MAC interrupt service routine
270  **/
271 
273 {
274  bool_t flag;
275  uint32_t status;
276 
277  //Interrupt service routine prologue
278  osEnterIsr();
279 
280  //This flag will be set if a higher priority task must be woken
281  flag = FALSE;
282 
283  //Read interrupt status register
284  status = MAC->CSR5;
285 
286  //A packet has been transmitted?
287  if(status & CSR5_TI_MASK)
288  {
289  //Clear TI interrupt flag
290  MAC->CSR5 = CSR5_TI_MASK;
291 
292  //Check whether the TX buffer is available for writing
293  if(!(txCurDmaDesc->tdes0 & TDES0_OWN))
294  {
295  //Notify the TCP/IP stack that the transmitter is ready to send
296  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
297  }
298  }
299 
300  //A packet has been received?
301  if(status & CSR5_RI_MASK)
302  {
303  //Disable RIE interrupt
304  MAC->CSR7 &= ~CSR7_RIE_MASK;
305 
306  //Set event flag
307  nicDriverInterface->nicEvent = TRUE;
308  //Notify the TCP/IP stack of the event
309  flag |= osSetEventFromIsr(&netEvent);
310  }
311 
312  //Clear NIS interrupt flag
313  MAC->CSR5 = CSR5_NIS_MASK;
314 
315  //Interrupt service routine epilogue
316  osExitIsr(flag);
317 }
318 
319 
320 /**
321  * @brief A2FxxxM3 Ethernet MAC event handler
322  * @param[in] interface Underlying network interface
323  **/
324 
326 {
327  error_t error;
328 
329  //Packet received?
330  if(MAC->CSR5 & CSR5_RI_MASK)
331  {
332  //Clear interrupt flag
333  MAC->CSR5 = CSR5_RI_MASK;
334 
335  //Process all pending packets
336  do
337  {
338  //Read incoming packet
339  error = a2fxxxm3EthReceivePacket(interface);
340 
341  //No more data in the receive buffer?
342  } while(error != ERROR_BUFFER_EMPTY);
343  }
344 
345  //Re-enable Ethernet interrupts
346  MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
347 }
348 
349 
350 /**
351  * @brief Send a setup frame
352  * @param[in] interface Underlying network interface
353  * @return Error code
354  **/
355 
357 {
358  A2fxxxm3HashTableSetupFrame *setupFrame;
359 
360  //Make sure the current buffer is available for writing
361  if(txCurDmaDesc->tdes0 & TDES0_OWN)
362  return ERROR_FAILURE;
363 
364  //Point to the buffer where to format the setup frame
365  setupFrame = (A2fxxxm3HashTableSetupFrame *) txCurDmaDesc->tdes2;
366 
367  //Clear contents
368  memset(setupFrame, 0, sizeof(A2fxxxm3HashTableSetupFrame));
369 
370  //Set MAC address
371  setupFrame->physicalAddr[0] = interface->macAddr.w[0];
372  setupFrame->physicalAddr[1] = interface->macAddr.w[1];
373  setupFrame->physicalAddr[2] = interface->macAddr.w[2];
374 
375  //Write the number of bytes to send
376  txCurDmaDesc->tdes1 = sizeof(A2fxxxm3HashTableSetupFrame) & TDES1_TBS1_MASK;
377  //The SET flag indicates that this is a setup frame descriptor
378  txCurDmaDesc->tdes1 |= TDES1_SET | TDES1_TCH | TDES1_FT0;
379  //Give the ownership of the descriptor to the DMA
380  txCurDmaDesc->tdes0 |= TDES0_OWN;
381 
382  //Instruct the DMA to poll the transmit descriptor list
383  MAC->CSR1 = 1;
384 
385  //Point to the next descriptor in the list
386  txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
387 
388  //Data successfully written
389  return NO_ERROR;
390 }
391 
392 
393 /**
394  * @brief Send a packet
395  * @param[in] interface Underlying network interface
396  * @param[in] buffer Multi-part buffer containing the data to send
397  * @param[in] offset Offset to the first data byte
398  * @return Error code
399  **/
400 
402  const NetBuffer *buffer, size_t offset)
403 {
404  size_t length;
405 
406  //Retrieve the length of the packet
407  length = netBufferGetLength(buffer) - offset;
408 
409  //Check the frame length
411  {
412  //The transmitter can accept another packet
413  osSetEvent(&interface->nicTxEvent);
414  //Report an error
415  return ERROR_INVALID_LENGTH;
416  }
417 
418  //Make sure the current buffer is available for writing
419  if(txCurDmaDesc->tdes0 & TDES0_OWN)
420  return ERROR_FAILURE;
421 
422  //Copy user data to the transmit buffer
423  netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
424 
425  //Write the number of bytes to send
426  txCurDmaDesc->tdes1 = length & TDES1_TBS1_MASK;
427  //Set LS and FS flags as the data fits in a single buffer
428  txCurDmaDesc->tdes1 |= TDES1_IC | TDES1_LS | TDES1_FS | TDES1_TCH;
429  //Give the ownership of the descriptor to the DMA
430  txCurDmaDesc->tdes0 |= TDES0_OWN;
431 
432  //Instruct the DMA to poll the transmit descriptor list
433  MAC->CSR1 = 1;
434 
435  //Point to the next descriptor in the list
436  txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
437 
438  //Check whether the next buffer is available for writing
439  if(!(txCurDmaDesc->tdes0 & TDES0_OWN))
440  {
441  //The transmitter can accept another packet
442  osSetEvent(&interface->nicTxEvent);
443  }
444 
445  //Data successfully written
446  return NO_ERROR;
447 }
448 
449 
450 /**
451  * @brief Receive a packet
452  * @param[in] interface Underlying network interface
453  * @return Error code
454  **/
455 
457 {
458  error_t error;
459  size_t n;
460 
461  //The current buffer is available for reading?
462  if(!(rxCurDmaDesc->rdes0 & RDES0_OWN))
463  {
464  //FS and LS flags should be set
465  if((rxCurDmaDesc->rdes0 & RDES0_FS) && (rxCurDmaDesc->rdes0 & RDES0_LS))
466  {
467  //Make sure no error occurred
468  if(!(rxCurDmaDesc->rdes0 & RDES0_ES))
469  {
470  //Retrieve the length of the frame
471  n = (rxCurDmaDesc->rdes0 >> RDES0_FL_OFFSET) & RDES0_FL_MASK;
472  //Limit the number of data to read
474 
475  //Pass the packet to the upper layer
476  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
477 
478  //Valid packet received
479  error = NO_ERROR;
480  }
481  else
482  {
483  //The received packet contains an error
484  error = ERROR_INVALID_PACKET;
485  }
486  }
487  else
488  {
489  //The packet is not valid
490  error = ERROR_INVALID_PACKET;
491  }
492 
493  //Give the ownership of the descriptor back to the DMA
494  rxCurDmaDesc->rdes0 = RDES0_OWN;
495  //Point to the next descriptor in the list
496  rxCurDmaDesc = (A2fxxxm3RxDmaDesc *) rxCurDmaDesc->rdes3;
497  }
498  else
499  {
500  //No more data in the receive buffer
501  error = ERROR_BUFFER_EMPTY;
502  }
503 
504  //Instruct the DMA to poll the receive descriptor list
505  MAC->CSR2 = 1;
506 
507  //Return status code
508  return error;
509 }
510 
511 
512 /**
513  * @brief Configure MAC address filtering
514  * @param[in] interface Underlying network interface
515  * @return Error code
516  **/
517 
519 {
520  uint_t i;
521  bool_t acceptMulticast;
522 
523  //This flag will be set if multicast addresses should be accepted
524  acceptMulticast = FALSE;
525 
526  //The MAC address filter contains the list of MAC addresses to accept
527  //when receiving an Ethernet frame
528  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
529  {
530  //Valid entry?
531  if(interface->macAddrFilter[i].refCount > 0)
532  {
533  //Accept multicast addresses
534  acceptMulticast = TRUE;
535  //We are done
536  break;
537  }
538  }
539 
540  //Enable the reception of multicast frames if necessary
541  if(acceptMulticast)
542  MAC->CSR6 |= CSR6_PM_MASK;
543  else
544  MAC->CSR6 &= ~CSR6_PM_MASK;
545 
546  //Successful processing
547  return NO_ERROR;
548 }
549 
550 
551 /**
552  * @brief Adjust MAC configuration parameters for proper operation
553  * @param[in] interface Underlying network interface
554  * @return Error code
555  **/
556 
558 {
559  //Stop transmission
560  while(((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) != CSR5_TS_STOPPED)
561  MAC->CSR6 &= ~CSR6_ST_MASK;
562 
563  //Stop reception
564  while(((MAC->CSR5 & CSR5_RS_MASK) >> CSR5_RS_SHIFT) != CSR5_RS_STOPPED)
565  MAC->CSR6 &= ~CSR6_SR_MASK;
566 
567  //10BASE-T or 100BASE-TX operation mode?
568  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
569  MAC->CSR6 |= CSR6_TTM_MASK;
570  else
571  MAC->CSR6 &= ~CSR6_TTM_MASK;
572 
573  //Half-duplex or full-duplex mode?
574  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
575  MAC->CSR6 |= CSR6_FD_MASK;
576  else
577  MAC->CSR6 &= ~CSR6_FD_MASK;
578 
579  //Restart transmission and reception
580  MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
581 
582  //Successful processing
583  return NO_ERROR;
584 }
585 
586 
587 /**
588  * @brief Write PHY register
589  * @param[in] opcode Access type (2 bits)
590  * @param[in] phyAddr PHY address (5 bits)
591  * @param[in] regAddr Register address (5 bits)
592  * @param[in] data Register value
593  **/
594 
595 void a2fxxxm3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
596  uint8_t regAddr, uint16_t data)
597 {
598  //Synchronization pattern
600  //Start of frame
602  //Set up a write operation
604  //Write PHY address
605  a2fxxxm3EthWriteSmi(phyAddr, 5);
606  //Write register address
608  //Turnaround
610  //Write register value
612  //Release MDIO
614 }
615 
616 
617 /**
618  * @brief Read PHY register
619  * @param[in] opcode Access type (2 bits)
620  * @param[in] phyAddr PHY address (5 bits)
621  * @param[in] regAddr Register address (5 bits)
622  * @return Register value
623  **/
624 
625 uint16_t a2fxxxm3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
626  uint8_t regAddr)
627 {
628  uint16_t data;
629 
630  //Synchronization pattern
632  //Start of frame
634  //Set up a read operation
636  //Write PHY address
637  a2fxxxm3EthWriteSmi(phyAddr, 5);
638  //Write register address
640  //Turnaround to avoid contention
642  //Read register value
643  data = a2fxxxm3EthReadSmi(16);
644  //Force the PHY to release the MDIO pin
646 
647  //Return PHY register contents
648  return data;
649 }
650 
651 
652 /**
653  * @brief SMI write operation
654  * @param[in] data Raw data to be written
655  * @param[in] length Number of bits to be written
656  **/
657 
659 {
660  //Skip the most significant bits since they are meaningless
661  data <<= 32 - length;
662 
663  //Configure MDIO as an output
664  MAC->CSR9 |= CSR9_MDEN_MASK;
665 
666  //Write the specified number of bits
667  while(length--)
668  {
669  //Write MDIO
670  if(data & 0x80000000)
671  MAC->CSR9 |= CSR9_MDO_MASK;
672  else
673  MAC->CSR9 &= ~CSR9_MDO_MASK;
674 
675  //Assert MDC
676  usleep(1);
677  MAC->CSR9 |= CSR9_MDC_MASK;
678  //Deassert MDC
679  usleep(1);
680  MAC->CSR9 &= ~CSR9_MDC_MASK;
681 
682  //Rotate data
683  data <<= 1;
684  }
685 }
686 
687 
688 /**
689  * @brief SMI read operation
690  * @param[in] length Number of bits to be read
691  * @return Data resulting from the MDIO read operation
692  **/
693 
695 {
696  uint32_t data = 0;
697 
698  //Configure MDIO as an input
699  MAC->CSR9 &= ~CSR9_MDEN_MASK;
700 
701  //Read the specified number of bits
702  while(length--)
703  {
704  //Rotate data
705  data <<= 1;
706 
707  //Assert MDC
708  MAC->CSR9 |= CSR9_MDC_MASK;
709  usleep(1);
710  //Deassert MDC
711  MAC->CSR9 &= ~CSR9_MDC_MASK;
712  usleep(1);
713 
714  //Check MDIO state
715  if(MAC->CSR9 & CSR9_MDI_MASK)
716  data |= 0x00000001;
717  }
718 
719  //Return the received data
720  return data;
721 }
722 
723 
724 /**
725  * @brief CRC calculation
726  * @param[in] data Pointer to the data over which to calculate the CRC
727  * @param[in] length Number of bytes to process
728  * @return Resulting CRC value
729  **/
730 
731 uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
732 {
733  uint_t i;
734  uint_t j;
735 
736  //Point to the data over which to calculate the CRC
737  const uint8_t *p = (uint8_t *) data;
738  //CRC preset value
739  uint32_t crc = 0xFFFFFFFF;
740 
741  //Loop through data
742  for(i = 0; i < length; i++)
743  {
744  //Update CRC value
745  crc ^= p[i];
746 
747  //The message is processed bit by bit
748  for(j = 0; j < 8; j++)
749  {
750  //Update CRC value
751  if(crc & 0x00000001)
752  crc = (crc >> 1) ^ 0xEDB88320;
753  else
754  crc = crc >> 1;
755  }
756  }
757 
758  //Return CRC value
759  return crc;
760 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define usleep(delay)
Definition: os_port.h:127
void EthernetMAC_IRQHandler(void)
A2FxxxM3 Ethernet MAC interrupt service routine.
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
error_t a2fxxxm3EthReceivePacket(NetInterface *interface)
Receive a packet.
int bool_t
Definition: compiler_port.h:49
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define A2FXXXM3_ETH_IRQ_SUB_PRIORITY
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
void a2fxxxm3EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define SMI_TA
Definition: nic.h:64
void a2fxxxm3EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define SMI_START
Definition: nic.h:60
uint32_t a2fxxxm3EthReadSmi(uint_t length)
SMI read operation.
#define osExitIsr(flag)
#define A2FXXXM3_ETH_TX_BUFFER_SIZE
void a2fxxxm3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define FALSE
Definition: os_port.h:46
error_t
Error codes.
Definition: error.h:42
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
error_t a2fxxxm3EthSendSetup(NetInterface *interface)
Send a setup frame.
#define txBuffer
error_t a2fxxxm3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
@ ERROR_INVALID_PACKET
Definition: error.h:138
#define NetInterface
Definition: net.h:36
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
uint16_t a2fxxxm3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
const NicDriver a2fxxxm3EthDriver
A2FxxxM3 Ethernet MAC driver.
void a2fxxxm3EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
#define A2FXXXM3_ETH_RX_BUFFER_SIZE
#define A2FXXXM3_ETH_RX_BUFFER_COUNT
uint16_t regAddr
void a2fxxxm3EthEventHandler(NetInterface *interface)
A2FxxxM3 Ethernet MAC event handler.
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
#define osEnterIsr()
Transmit DMA descriptor.
SmartFusion (A2FxxxM3) Ethernet MAC controller.
Hash table setup frame.
#define rxDmaDesc
uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
CRC calculation.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define txDmaDesc
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
void a2fxxxm3EthTick(NetInterface *interface)
A2FxxxM3 Ethernet MAC timer handler.
#define SMI_SYNC
Definition: nic.h:59
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
#define CSR9_MDEN_MASK
void a2fxxxm3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t a2fxxxm3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING
error_t a2fxxxm3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t a2fxxxm3EthInit(NetInterface *interface)
A2FxxxM3 Ethernet MAC initialization.
Receive DMA descriptor.
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define A2FXXXM3_ETH_IRQ_GROUP_PRIORITY
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79
#define A2FXXXM3_ETH_TX_BUFFER_COUNT