a2fxxxm3_eth_driver.c
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1 /**
2  * @file a2fxxxm3_eth_driver.c
3  * @brief SmartFusion (A2FxxxM3) Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "a2fxxxm3.h"
34 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_regs_driver.h"
35 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_desc_driver.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit DMA descriptors
53 #pragma data_alignment = 4
55 //Receive DMA descriptors
56 #pragma data_alignment = 4
58 
59 //Keil MDK-ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
64  __attribute__((aligned(4)));
65 //Receive buffer
67  __attribute__((aligned(4)));
68 //Transmit DMA descriptors
70  __attribute__((aligned(4)));
71 //Receive DMA descriptors
73  __attribute__((aligned(4)));
74 
75 #endif
76 
77 //Pointer to the current TX DMA descriptor
78 static A2fxxxm3TxDmaDesc *txCurDmaDesc;
79 //Pointer to the current RX DMA descriptor
80 static A2fxxxm3RxDmaDesc *rxCurDmaDesc;
81 
82 
83 /**
84  * @brief A2FxxxM3 Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief A2FxxxM3 Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117 
118  //Debug message
119  TRACE_INFO("Initializing A2FxxxM3 Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Perform a software reset
125  MAC->CSR0 |= CSR0_SWR_MASK;
126  //Wait for the reset to complete
127  while(MAC->CSR0 & CSR0_SWR_MASK);
128 
129  //PHY transceiver initialization
130  error = interface->phyDriver->init(interface);
131  //Failed to initialize PHY transceiver?
132  if(error)
133  return error;
134 
135  //Enable store and forward mode
136  MAC->CSR6 |= CSR6_SF_MASK;
137 
138  //Initialize DMA descriptor lists
139  a2fxxxm3EthInitDmaDesc(interface);
140 
141  //Enable the desired Ethernet interrupts
142  MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
143 
144  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
145  NVIC_SetPriorityGrouping(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING);
146 
147  //Configure Ethernet interrupt priority
148  NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING,
150 
151  //Enable transmission and reception
152  MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
153 
154  //Set MAC address
155  error = a2fxxxm3EthSendSetup(interface);
156  //Any error to report?
157  if(error)
158  return error;
159 
160  //Accept any packets from the upper layer
161  osSetEvent(&interface->nicTxEvent);
162 
163  //Successful initialization
164  return NO_ERROR;
165 }
166 
167 
168 /**
169  * @brief Initialize DMA descriptor lists
170  * @param[in] interface Underlying network interface
171  **/
172 
174 {
175  uint_t i;
176 
177  //Initialize TX DMA descriptor list
178  for(i = 0; i < A2FXXXM3_ETH_TX_BUFFER_COUNT; i++)
179  {
180  //The descriptor is initially owned by the user
181  txDmaDesc[i].tdes0 = 0;
182  //Use chain structure rather than ring structure
183  txDmaDesc[i].tdes1 = TDES1_TCH;
184  //Transmit buffer address
185  txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
186  //Next descriptor address
187  txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
188  }
189 
190  //The last descriptor is chained to the first entry
191  txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
192  //Point to the very first descriptor
193  txCurDmaDesc = &txDmaDesc[0];
194 
195  //Initialize RX DMA descriptor list
196  for(i = 0; i < A2FXXXM3_ETH_RX_BUFFER_COUNT; i++)
197  {
198  //The descriptor is initially owned by the DMA
199  rxDmaDesc[i].rdes0 = RDES0_OWN;
200  //Use chain structure rather than ring structure
201  rxDmaDesc[i].rdes1 = RDES1_RCH | (A2FXXXM3_ETH_RX_BUFFER_SIZE & RDES1_RBS1_MASK);
202  //Receive buffer address
203  rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
204  //Next descriptor address
205  rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
206  }
207 
208  //The last descriptor is chained to the first entry
209  rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
210  //Point to the very first descriptor
211  rxCurDmaDesc = &rxDmaDesc[0];
212 
213  //Start location of the TX descriptor list
214  MAC->CSR4 = (uint32_t) txDmaDesc;
215  //Start location of the RX descriptor list
216  MAC->CSR3 = (uint32_t) rxDmaDesc;
217 }
218 
219 
220 /**
221  * @brief A2FxxxM3 Ethernet MAC timer handler
222  *
223  * This routine is periodically called by the TCP/IP stack to
224  * handle periodic operations such as polling the link state
225  *
226  * @param[in] interface Underlying network interface
227  **/
228 
230 {
231  //Handle periodic operations
232  interface->phyDriver->tick(interface);
233 }
234 
235 
236 /**
237  * @brief Enable interrupts
238  * @param[in] interface Underlying network interface
239  **/
240 
242 {
243  //Enable Ethernet MAC interrupts
244  NVIC_EnableIRQ(EthernetMAC_IRQn);
245  //Enable Ethernet PHY interrupts
246  interface->phyDriver->enableIrq(interface);
247 }
248 
249 
250 /**
251  * @brief Disable interrupts
252  * @param[in] interface Underlying network interface
253  **/
254 
256 {
257  //Disable Ethernet MAC interrupts
258  NVIC_DisableIRQ(EthernetMAC_IRQn);
259  //Disable Ethernet PHY interrupts
260  interface->phyDriver->disableIrq(interface);
261 }
262 
263 
264 /**
265  * @brief A2FxxxM3 Ethernet MAC interrupt service routine
266  **/
267 
269 {
270  bool_t flag;
271  uint32_t status;
272 
273  //Enter interrupt service routine
274  osEnterIsr();
275 
276  //This flag will be set if a higher priority task must be woken
277  flag = FALSE;
278 
279  //Read interrupt status register
280  status = MAC->CSR5;
281 
282  //A packet has been transmitted?
283  if(status & CSR5_TI_MASK)
284  {
285  //Clear TI interrupt flag
286  MAC->CSR5 = CSR5_TI_MASK;
287 
288  //Check whether the TX buffer is available for writing
289  if(!(txCurDmaDesc->tdes0 & TDES0_OWN))
290  {
291  //Notify the TCP/IP stack that the transmitter is ready to send
292  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
293  }
294  }
295 
296  //A packet has been received?
297  if(status & CSR5_RI_MASK)
298  {
299  //Disable RIE interrupt
300  MAC->CSR7 &= ~CSR7_RIE_MASK;
301 
302  //Set event flag
303  nicDriverInterface->nicEvent = TRUE;
304  //Notify the TCP/IP stack of the event
305  flag |= osSetEventFromIsr(&netEvent);
306  }
307 
308  //Clear NIS interrupt flag
309  MAC->CSR5 = CSR5_NIS_MASK;
310 
311  //Leave interrupt service routine
312  osExitIsr(flag);
313 }
314 
315 
316 /**
317  * @brief A2FxxxM3 Ethernet MAC event handler
318  * @param[in] interface Underlying network interface
319  **/
320 
322 {
323  error_t error;
324 
325  //Packet received?
326  if(MAC->CSR5 & CSR5_RI_MASK)
327  {
328  //Clear interrupt flag
329  MAC->CSR5 = CSR5_RI_MASK;
330 
331  //Process all pending packets
332  do
333  {
334  //Read incoming packet
335  error = a2fxxxm3EthReceivePacket(interface);
336 
337  //No more data in the receive buffer?
338  } while(error != ERROR_BUFFER_EMPTY);
339  }
340 
341  //Re-enable Ethernet interrupts
342  MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
343 }
344 
345 
346 /**
347  * @brief Send a setup frame
348  * @param[in] interface Underlying network interface
349  * @return Error code
350  **/
351 
353 {
354  A2fxxxm3HashTableSetupFrame *setupFrame;
355 
356  //Make sure the current buffer is available for writing
357  if(txCurDmaDesc->tdes0 & TDES0_OWN)
358  return ERROR_FAILURE;
359 
360  //Point to the buffer where to format the setup frame
361  setupFrame = (A2fxxxm3HashTableSetupFrame *) txCurDmaDesc->tdes2;
362 
363  //Clear contents
364  memset(setupFrame, 0, sizeof(A2fxxxm3HashTableSetupFrame));
365 
366  //Set MAC address
367  setupFrame->physicalAddr[0] = interface->macAddr.w[0];
368  setupFrame->physicalAddr[1] = interface->macAddr.w[1];
369  setupFrame->physicalAddr[2] = interface->macAddr.w[2];
370 
371  //Write the number of bytes to send
372  txCurDmaDesc->tdes1 = sizeof(A2fxxxm3HashTableSetupFrame) & TDES1_TBS1_MASK;
373  //The SET flag indicates that this is a setup frame descriptor
374  txCurDmaDesc->tdes1 |= TDES1_SET | TDES1_TCH | TDES1_FT0;
375  //Give the ownership of the descriptor to the DMA
376  txCurDmaDesc->tdes0 |= TDES0_OWN;
377 
378  //Instruct the DMA to poll the transmit descriptor list
379  MAC->CSR1 = 1;
380 
381  //Point to the next descriptor in the list
382  txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
383 
384  //Data successfully written
385  return NO_ERROR;
386 }
387 
388 
389 /**
390  * @brief Send a packet
391  * @param[in] interface Underlying network interface
392  * @param[in] buffer Multi-part buffer containing the data to send
393  * @param[in] offset Offset to the first data byte
394  * @return Error code
395  **/
396 
398  const NetBuffer *buffer, size_t offset)
399 {
400  size_t length;
401 
402  //Retrieve the length of the packet
403  length = netBufferGetLength(buffer) - offset;
404 
405  //Check the frame length
407  {
408  //The transmitter can accept another packet
409  osSetEvent(&interface->nicTxEvent);
410  //Report an error
411  return ERROR_INVALID_LENGTH;
412  }
413 
414  //Make sure the current buffer is available for writing
415  if(txCurDmaDesc->tdes0 & TDES0_OWN)
416  return ERROR_FAILURE;
417 
418  //Copy user data to the transmit buffer
419  netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
420 
421  //Write the number of bytes to send
422  txCurDmaDesc->tdes1 = length & TDES1_TBS1_MASK;
423  //Set LS and FS flags as the data fits in a single buffer
424  txCurDmaDesc->tdes1 |= TDES1_IC | TDES1_LS | TDES1_FS | TDES1_TCH;
425  //Give the ownership of the descriptor to the DMA
426  txCurDmaDesc->tdes0 |= TDES0_OWN;
427 
428  //Instruct the DMA to poll the transmit descriptor list
429  MAC->CSR1 = 1;
430 
431  //Point to the next descriptor in the list
432  txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
433 
434  //Check whether the next buffer is available for writing
435  if(!(txCurDmaDesc->tdes0 & TDES0_OWN))
436  {
437  //The transmitter can accept another packet
438  osSetEvent(&interface->nicTxEvent);
439  }
440 
441  //Data successfully written
442  return NO_ERROR;
443 }
444 
445 
446 /**
447  * @brief Receive a packet
448  * @param[in] interface Underlying network interface
449  * @return Error code
450  **/
451 
453 {
454  error_t error;
455  size_t n;
456 
457  //The current buffer is available for reading?
458  if(!(rxCurDmaDesc->rdes0 & RDES0_OWN))
459  {
460  //FS and LS flags should be set
461  if((rxCurDmaDesc->rdes0 & RDES0_FS) && (rxCurDmaDesc->rdes0 & RDES0_LS))
462  {
463  //Make sure no error occurred
464  if(!(rxCurDmaDesc->rdes0 & RDES0_ES))
465  {
466  //Retrieve the length of the frame
467  n = (rxCurDmaDesc->rdes0 >> RDES0_FL_OFFSET) & RDES0_FL_MASK;
468  //Limit the number of data to read
470 
471  //Pass the packet to the upper layer
472  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
473 
474  //Valid packet received
475  error = NO_ERROR;
476  }
477  else
478  {
479  //The received packet contains an error
480  error = ERROR_INVALID_PACKET;
481  }
482  }
483  else
484  {
485  //The packet is not valid
486  error = ERROR_INVALID_PACKET;
487  }
488 
489  //Give the ownership of the descriptor back to the DMA
490  rxCurDmaDesc->rdes0 = RDES0_OWN;
491  //Point to the next descriptor in the list
492  rxCurDmaDesc = (A2fxxxm3RxDmaDesc *) rxCurDmaDesc->rdes3;
493  }
494  else
495  {
496  //No more data in the receive buffer
497  error = ERROR_BUFFER_EMPTY;
498  }
499 
500  //Instruct the DMA to poll the receive descriptor list
501  MAC->CSR2 = 1;
502 
503  //Return status code
504  return error;
505 }
506 
507 
508 /**
509  * @brief Configure MAC address filtering
510  * @param[in] interface Underlying network interface
511  * @return Error code
512  **/
513 
515 {
516  uint_t i;
517  bool_t acceptMulticast;
518 
519  //This flag will be set if multicast addresses should be accepted
520  acceptMulticast = FALSE;
521 
522  //The MAC address filter contains the list of MAC addresses to accept
523  //when receiving an Ethernet frame
524  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
525  {
526  //Valid entry?
527  if(interface->macAddrFilter[i].refCount > 0)
528  {
529  //Accept multicast addresses
530  acceptMulticast = TRUE;
531  //We are done
532  break;
533  }
534  }
535 
536  //Enable the reception of multicast frames if necessary
537  if(acceptMulticast)
538  MAC->CSR6 |= CSR6_PM_MASK;
539  else
540  MAC->CSR6 &= ~CSR6_PM_MASK;
541 
542  //Successful processing
543  return NO_ERROR;
544 }
545 
546 
547 /**
548  * @brief Adjust MAC configuration parameters for proper operation
549  * @param[in] interface Underlying network interface
550  * @return Error code
551  **/
552 
554 {
555  //Stop transmission
556  while(((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) != CSR5_TS_STOPPED)
557  MAC->CSR6 &= ~CSR6_ST_MASK;
558 
559  //Stop reception
560  while(((MAC->CSR5 & CSR5_RS_MASK) >> CSR5_RS_SHIFT) != CSR5_RS_STOPPED)
561  MAC->CSR6 &= ~CSR6_SR_MASK;
562 
563  //10BASE-T or 100BASE-TX operation mode?
564  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
565  MAC->CSR6 |= CSR6_TTM_MASK;
566  else
567  MAC->CSR6 &= ~CSR6_TTM_MASK;
568 
569  //Half-duplex or full-duplex mode?
570  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
571  MAC->CSR6 |= CSR6_FD_MASK;
572  else
573  MAC->CSR6 &= ~CSR6_FD_MASK;
574 
575  //Restart transmission and reception
576  MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
577 
578  //Successful processing
579  return NO_ERROR;
580 }
581 
582 
583 /**
584  * @brief Write PHY register
585  * @param[in] phyAddr PHY address
586  * @param[in] regAddr Register address
587  * @param[in] data Register value
588  **/
589 
590 void a2fxxxm3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
591 {
592  //Synchronization pattern
594  //Start of frame
596  //Set up a write operation
598  //Write PHY address
599  a2fxxxm3EthWriteSmi(phyAddr, 5);
600  //Write register address
602  //Turnaround
604  //Write register value
606  //Release MDIO
608 }
609 
610 
611 /**
612  * @brief Read PHY register
613  * @param[in] phyAddr PHY address
614  * @param[in] regAddr Register address
615  * @return Register value
616  **/
617 
618 uint16_t a2fxxxm3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
619 {
620  uint16_t data;
621 
622  //Synchronization pattern
624  //Start of frame
626  //Set up a read operation
628  //Write PHY address
629  a2fxxxm3EthWriteSmi(phyAddr, 5);
630  //Write register address
632  //Turnaround to avoid contention
634  //Read register value
635  data = a2fxxxm3EthReadSmi(16);
636  //Force the PHY to release the MDIO pin
638 
639  //Return PHY register contents
640  return data;
641 }
642 
643 
644 /**
645  * @brief SMI write operation
646  * @param[in] data Raw data to be written
647  * @param[in] length Number of bits to be written
648  **/
649 
651 {
652  //Skip the most significant bits since they are meaningless
653  data <<= 32 - length;
654 
655  //Configure MDIO as an output
656  MAC->CSR9 |= CSR9_MDEN_MASK;
657 
658  //Write the specified number of bits
659  while(length--)
660  {
661  //Write MDIO
662  if(data & 0x80000000)
663  MAC->CSR9 |= CSR9_MDO_MASK;
664  else
665  MAC->CSR9 &= ~CSR9_MDO_MASK;
666 
667  //Assert MDC
668  usleep(1);
669  MAC->CSR9 |= CSR9_MDC_MASK;
670  //Deassert MDC
671  usleep(1);
672  MAC->CSR9 &= ~CSR9_MDC_MASK;
673 
674  //Rotate data
675  data <<= 1;
676  }
677 }
678 
679 
680 /**
681  * @brief SMI read operation
682  * @param[in] length Number of bits to be read
683  * @return Data resulting from the MDIO read operation
684  **/
685 
687 {
688  uint32_t data = 0;
689 
690  //Configure MDIO as an input
691  MAC->CSR9 &= ~CSR9_MDEN_MASK;
692 
693  //Read the specified number of bits
694  while(length--)
695  {
696  //Rotate data
697  data <<= 1;
698 
699  //Assert MDC
700  MAC->CSR9 |= CSR9_MDC_MASK;
701  usleep(1);
702  //Deassert MDC
703  MAC->CSR9 &= ~CSR9_MDC_MASK;
704  usleep(1);
705 
706  //Check MDIO state
707  if(MAC->CSR9 & CSR9_MDI_MASK)
708  data |= 0x00000001;
709  }
710 
711  //Return the received data
712  return data;
713 }
714 
715 
716 /**
717  * @brief CRC calculation
718  * @param[in] data Pointer to the data over which to calculate the CRC
719  * @param[in] length Number of bytes to process
720  * @return Resulting CRC value
721  **/
722 
723 uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
724 {
725  uint_t i;
726  uint_t j;
727 
728  //Point to the data over which to calculate the CRC
729  const uint8_t *p = (uint8_t *) data;
730  //CRC preset value
731  uint32_t crc = 0xFFFFFFFF;
732 
733  //Loop through data
734  for(i = 0; i < length; i++)
735  {
736  //Update CRC value
737  crc ^= p[i];
738 
739  //The message is processed bit by bit
740  for(j = 0; j < 8; j++)
741  {
742  //Update CRC value
743  if(crc & 0x00000001)
744  crc = (crc >> 1) ^ 0xEDB88320;
745  else
746  crc = crc >> 1;
747  }
748  }
749 
750  //Return CRC value
751  return crc;
752 }
error_t a2fxxxm3EthInit(NetInterface *interface)
A2FxxxM3 Ethernet MAC initialization.
void a2fxxxm3EthTick(NetInterface *interface)
A2FxxxM3 Ethernet MAC timer handler.
#define txDmaDesc
#define A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING
TCP/IP stack core.
error_t a2fxxxm3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
void EthernetMAC_IRQHandler(void)
A2FxxxM3 Ethernet MAC interrupt service routine.
Generic error code.
Definition: error.h:43
uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define rxDmaDesc
#define txBuffer
error_t a2fxxxm3EthSendSetup(NetInterface *interface)
Send a setup frame.
void a2fxxxm3EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define A2FXXXM3_ETH_TX_BUFFER_COUNT
uint16_t a2fxxxm3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
error_t a2fxxxm3EthReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t a2fxxxm3EthReadSmi(uint_t length)
SMI read operation.
#define A2FXXXM3_ETH_IRQ_GROUP_PRIORITY
#define SMI_START
#define SMI_SYNC
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define usleep(delay)
Definition: os_port.h:122
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void a2fxxxm3EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define CSR9_MDEN_MASK
#define A2FXXXM3_ETH_IRQ_SUB_PRIORITY
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
SmartFusion (A2FxxxM3) Ethernet MAC controller.
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
Receive DMA descriptor.
#define NetInterface
Definition: net.h:34
void a2fxxxm3EthEventHandler(NetInterface *interface)
A2FxxxM3 Ethernet MAC event handler.
Hash table setup frame.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define SMI_TA
#define SMI_READ
void a2fxxxm3EthDisableIrq(NetInterface *interface)
Disable interrupts.
void a2fxxxm3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define SMI_WRITE
#define osExitIsr(flag)
error_t a2fxxxm3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define osEnterIsr()
#define A2FXXXM3_ETH_RX_BUFFER_SIZE
const NicDriver a2fxxxm3EthDriver
A2FxxxM3 Ethernet MAC driver.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define A2FXXXM3_ETH_RX_BUFFER_COUNT
Transmit DMA descriptor.
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
#define A2FXXXM3_ETH_TX_BUFFER_SIZE
void a2fxxxm3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t a2fxxxm3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.