efm32gg11_eth_driver.c
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1 /**
2  * @file efm32gg11_eth_driver.c
3  * @brief EFM32 Giant Gecko 11 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "em_device.h"
37 #include "em_cmu.h"
38 #include "em_gpio.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 8
52 //RX buffer
53 #pragma data_alignment = 8
55 //TX buffer descriptors
56 #pragma data_alignment = 4
58 //RX buffer descriptors
59 #pragma data_alignment = 4
61 
62 //Keil MDK-ARM or GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(8)));
68 //RX buffer
70  __attribute__((aligned(8)));
71 //TX buffer descriptors
73  __attribute__((aligned(4)));
74 //RX buffer descriptors
76  __attribute__((aligned(4)));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief EFM32GG11 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief EFM32GG11 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing EFM32GG11 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Enable high-frequency peripheral clock
129  CMU_ClockEnable(cmuClock_HFPER, true);
130  //Enable Ethernet peripheral clock
131  CMU_ClockEnable(cmuClock_ETH, true);
132 
133  //GPIO configuration
134  efm32gg11EthInitGpio(interface);
135 
136  //Configure MDC clock speed
137  ETH->NETWORKCFG = (4 << _ETH_NETWORKCFG_MDCCLKDIV_SHIFT) &
138  _ETH_NETWORKCFG_MDCCLKDIV_MASK;
139 
140  //Enable management port (MDC and MDIO)
141  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_MANPORTEN_MASK;
142 
143  //PHY transceiver initialization
144  error = interface->phyDriver->init(interface);
145  //Failed to initialize PHY transceiver?
146  if(error)
147  return error;
148 
149  //Set the MAC address of the station
150  ETH->SPECADDR1BOTTOM = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
151  ETH->SPECADDR1TOP = interface->macAddr.w[2];
152 
153  //The MAC supports 3 additional addresses for unicast perfect filtering
154  ETH->SPECADDR2BOTTOM = 0;
155  ETH->SPECADDR3BOTTOM = 0;
156  ETH->SPECADDR4BOTTOM = 0;
157 
158  //Initialize hash table
159  ETH->HASHBOTTOM = 0;
160  ETH->HASHTOP = 0;
161 
162  //Configure the receive filter
163  ETH->NETWORKCFG |= _ETH_NETWORKCFG_RX1536BYTEFRAMES_MASK |
164  _ETH_NETWORKCFG_MULTICASTHASHEN_MASK;
165 
166  //Initialize buffer descriptors
167  efm32gg11EthInitBufferDesc(interface);
168 
169  //Clear transmit status register
170  ETH->TXSTATUS = _ETH_TXSTATUS_TXUNDERRUN_MASK |
171  _ETH_TXSTATUS_TXCMPLT_MASK | _ETH_TXSTATUS_AMBAERR_MASK |
172  _ETH_TXSTATUS_TXGO_MASK | _ETH_TXSTATUS_RETRYLMTEXCD_MASK |
173  _ETH_TXSTATUS_COLOCCRD_MASK | _ETH_TXSTATUS_USEDBITREAD_MASK;
174 
175  //Clear receive status register
176  ETH->RXSTATUS = _ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
177  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK;
178 
179  //First disable all interrupts
180  ETH->IENC = 0xFFFFFFFF;
181 
182  //Only the desired ones are enabled
183  ETH->IENS = _ETH_IENS_RXOVERRUN_MASK |
184  _ETH_IENS_TXCMPLT_MASK | _ETH_IENS_AMBAERR_MASK |
185  _ETH_IENS_RTRYLMTORLATECOL_MASK | _ETH_IENS_TXUNDERRUN_MASK |
186  _ETH_IENS_RXUSEDBITREAD_MASK | _ETH_IENS_RXCMPLT_MASK;
187 
188  //Read ETH_IFCR register to clear any pending interrupt
189  status = ETH->IFCR;
190 
191  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
192  NVIC_SetPriorityGrouping(EFM32GG11_ETH_IRQ_PRIORITY_GROUPING);
193 
194  //Configure Ethernet interrupt priority
195  NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(EFM32GG11_ETH_IRQ_PRIORITY_GROUPING,
197 
198  //Enable the transmitter and the receiver
199  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_ENBTX_MASK | _ETH_NETWORKCTRL_ENBRX_MASK;
200 
201  //Accept any packets from the upper layer
202  osSetEvent(&interface->nicTxEvent);
203 
204  //Successful initialization
205  return NO_ERROR;
206 }
207 
208 
209 //EFM32 Giant Gecko 11 Starter Kit?
210 #if defined(USE_EFM32_GIANT_GECKO_11_SK)
211 
212 /**
213  * @brief GPIO configuration
214  * @param[in] interface Underlying network interface
215  **/
216 
217 void efm32gg11EthInitGpio(NetInterface *interface)
218 {
219  uint32_t temp;
220 
221  //Enable GPIO clock
222  CMU_ClockEnable(cmuClock_GPIO, true);
223  //Enable external oscillator
224  CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
225 
226  //Select CMU_CLK2 clock source
227  CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
228 
229  //Configure CMU_CLK2 (PD10)
230  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_CMU_CLK2_PORT(5),
231  AF_CMU_CLK2_PIN(5), gpioModePushPull, 0);
232 
233  //Remap CMU_CLK2 pin
234  temp = CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK;
235  CMU->ROUTELOC0 = temp | CMU_ROUTELOC0_CLKOUT2LOC_LOC5;
236 
237  //Enable CMU_CLK2 pin
238  CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
239 
240  //Select RMII operation mode and enable transceiver clock
241  ETH->CTRL = ETH_CTRL_GBLCLKEN | ETH_CTRL_MIISEL_RMII;
242 
243  //Configure ETH_RMII_TXD0 (PF7)
244  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXD0_PORT(1),
245  AF_ETH_RMIITXD0_PIN(1), gpioModePushPull, 0);
246 
247  //Configure ETH_RMII_TXD1 (PF6)
248  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXD1_PORT(1),
249  AF_ETH_RMIITXD1_PIN(1), gpioModePushPull, 0);
250 
251  //Configure ETH_RMII_TXEN (PF8)
252  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXEN_PORT(1),
253  AF_ETH_RMIITXEN_PIN(1), gpioModePushPull, 0);
254 
255  //Configure ETH_RMII_RXD0 (PD9)
256  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXD0_PORT(1),
257  AF_ETH_RMIIRXD0_PIN(1), gpioModeInput, 0);
258 
259  //Configure ETH_RMII_RXD1 (PF9)
260  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXD1_PORT(1),
261  AF_ETH_RMIIRXD1_PIN(1), gpioModeInput, 0);
262 
263  //Configure ETH_RMII_CRSDV (PD11)
264  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIICRSDV_PORT(1),
265  AF_ETH_RMIICRSDV_PIN(1), gpioModeInput, 0);
266 
267  //Configure ETH_RMII_RXER (PD12)
268  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXER_PORT(1),
269  AF_ETH_RMIIRXER_PIN(1), gpioModeInput, 0);
270 
271  //Configure ETH_MDIO (PD13)
272  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_MDIO_PORT(1),
273  AF_ETH_MDIO_PIN(1), gpioModePushPull, 0);
274 
275  //Configure ETH_MDC (PD14)
276  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_MDC_PORT(1),
277  AF_ETH_MDC_PIN(1), gpioModePushPull, 0);
278 
279  //Remap RMII pins
280  temp = ETH->ROUTELOC1 & ~(_ETH_ROUTELOC1_RMIILOC_MASK & _ETH_ROUTELOC1_MDIOLOC_MASK);
281  ETH->ROUTELOC1 = temp | (ETH_ROUTELOC1_RMIILOC_LOC1 | ETH_ROUTELOC1_MDIOLOC_LOC1);
282 
283  //Enable RMII pins
284  ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
285 
286  //Configure ETH_PWR_ENABLE (PI10)
287  GPIO_PinModeSet(gpioPortI, 10, gpioModePushPull, 0);
288  //Configure ETH_RESET_N (PH7)
289  GPIO_PinModeSet(gpioPortH, 7, gpioModePushPull, 0);
290  //Configure ETH_INTRP (PG15)
291  GPIO_PinModeSet(gpioPortG, 15, gpioModeInput, 0);
292 
293  //Power on PHY transceiver
294  GPIO_PinOutSet(gpioPortI, 10);
295  sleep(10);
296 
297  //Reset PHY transceiver (hard reset)
298  GPIO_PinOutClear(gpioPortH, 7);
299  sleep(10);
300  GPIO_PinOutSet(gpioPortH, 7);
301  sleep(10);
302 }
303 
304 #endif
305 
306 
307 /**
308  * @brief Initialize buffer descriptors
309  * @param[in] interface Underlying network interface
310  **/
311 
313 {
314  uint_t i;
315  uint32_t address;
316 
317  //Initialize TX buffer descriptors
318  for(i = 0; i < EFM32GG11_ETH_TX_BUFFER_COUNT; i++)
319  {
320  //Calculate the address of the current TX buffer
321  address = (uint32_t) txBuffer[i];
322  //Write the address to the descriptor entry
323  txBufferDesc[i].address = address;
324  //Initialize status field
325  txBufferDesc[i].status = ETH_TX_USED;
326  }
327 
328  //Mark the last descriptor entry with the wrap flag
329  txBufferDesc[i - 1].status |= ETH_TX_WRAP;
330  //Initialize TX buffer index
331  txBufferIndex = 0;
332 
333  //Initialize RX buffer descriptors
334  for(i = 0; i < EFM32GG11_ETH_RX_BUFFER_COUNT; i++)
335  {
336  //Calculate the address of the current RX buffer
337  address = (uint32_t) rxBuffer[i];
338  //Write the address to the descriptor entry
339  rxBufferDesc[i].address = address & ETH_RX_ADDRESS;
340  //Clear status field
341  rxBufferDesc[i].status = 0;
342  }
343 
344  //Mark the last descriptor entry with the wrap flag
345  rxBufferDesc[i - 1].address |= ETH_RX_WRAP;
346  //Initialize RX buffer index
347  rxBufferIndex = 0;
348 
349  //Start location of the TX descriptor list
350  ETH->TXQPTR = (uint32_t) txBufferDesc;
351  //Start location of the RX descriptor list
352  ETH->RXQPTR = (uint32_t) rxBufferDesc;
353 }
354 
355 
356 /**
357  * @brief EFM32GG11 Ethernet MAC timer handler
358  *
359  * This routine is periodically called by the TCP/IP stack to
360  * handle periodic operations such as polling the link state
361  *
362  * @param[in] interface Underlying network interface
363  **/
364 
366 {
367  //Handle periodic operations
368  interface->phyDriver->tick(interface);
369 }
370 
371 
372 /**
373  * @brief Enable interrupts
374  * @param[in] interface Underlying network interface
375  **/
376 
378 {
379  //Enable Ethernet MAC interrupts
380  NVIC_EnableIRQ(ETH_IRQn);
381  //Enable Ethernet PHY interrupts
382  interface->phyDriver->enableIrq(interface);
383 }
384 
385 
386 /**
387  * @brief Disable interrupts
388  * @param[in] interface Underlying network interface
389  **/
390 
392 {
393  //Disable Ethernet MAC interrupts
394  NVIC_DisableIRQ(ETH_IRQn);
395  //Disable Ethernet PHY interrupts
396  interface->phyDriver->disableIrq(interface);
397 }
398 
399 
400 /**
401  * @brief EFM32GG11 Ethernet MAC interrupt service routine
402  **/
403 
404 void ETH_IRQHandler(void)
405 {
406  bool_t flag;
407  volatile uint32_t isr;
408  volatile uint32_t tsr;
409  volatile uint32_t rsr;
410 
411  //Enter interrupt service routine
412  osEnterIsr();
413 
414  //This flag will be set if a higher priority task must be woken
415  flag = FALSE;
416 
417  //Each time the software reads ETH_IFCR, it has to check the contents
418  //of ETH_TXSTATUS, ETH_RXSTATUS and ETH_NETWORKSTATUS
419  isr = ETH->IFCR;
420  tsr = ETH->TXSTATUS;
421  rsr = ETH->RXSTATUS;
422 
423  //Clear interrupt flags
424  ETH->IFCR = isr;
425 
426  //A packet has been transmitted?
427  if(tsr & (_ETH_TXSTATUS_TXUNDERRUN_MASK |
428  _ETH_TXSTATUS_TXCMPLT_MASK | _ETH_TXSTATUS_AMBAERR_MASK |
429  _ETH_TXSTATUS_TXGO_MASK | _ETH_TXSTATUS_RETRYLMTEXCD_MASK |
430  _ETH_TXSTATUS_COLOCCRD_MASK | _ETH_TXSTATUS_USEDBITREAD_MASK))
431  {
432  //Only clear TXSTATUS flags that are currently set
433  ETH->TXSTATUS = tsr;
434 
435  //Check whether the TX buffer is available for writing
436  if(txBufferDesc[txBufferIndex].status & ETH_TX_USED)
437  {
438  //Notify the TCP/IP stack that the transmitter is ready to send
439  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
440  }
441  }
442 
443  //A packet has been received?
444  if(rsr & (_ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
445  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK))
446  {
447  //Set event flag
448  nicDriverInterface->nicEvent = TRUE;
449  //Notify the TCP/IP stack of the event
450  flag |= osSetEventFromIsr(&netEvent);
451  }
452 
453  //Leave interrupt service routine
454  osExitIsr(flag);
455 }
456 
457 
458 /**
459  * @brief EFM32GG11 Ethernet MAC event handler
460  * @param[in] interface Underlying network interface
461  **/
462 
464 {
465  error_t error;
466  uint32_t rsr;
467 
468  //Read receive status
469  rsr = ETH->RXSTATUS;
470 
471  //Packet received?
472  if(rsr & (_ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
473  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK))
474  {
475  //Only clear RXSTATUS flags that are currently set
476  ETH->RXSTATUS = rsr;
477 
478  //Process all pending packets
479  do
480  {
481  //Read incoming packet
482  error = efm32gg11EthReceivePacket(interface);
483 
484  //No more data in the receive buffer?
485  } while(error != ERROR_BUFFER_EMPTY);
486  }
487 }
488 
489 
490 /**
491  * @brief Send a packet
492  * @param[in] interface Underlying network interface
493  * @param[in] buffer Multi-part buffer containing the data to send
494  * @param[in] offset Offset to the first data byte
495  * @return Error code
496  **/
497 
499  const NetBuffer *buffer, size_t offset)
500 {
501  size_t length;
502 
503  //Retrieve the length of the packet
504  length = netBufferGetLength(buffer) - offset;
505 
506  //Check the frame length
508  {
509  //The transmitter can accept another packet
510  osSetEvent(&interface->nicTxEvent);
511  //Report an error
512  return ERROR_INVALID_LENGTH;
513  }
514 
515  //Make sure the current buffer is available for writing
516  if(!(txBufferDesc[txBufferIndex].status & ETH_TX_USED))
517  return ERROR_FAILURE;
518 
519  //Copy user data to the transmit buffer
520  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
521 
522  //Set the necessary flags in the descriptor entry
523  if(txBufferIndex < (EFM32GG11_ETH_TX_BUFFER_COUNT - 1))
524  {
525  //Write the status word
526  txBufferDesc[txBufferIndex].status = ETH_TX_LAST |
527  (length & ETH_TX_LENGTH);
528 
529  //Point to the next buffer
530  txBufferIndex++;
531  }
532  else
533  {
534  //Write the status word
535  txBufferDesc[txBufferIndex].status = ETH_TX_WRAP | ETH_TX_LAST |
536  (length & ETH_TX_LENGTH);
537 
538  //Wrap around
539  txBufferIndex = 0;
540  }
541 
542  //Set the TSTART bit to initiate transmission
543  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_TXSTRT_MASK;
544 
545  //Check whether the next buffer is available for writing
546  if(txBufferDesc[txBufferIndex].status & ETH_TX_USED)
547  {
548  //The transmitter can accept another packet
549  osSetEvent(&interface->nicTxEvent);
550  }
551 
552  //Successful processing
553  return NO_ERROR;
554 }
555 
556 
557 /**
558  * @brief Receive a packet
559  * @param[in] interface Underlying network interface
560  * @return Error code
561  **/
562 
564 {
565  static uint8_t temp[ETH_MAX_FRAME_SIZE];
566  error_t error;
567  uint_t i;
568  uint_t j;
569  uint_t sofIndex;
570  uint_t eofIndex;
571  size_t n;
572  size_t size;
573  size_t length;
574 
575  //Initialize SOF and EOF indices
576  sofIndex = UINT_MAX;
577  eofIndex = UINT_MAX;
578 
579  //Search for SOF and EOF flags
580  for(i = 0; i < EFM32GG11_ETH_RX_BUFFER_COUNT; i++)
581  {
582  //Point to the current entry
583  j = rxBufferIndex + i;
584 
585  //Wrap around to the beginning of the buffer if necessary
588 
589  //No more entries to process?
590  if(!(rxBufferDesc[j].address & ETH_RX_OWNERSHIP))
591  {
592  //Stop processing
593  break;
594  }
595  //A valid SOF has been found?
596  if(rxBufferDesc[j].status & ETH_RX_SOF)
597  {
598  //Save the position of the SOF
599  sofIndex = i;
600  }
601  //A valid EOF has been found?
602  if((rxBufferDesc[j].status & ETH_RX_EOF) && sofIndex != UINT_MAX)
603  {
604  //Save the position of the EOF
605  eofIndex = i;
606  //Retrieve the length of the frame
607  size = rxBufferDesc[j].status & ETH_RX_LENGTH;
608  //Limit the number of data to read
609  size = MIN(size, ETH_MAX_FRAME_SIZE);
610  //Stop processing since we have reached the end of the frame
611  break;
612  }
613  }
614 
615  //Determine the number of entries to process
616  if(eofIndex != UINT_MAX)
617  j = eofIndex + 1;
618  else if(sofIndex != UINT_MAX)
619  j = sofIndex;
620  else
621  j = i;
622 
623  //Total number of bytes that have been copied from the receive buffer
624  length = 0;
625 
626  //Process incoming frame
627  for(i = 0; i < j; i++)
628  {
629  //Any data to copy from current buffer?
630  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
631  {
632  //Calculate the number of bytes to read at a time
634  //Copy data from receive buffer
635  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
636  //Update byte counters
637  length += n;
638  size -= n;
639  }
640 
641  //Mark the current buffer as free
642  rxBufferDesc[rxBufferIndex].address &= ~ETH_RX_OWNERSHIP;
643 
644  //Point to the following entry
645  rxBufferIndex++;
646 
647  //Wrap around to the beginning of the buffer if necessary
648  if(rxBufferIndex >= EFM32GG11_ETH_RX_BUFFER_COUNT)
649  rxBufferIndex = 0;
650  }
651 
652  //Any packet to process?
653  if(length > 0)
654  {
655  //Pass the packet to the upper layer
656  nicProcessPacket(interface, temp, length);
657  //Valid packet received
658  error = NO_ERROR;
659  }
660  else
661  {
662  //No more data in the receive buffer
663  error = ERROR_BUFFER_EMPTY;
664  }
665 
666  //Return status code
667  return error;
668 }
669 
670 
671 /**
672  * @brief Configure MAC address filtering
673  * @param[in] interface Underlying network interface
674  * @return Error code
675  **/
676 
678 {
679  uint_t i;
680  uint_t j;
681  uint_t k;
682  uint8_t *p;
683  uint32_t hashTable[2];
684  MacAddr unicastMacAddr[3];
685  MacFilterEntry *entry;
686 
687  //Debug message
688  TRACE_DEBUG("Updating MAC filter...\r\n");
689 
690  //The MAC supports 3 additional addresses for unicast perfect filtering
691  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
692  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
693  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
694 
695  //The hash table is used for multicast address filtering
696  hashTable[0] = 0;
697  hashTable[1] = 0;
698 
699  //The MAC address filter contains the list of MAC addresses to accept
700  //when receiving an Ethernet frame
701  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
702  {
703  //Point to the current entry
704  entry = &interface->macAddrFilter[i];
705 
706  //Valid entry?
707  if(entry->refCount > 0)
708  {
709  //Multicast address?
710  if(macIsMulticastAddr(&entry->addr))
711  {
712  //Point to the MAC address
713  p = entry->addr.b;
714 
715  //Apply the hash function
716  k = (p[0] >> 6) ^ p[0];
717  k ^= (p[1] >> 4) ^ (p[1] << 2);
718  k ^= (p[2] >> 2) ^ (p[2] << 4);
719  k ^= (p[3] >> 6) ^ p[3];
720  k ^= (p[4] >> 4) ^ (p[4] << 2);
721  k ^= (p[5] >> 2) ^ (p[5] << 4);
722 
723  //The hash value is reduced to a 6-bit index
724  k &= 0x3F;
725 
726  //Update hash table contents
727  hashTable[k / 32] |= (1 << (k % 32));
728  }
729  else
730  {
731  //Up to 3 additional MAC addresses can be specified
732  if(j < 3)
733  {
734  //Save the unicast address
735  unicastMacAddr[j++] = entry->addr;
736  }
737  }
738  }
739  }
740 
741  //Configure the first unicast address filter
742  if(j >= 1)
743  {
744  //The addresse is activated when SAT register is written
745  ETH->SPECADDR2BOTTOM = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
746  ETH->SPECADDR2TOP = unicastMacAddr[0].w[2];
747  }
748  else
749  {
750  //The addresse is activated when SAB register is written
751  ETH->SPECADDR2BOTTOM = 0;
752  }
753 
754  //Configure the second unicast address filter
755  if(j >= 2)
756  {
757  //The addresse is activated when SAT register is written
758  ETH->SPECADDR3BOTTOM = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
759  ETH->SPECADDR3TOP = unicastMacAddr[1].w[2];
760  }
761  else
762  {
763  //The addresse is activated when SAB register is written
764  ETH->SPECADDR3BOTTOM = 0;
765  }
766 
767  //Configure the third unicast address filter
768  if(j >= 3)
769  {
770  //The addresse is activated when SAT register is written
771  ETH->SPECADDR4BOTTOM = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
772  ETH->SPECADDR4TOP = unicastMacAddr[2].w[2];
773  }
774  else
775  {
776  //The addresse is activated when SAB register is written
777  ETH->SPECADDR4BOTTOM = 0;
778  }
779 
780  //Configure the multicast address filter
781  ETH->HASHBOTTOM = hashTable[0];
782  ETH->HASHTOP = hashTable[1];
783 
784  //Debug message
785  TRACE_DEBUG(" HASHBOTTOM = %08" PRIX32 "\r\n", ETH->HASHBOTTOM);
786  TRACE_DEBUG(" HASHTOP = %08" PRIX32 "\r\n", ETH->HASHTOP);
787 
788  //Successful processing
789  return NO_ERROR;
790 }
791 
792 
793 /**
794  * @brief Adjust MAC configuration parameters for proper operation
795  * @param[in] interface Underlying network interface
796  * @return Error code
797  **/
798 
800 {
801  uint32_t config;
802 
803  //Read network configuration register
804  config = ETH->NETWORKCFG;
805 
806  //10BASE-T or 100BASE-TX operation mode?
807  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
808  config |= _ETH_NETWORKCFG_SPEED_MASK;
809  else
810  config &= ~_ETH_NETWORKCFG_SPEED_MASK;
811 
812  //Half-duplex or full-duplex mode?
813  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
814  config |= _ETH_NETWORKCFG_FULLDUPLEX_MASK;
815  else
816  config &= ~_ETH_NETWORKCFG_FULLDUPLEX_MASK;
817 
818  //Write configuration value back to ETH_NETWORKCFG register
819  ETH->NETWORKCFG = config;
820 
821  //Successful processing
822  return NO_ERROR;
823 }
824 
825 
826 /**
827  * @brief Write PHY register
828  * @param[in] phyAddr PHY address
829  * @param[in] regAddr Register address
830  * @param[in] data Register value
831  **/
832 
833 void efm32gg11EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
834 {
835  uint32_t value;
836 
837  //Set up a write operation
838  value = _ETH_PHYMNGMNT_WRITE1_MASK;
839  value |= (1 << _ETH_PHYMNGMNT_OPERATION_SHIFT) & _ETH_PHYMNGMNT_OPERATION_MASK;
840  value |= (2 << _ETH_PHYMNGMNT_WRITE10_SHIFT) & _ETH_PHYMNGMNT_WRITE10_MASK;
841 
842  //PHY address
843  value |= (phyAddr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) & _ETH_PHYMNGMNT_PHYADDR_MASK;
844  //Register address
845  value |= (regAddr << _ETH_PHYMNGMNT_REGADDR_SHIFT) & _ETH_PHYMNGMNT_REGADDR_MASK;
846  //Register value
847  value |= data & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
848 
849  //Start a write operation
850  ETH->PHYMNGMNT = value;
851  //Wait for the write to complete
852  while(!(ETH->NETWORKSTATUS & _ETH_NETWORKSTATUS_MANDONE_MASK));
853 }
854 
855 
856 /**
857  * @brief Read PHY register
858  * @param[in] phyAddr PHY address
859  * @param[in] regAddr Register address
860  * @return Register value
861  **/
862 
863 uint16_t efm32gg11EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
864 {
865  uint32_t value;
866 
867  //Set up a read operation
868  value = _ETH_PHYMNGMNT_WRITE1_MASK;
869  value |= (2 << _ETH_PHYMNGMNT_OPERATION_SHIFT) & _ETH_PHYMNGMNT_OPERATION_MASK;
870  value |= (2 << _ETH_PHYMNGMNT_WRITE10_SHIFT) & _ETH_PHYMNGMNT_WRITE10_MASK;
871 
872  //PHY address
873  value |= (phyAddr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) & _ETH_PHYMNGMNT_PHYADDR_MASK;
874  //Register address
875  value |= (regAddr << _ETH_PHYMNGMNT_REGADDR_SHIFT) & _ETH_PHYMNGMNT_REGADDR_MASK;
876 
877  //Start a read operation
878  ETH->PHYMNGMNT = value;
879  //Wait for the read to complete
880  while(!(ETH->NETWORKSTATUS & _ETH_NETWORKSTATUS_MANDONE_MASK));
881 
882  //Return PHY register contents
883  return ETH->PHYMNGMNT & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
884 }
#define EFM32GG11_ETH_RX_BUFFER_COUNT
uint16_t efm32gg11EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
MacAddr addr
MAC address.
Definition: ethernet.h:219
error_t efm32gg11EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
const NicDriver efm32gg11EthDriver
EFM32GG11 Ethernet MAC driver.
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:297
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define EFM32GG11_ETH_TX_BUFFER_SIZE
error_t efm32gg11EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ETH_RX_LENGTH
void efm32gg11EthDisableIrq(NetInterface *interface)
Disable interrupts.
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:107
void efm32gg11EthTick(NetInterface *interface)
EFM32GG11 Ethernet MAC timer handler.
#define txBuffer
void efm32gg11EthEventHandler(NetInterface *interface)
EFM32GG11 Ethernet MAC event handler.
#define ETH_TX_LAST
#define EFM32GG11_ETH_IRQ_SUB_PRIORITY
void efm32gg11EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define EFM32GG11_ETH_IRQ_PRIORITY_GROUPING
#define ETH_TX_USED
#define sleep(delay)
Definition: os_port.h:128
#define ETH_RX_ADDRESS
#define EFM32GG11_ETH_RX_BUFFER_SIZE
#define EFM32GG11_ETH_IRQ_GROUP_PRIORITY
#define TRUE
Definition: os_port.h:50
#define ETH_RX_WRAP
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define EFM32GG11_ETH_TX_BUFFER_COUNT
Transmit buffer descriptor.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void efm32gg11EthInitGpio(NetInterface *interface)
error_t efm32gg11EthInit(NetInterface *interface)
EFM32GG11 Ethernet MAC initialization.
NIC driver.
Definition: nic.h:164
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void efm32gg11EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MIN(a, b)
Definition: os_port.h:62
Receive buffer descriptor.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void ETH_IRQHandler(void)
EFM32GG11 Ethernet MAC interrupt service routine.
#define ETH_TX_LENGTH
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
#define ETH_RX_EOF
#define TRACE_INFO(...)
Definition: debug.h:94
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:71
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:73
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:220
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
#define ETH_RX_OWNERSHIP
#define ETH_TX_WRAP
unsigned int uint_t
Definition: compiler_port.h:45
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define ETH_RX_SOF
#define osExitIsr(flag)
EFM32 Giant Gecko 11 Ethernet MAC controller.
void efm32gg11EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t efm32gg11EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define osEnterIsr()
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
error_t efm32gg11EthReceivePacket(NetInterface *interface)
Receive a packet.
MAC filter table entry.
Definition: ethernet.h:217
#define TRACE_DEBUG(...)
Definition: debug.h:106