efm32gg11_eth_driver.c
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1 /**
2  * @file efm32gg11_eth_driver.c
3  * @brief EFM32 Giant Gecko 11 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "em_device.h"
37 #include "em_cmu.h"
38 #include "em_gpio.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 8
52 //RX buffer
53 #pragma data_alignment = 8
55 //TX buffer descriptors
56 #pragma data_alignment = 4
58 //RX buffer descriptors
59 #pragma data_alignment = 4
61 
62 //Keil MDK-ARM or GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(8)));
68 //RX buffer
70  __attribute__((aligned(8)));
71 //TX buffer descriptors
73  __attribute__((aligned(4)));
74 //RX buffer descriptors
76  __attribute__((aligned(4)));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief EFM32GG11 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief EFM32GG11 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing EFM32GG11 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Enable high-frequency peripheral clock
129  CMU_ClockEnable(cmuClock_HFPER, true);
130  //Enable Ethernet peripheral clock
131  CMU_ClockEnable(cmuClock_ETH, true);
132 
133  //Disable transmit and receive circuits
134  ETH->NETWORKCTRL = 0;
135 
136  //GPIO configuration
137  efm32gg11EthInitGpio(interface);
138 
139  //Configure MDC clock speed
140  ETH->NETWORKCFG = (4 << _ETH_NETWORKCFG_MDCCLKDIV_SHIFT) &
141  _ETH_NETWORKCFG_MDCCLKDIV_MASK;
142 
143  //Enable management port (MDC and MDIO)
144  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_MANPORTEN_MASK;
145 
146  //PHY transceiver initialization
147  error = interface->phyDriver->init(interface);
148  //Failed to initialize PHY transceiver?
149  if(error)
150  return error;
151 
152  //Set the MAC address of the station
153  ETH->SPECADDR1BOTTOM = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
154  ETH->SPECADDR1TOP = interface->macAddr.w[2];
155 
156  //The MAC supports 3 additional addresses for unicast perfect filtering
157  ETH->SPECADDR2BOTTOM = 0;
158  ETH->SPECADDR3BOTTOM = 0;
159  ETH->SPECADDR4BOTTOM = 0;
160 
161  //Initialize hash table
162  ETH->HASHBOTTOM = 0;
163  ETH->HASHTOP = 0;
164 
165  //Configure the receive filter
166  ETH->NETWORKCFG |= _ETH_NETWORKCFG_RX1536BYTEFRAMES_MASK |
167  _ETH_NETWORKCFG_MULTICASTHASHEN_MASK;
168 
169  //Initialize buffer descriptors
170  efm32gg11EthInitBufferDesc(interface);
171 
172  //Clear transmit status register
173  ETH->TXSTATUS = _ETH_TXSTATUS_TXUNDERRUN_MASK |
174  _ETH_TXSTATUS_TXCMPLT_MASK | _ETH_TXSTATUS_AMBAERR_MASK |
175  _ETH_TXSTATUS_TXGO_MASK | _ETH_TXSTATUS_RETRYLMTEXCD_MASK |
176  _ETH_TXSTATUS_COLOCCRD_MASK | _ETH_TXSTATUS_USEDBITREAD_MASK;
177 
178  //Clear receive status register
179  ETH->RXSTATUS = _ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
180  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK;
181 
182  //First disable all interrupts
183  ETH->IENC = 0xFFFFFFFF;
184 
185  //Only the desired ones are enabled
186  ETH->IENS = _ETH_IENS_RXOVERRUN_MASK |
187  _ETH_IENS_TXCMPLT_MASK | _ETH_IENS_AMBAERR_MASK |
188  _ETH_IENS_RTRYLMTORLATECOL_MASK | _ETH_IENS_TXUNDERRUN_MASK |
189  _ETH_IENS_RXUSEDBITREAD_MASK | _ETH_IENS_RXCMPLT_MASK;
190 
191  //Read ETH_IFCR register to clear any pending interrupt
192  status = ETH->IFCR;
193 
194  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
195  NVIC_SetPriorityGrouping(EFM32GG11_ETH_IRQ_PRIORITY_GROUPING);
196 
197  //Configure Ethernet interrupt priority
198  NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(EFM32GG11_ETH_IRQ_PRIORITY_GROUPING,
200 
201  //Enable the transmitter and the receiver
202  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_ENBTX_MASK | _ETH_NETWORKCTRL_ENBRX_MASK;
203 
204  //Accept any packets from the upper layer
205  osSetEvent(&interface->nicTxEvent);
206 
207  //Successful initialization
208  return NO_ERROR;
209 }
210 
211 
212 //EFM32 Giant Gecko 11 Starter Kit?
213 #if defined(USE_EFM32_GIANT_GECKO_11_SK)
214 
215 /**
216  * @brief GPIO configuration
217  * @param[in] interface Underlying network interface
218  **/
219 
220 void efm32gg11EthInitGpio(NetInterface *interface)
221 {
222  uint32_t temp;
223 
224  //Enable GPIO clock
225  CMU_ClockEnable(cmuClock_GPIO, true);
226  //Enable external oscillator
227  CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
228 
229  //Select CMU_CLK2 clock source
230  CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
231 
232  //Configure CMU_CLK2 (PD10)
233  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_CMU_CLK2_PORT(5),
234  AF_CMU_CLK2_PIN(5), gpioModePushPull, 0);
235 
236  //Remap CMU_CLK2 pin
237  temp = CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK;
238  CMU->ROUTELOC0 = temp | CMU_ROUTELOC0_CLKOUT2LOC_LOC5;
239 
240  //Enable CMU_CLK2 pin
241  CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
242 
243  //Select RMII operation mode and enable transceiver clock
244  ETH->CTRL = ETH_CTRL_GBLCLKEN | ETH_CTRL_MIISEL_RMII;
245 
246  //Configure ETH_RMII_TXD0 (PF7)
247  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXD0_PORT(1),
248  AF_ETH_RMIITXD0_PIN(1), gpioModePushPull, 0);
249 
250  //Configure ETH_RMII_TXD1 (PF6)
251  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXD1_PORT(1),
252  AF_ETH_RMIITXD1_PIN(1), gpioModePushPull, 0);
253 
254  //Configure ETH_RMII_TXEN (PF8)
255  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXEN_PORT(1),
256  AF_ETH_RMIITXEN_PIN(1), gpioModePushPull, 0);
257 
258  //Configure ETH_RMII_RXD0 (PD9)
259  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXD0_PORT(1),
260  AF_ETH_RMIIRXD0_PIN(1), gpioModeInput, 0);
261 
262  //Configure ETH_RMII_RXD1 (PF9)
263  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXD1_PORT(1),
264  AF_ETH_RMIIRXD1_PIN(1), gpioModeInput, 0);
265 
266  //Configure ETH_RMII_CRSDV (PD11)
267  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIICRSDV_PORT(1),
268  AF_ETH_RMIICRSDV_PIN(1), gpioModeInput, 0);
269 
270  //Configure ETH_RMII_RXER (PD12)
271  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXER_PORT(1),
272  AF_ETH_RMIIRXER_PIN(1), gpioModeInput, 0);
273 
274  //Configure ETH_MDIO (PD13)
275  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_MDIO_PORT(1),
276  AF_ETH_MDIO_PIN(1), gpioModePushPull, 0);
277 
278  //Configure ETH_MDC (PD14)
279  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_MDC_PORT(1),
280  AF_ETH_MDC_PIN(1), gpioModePushPull, 0);
281 
282  //Remap RMII pins
283  temp = ETH->ROUTELOC1 & ~(_ETH_ROUTELOC1_RMIILOC_MASK & _ETH_ROUTELOC1_MDIOLOC_MASK);
284  ETH->ROUTELOC1 = temp | (ETH_ROUTELOC1_RMIILOC_LOC1 | ETH_ROUTELOC1_MDIOLOC_LOC1);
285 
286  //Enable RMII pins
287  ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
288 
289  //Configure ETH_PWR_ENABLE (PI10)
290  GPIO_PinModeSet(gpioPortI, 10, gpioModePushPull, 0);
291  //Configure ETH_RESET_N (PH7)
292  GPIO_PinModeSet(gpioPortH, 7, gpioModePushPull, 0);
293  //Configure ETH_INTRP (PG15)
294  GPIO_PinModeSet(gpioPortG, 15, gpioModeInput, 0);
295 
296  //Power on PHY transceiver
297  GPIO_PinOutSet(gpioPortI, 10);
298  sleep(10);
299 
300  //Reset PHY transceiver (hard reset)
301  GPIO_PinOutClear(gpioPortH, 7);
302  sleep(10);
303  GPIO_PinOutSet(gpioPortH, 7);
304  sleep(10);
305 }
306 
307 #endif
308 
309 
310 /**
311  * @brief Initialize buffer descriptors
312  * @param[in] interface Underlying network interface
313  **/
314 
316 {
317  uint_t i;
318  uint32_t address;
319 
320  //Initialize TX buffer descriptors
321  for(i = 0; i < EFM32GG11_ETH_TX_BUFFER_COUNT; i++)
322  {
323  //Calculate the address of the current TX buffer
324  address = (uint32_t) txBuffer[i];
325  //Write the address to the descriptor entry
326  txBufferDesc[i].address = address;
327  //Initialize status field
328  txBufferDesc[i].status = ETH_TX_USED;
329  }
330 
331  //Mark the last descriptor entry with the wrap flag
332  txBufferDesc[i - 1].status |= ETH_TX_WRAP;
333  //Initialize TX buffer index
334  txBufferIndex = 0;
335 
336  //Initialize RX buffer descriptors
337  for(i = 0; i < EFM32GG11_ETH_RX_BUFFER_COUNT; i++)
338  {
339  //Calculate the address of the current RX buffer
340  address = (uint32_t) rxBuffer[i];
341  //Write the address to the descriptor entry
342  rxBufferDesc[i].address = address & ETH_RX_ADDRESS;
343  //Clear status field
344  rxBufferDesc[i].status = 0;
345  }
346 
347  //Mark the last descriptor entry with the wrap flag
348  rxBufferDesc[i - 1].address |= ETH_RX_WRAP;
349  //Initialize RX buffer index
350  rxBufferIndex = 0;
351 
352  //Start location of the TX descriptor list
353  ETH->TXQPTR = (uint32_t) txBufferDesc;
354  //Start location of the RX descriptor list
355  ETH->RXQPTR = (uint32_t) rxBufferDesc;
356 }
357 
358 
359 /**
360  * @brief EFM32GG11 Ethernet MAC timer handler
361  *
362  * This routine is periodically called by the TCP/IP stack to
363  * handle periodic operations such as polling the link state
364  *
365  * @param[in] interface Underlying network interface
366  **/
367 
369 {
370  //Handle periodic operations
371  interface->phyDriver->tick(interface);
372 }
373 
374 
375 /**
376  * @brief Enable interrupts
377  * @param[in] interface Underlying network interface
378  **/
379 
381 {
382  //Enable Ethernet MAC interrupts
383  NVIC_EnableIRQ(ETH_IRQn);
384  //Enable Ethernet PHY interrupts
385  interface->phyDriver->enableIrq(interface);
386 }
387 
388 
389 /**
390  * @brief Disable interrupts
391  * @param[in] interface Underlying network interface
392  **/
393 
395 {
396  //Disable Ethernet MAC interrupts
397  NVIC_DisableIRQ(ETH_IRQn);
398  //Disable Ethernet PHY interrupts
399  interface->phyDriver->disableIrq(interface);
400 }
401 
402 
403 /**
404  * @brief EFM32GG11 Ethernet MAC interrupt service routine
405  **/
406 
407 void ETH_IRQHandler(void)
408 {
409  bool_t flag;
410  volatile uint32_t isr;
411  volatile uint32_t tsr;
412  volatile uint32_t rsr;
413 
414  //Enter interrupt service routine
415  osEnterIsr();
416 
417  //This flag will be set if a higher priority task must be woken
418  flag = FALSE;
419 
420  //Each time the software reads ETH_IFCR, it has to check the contents
421  //of ETH_TXSTATUS, ETH_RXSTATUS and ETH_NETWORKSTATUS
422  isr = ETH->IFCR;
423  tsr = ETH->TXSTATUS;
424  rsr = ETH->RXSTATUS;
425 
426  //Clear interrupt flags
427  ETH->IFCR = isr;
428 
429  //A packet has been transmitted?
430  if(tsr & (_ETH_TXSTATUS_TXUNDERRUN_MASK |
431  _ETH_TXSTATUS_TXCMPLT_MASK | _ETH_TXSTATUS_AMBAERR_MASK |
432  _ETH_TXSTATUS_TXGO_MASK | _ETH_TXSTATUS_RETRYLMTEXCD_MASK |
433  _ETH_TXSTATUS_COLOCCRD_MASK | _ETH_TXSTATUS_USEDBITREAD_MASK))
434  {
435  //Only clear TXSTATUS flags that are currently set
436  ETH->TXSTATUS = tsr;
437 
438  //Check whether the TX buffer is available for writing
439  if(txBufferDesc[txBufferIndex].status & ETH_TX_USED)
440  {
441  //Notify the TCP/IP stack that the transmitter is ready to send
442  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
443  }
444  }
445 
446  //A packet has been received?
447  if(rsr & (_ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
448  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK))
449  {
450  //Set event flag
451  nicDriverInterface->nicEvent = TRUE;
452  //Notify the TCP/IP stack of the event
453  flag |= osSetEventFromIsr(&netEvent);
454  }
455 
456  //Leave interrupt service routine
457  osExitIsr(flag);
458 }
459 
460 
461 /**
462  * @brief EFM32GG11 Ethernet MAC event handler
463  * @param[in] interface Underlying network interface
464  **/
465 
467 {
468  error_t error;
469  uint32_t rsr;
470 
471  //Read receive status
472  rsr = ETH->RXSTATUS;
473 
474  //Packet received?
475  if(rsr & (_ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
476  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK))
477  {
478  //Only clear RXSTATUS flags that are currently set
479  ETH->RXSTATUS = rsr;
480 
481  //Process all pending packets
482  do
483  {
484  //Read incoming packet
485  error = efm32gg11EthReceivePacket(interface);
486 
487  //No more data in the receive buffer?
488  } while(error != ERROR_BUFFER_EMPTY);
489  }
490 }
491 
492 
493 /**
494  * @brief Send a packet
495  * @param[in] interface Underlying network interface
496  * @param[in] buffer Multi-part buffer containing the data to send
497  * @param[in] offset Offset to the first data byte
498  * @return Error code
499  **/
500 
502  const NetBuffer *buffer, size_t offset)
503 {
504  size_t length;
505 
506  //Retrieve the length of the packet
507  length = netBufferGetLength(buffer) - offset;
508 
509  //Check the frame length
511  {
512  //The transmitter can accept another packet
513  osSetEvent(&interface->nicTxEvent);
514  //Report an error
515  return ERROR_INVALID_LENGTH;
516  }
517 
518  //Make sure the current buffer is available for writing
519  if(!(txBufferDesc[txBufferIndex].status & ETH_TX_USED))
520  return ERROR_FAILURE;
521 
522  //Copy user data to the transmit buffer
523  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
524 
525  //Set the necessary flags in the descriptor entry
526  if(txBufferIndex < (EFM32GG11_ETH_TX_BUFFER_COUNT - 1))
527  {
528  //Write the status word
529  txBufferDesc[txBufferIndex].status = ETH_TX_LAST |
530  (length & ETH_TX_LENGTH);
531 
532  //Point to the next buffer
533  txBufferIndex++;
534  }
535  else
536  {
537  //Write the status word
538  txBufferDesc[txBufferIndex].status = ETH_TX_WRAP | ETH_TX_LAST |
539  (length & ETH_TX_LENGTH);
540 
541  //Wrap around
542  txBufferIndex = 0;
543  }
544 
545  //Set the TSTART bit to initiate transmission
546  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_TXSTRT_MASK;
547 
548  //Check whether the next buffer is available for writing
549  if(txBufferDesc[txBufferIndex].status & ETH_TX_USED)
550  {
551  //The transmitter can accept another packet
552  osSetEvent(&interface->nicTxEvent);
553  }
554 
555  //Successful processing
556  return NO_ERROR;
557 }
558 
559 
560 /**
561  * @brief Receive a packet
562  * @param[in] interface Underlying network interface
563  * @return Error code
564  **/
565 
567 {
568  static uint8_t temp[ETH_MAX_FRAME_SIZE];
569  error_t error;
570  uint_t i;
571  uint_t j;
572  uint_t sofIndex;
573  uint_t eofIndex;
574  size_t n;
575  size_t size;
576  size_t length;
577 
578  //Initialize SOF and EOF indices
579  sofIndex = UINT_MAX;
580  eofIndex = UINT_MAX;
581 
582  //Search for SOF and EOF flags
583  for(i = 0; i < EFM32GG11_ETH_RX_BUFFER_COUNT; i++)
584  {
585  //Point to the current entry
586  j = rxBufferIndex + i;
587 
588  //Wrap around to the beginning of the buffer if necessary
591 
592  //No more entries to process?
593  if(!(rxBufferDesc[j].address & ETH_RX_OWNERSHIP))
594  {
595  //Stop processing
596  break;
597  }
598  //A valid SOF has been found?
599  if(rxBufferDesc[j].status & ETH_RX_SOF)
600  {
601  //Save the position of the SOF
602  sofIndex = i;
603  }
604  //A valid EOF has been found?
605  if((rxBufferDesc[j].status & ETH_RX_EOF) && sofIndex != UINT_MAX)
606  {
607  //Save the position of the EOF
608  eofIndex = i;
609  //Retrieve the length of the frame
610  size = rxBufferDesc[j].status & ETH_RX_LENGTH;
611  //Limit the number of data to read
612  size = MIN(size, ETH_MAX_FRAME_SIZE);
613  //Stop processing since we have reached the end of the frame
614  break;
615  }
616  }
617 
618  //Determine the number of entries to process
619  if(eofIndex != UINT_MAX)
620  j = eofIndex + 1;
621  else if(sofIndex != UINT_MAX)
622  j = sofIndex;
623  else
624  j = i;
625 
626  //Total number of bytes that have been copied from the receive buffer
627  length = 0;
628 
629  //Process incoming frame
630  for(i = 0; i < j; i++)
631  {
632  //Any data to copy from current buffer?
633  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
634  {
635  //Calculate the number of bytes to read at a time
637  //Copy data from receive buffer
638  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
639  //Update byte counters
640  length += n;
641  size -= n;
642  }
643 
644  //Mark the current buffer as free
645  rxBufferDesc[rxBufferIndex].address &= ~ETH_RX_OWNERSHIP;
646 
647  //Point to the following entry
648  rxBufferIndex++;
649 
650  //Wrap around to the beginning of the buffer if necessary
651  if(rxBufferIndex >= EFM32GG11_ETH_RX_BUFFER_COUNT)
652  rxBufferIndex = 0;
653  }
654 
655  //Any packet to process?
656  if(length > 0)
657  {
658  //Pass the packet to the upper layer
659  nicProcessPacket(interface, temp, length);
660  //Valid packet received
661  error = NO_ERROR;
662  }
663  else
664  {
665  //No more data in the receive buffer
666  error = ERROR_BUFFER_EMPTY;
667  }
668 
669  //Return status code
670  return error;
671 }
672 
673 
674 /**
675  * @brief Configure MAC address filtering
676  * @param[in] interface Underlying network interface
677  * @return Error code
678  **/
679 
681 {
682  uint_t i;
683  uint_t j;
684  uint_t k;
685  uint8_t *p;
686  uint32_t hashTable[2];
687  MacAddr unicastMacAddr[3];
688  MacFilterEntry *entry;
689 
690  //Debug message
691  TRACE_DEBUG("Updating MAC filter...\r\n");
692 
693  //The MAC supports 3 additional addresses for unicast perfect filtering
694  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
695  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
696  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
697 
698  //The hash table is used for multicast address filtering
699  hashTable[0] = 0;
700  hashTable[1] = 0;
701 
702  //The MAC address filter contains the list of MAC addresses to accept
703  //when receiving an Ethernet frame
704  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
705  {
706  //Point to the current entry
707  entry = &interface->macAddrFilter[i];
708 
709  //Valid entry?
710  if(entry->refCount > 0)
711  {
712  //Multicast address?
713  if(macIsMulticastAddr(&entry->addr))
714  {
715  //Point to the MAC address
716  p = entry->addr.b;
717 
718  //Apply the hash function
719  k = (p[0] >> 6) ^ p[0];
720  k ^= (p[1] >> 4) ^ (p[1] << 2);
721  k ^= (p[2] >> 2) ^ (p[2] << 4);
722  k ^= (p[3] >> 6) ^ p[3];
723  k ^= (p[4] >> 4) ^ (p[4] << 2);
724  k ^= (p[5] >> 2) ^ (p[5] << 4);
725 
726  //The hash value is reduced to a 6-bit index
727  k &= 0x3F;
728 
729  //Update hash table contents
730  hashTable[k / 32] |= (1 << (k % 32));
731  }
732  else
733  {
734  //Up to 3 additional MAC addresses can be specified
735  if(j < 3)
736  {
737  //Save the unicast address
738  unicastMacAddr[j++] = entry->addr;
739  }
740  }
741  }
742  }
743 
744  //Configure the first unicast address filter
745  if(j >= 1)
746  {
747  //The address is activated when SAT register is written
748  ETH->SPECADDR2BOTTOM = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
749  ETH->SPECADDR2TOP = unicastMacAddr[0].w[2];
750  }
751  else
752  {
753  //The address is deactivated when SAB register is written
754  ETH->SPECADDR2BOTTOM = 0;
755  }
756 
757  //Configure the second unicast address filter
758  if(j >= 2)
759  {
760  //The address is activated when SAT register is written
761  ETH->SPECADDR3BOTTOM = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
762  ETH->SPECADDR3TOP = unicastMacAddr[1].w[2];
763  }
764  else
765  {
766  //The address is deactivated when SAB register is written
767  ETH->SPECADDR3BOTTOM = 0;
768  }
769 
770  //Configure the third unicast address filter
771  if(j >= 3)
772  {
773  //The address is activated when SAT register is written
774  ETH->SPECADDR4BOTTOM = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
775  ETH->SPECADDR4TOP = unicastMacAddr[2].w[2];
776  }
777  else
778  {
779  //The address is deactivated when SAB register is written
780  ETH->SPECADDR4BOTTOM = 0;
781  }
782 
783  //Configure the multicast address filter
784  ETH->HASHBOTTOM = hashTable[0];
785  ETH->HASHTOP = hashTable[1];
786 
787  //Debug message
788  TRACE_DEBUG(" HASHBOTTOM = %08" PRIX32 "\r\n", ETH->HASHBOTTOM);
789  TRACE_DEBUG(" HASHTOP = %08" PRIX32 "\r\n", ETH->HASHTOP);
790 
791  //Successful processing
792  return NO_ERROR;
793 }
794 
795 
796 /**
797  * @brief Adjust MAC configuration parameters for proper operation
798  * @param[in] interface Underlying network interface
799  * @return Error code
800  **/
801 
803 {
804  uint32_t config;
805 
806  //Read network configuration register
807  config = ETH->NETWORKCFG;
808 
809  //10BASE-T or 100BASE-TX operation mode?
810  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
811  config |= _ETH_NETWORKCFG_SPEED_MASK;
812  else
813  config &= ~_ETH_NETWORKCFG_SPEED_MASK;
814 
815  //Half-duplex or full-duplex mode?
816  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
817  config |= _ETH_NETWORKCFG_FULLDUPLEX_MASK;
818  else
819  config &= ~_ETH_NETWORKCFG_FULLDUPLEX_MASK;
820 
821  //Write configuration value back to ETH_NETWORKCFG register
822  ETH->NETWORKCFG = config;
823 
824  //Successful processing
825  return NO_ERROR;
826 }
827 
828 
829 /**
830  * @brief Write PHY register
831  * @param[in] phyAddr PHY address
832  * @param[in] regAddr Register address
833  * @param[in] data Register value
834  **/
835 
836 void efm32gg11EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
837 {
838  uint32_t value;
839 
840  //Set up a write operation
841  value = _ETH_PHYMNGMNT_WRITE1_MASK;
842  value |= (1 << _ETH_PHYMNGMNT_OPERATION_SHIFT) & _ETH_PHYMNGMNT_OPERATION_MASK;
843  value |= (2 << _ETH_PHYMNGMNT_WRITE10_SHIFT) & _ETH_PHYMNGMNT_WRITE10_MASK;
844 
845  //PHY address
846  value |= (phyAddr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) & _ETH_PHYMNGMNT_PHYADDR_MASK;
847  //Register address
848  value |= (regAddr << _ETH_PHYMNGMNT_REGADDR_SHIFT) & _ETH_PHYMNGMNT_REGADDR_MASK;
849  //Register value
850  value |= data & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
851 
852  //Start a write operation
853  ETH->PHYMNGMNT = value;
854  //Wait for the write to complete
855  while(!(ETH->NETWORKSTATUS & _ETH_NETWORKSTATUS_MANDONE_MASK));
856 }
857 
858 
859 /**
860  * @brief Read PHY register
861  * @param[in] phyAddr PHY address
862  * @param[in] regAddr Register address
863  * @return Register value
864  **/
865 
866 uint16_t efm32gg11EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
867 {
868  uint32_t value;
869 
870  //Set up a read operation
871  value = _ETH_PHYMNGMNT_WRITE1_MASK;
872  value |= (2 << _ETH_PHYMNGMNT_OPERATION_SHIFT) & _ETH_PHYMNGMNT_OPERATION_MASK;
873  value |= (2 << _ETH_PHYMNGMNT_WRITE10_SHIFT) & _ETH_PHYMNGMNT_WRITE10_MASK;
874 
875  //PHY address
876  value |= (phyAddr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) & _ETH_PHYMNGMNT_PHYADDR_MASK;
877  //Register address
878  value |= (regAddr << _ETH_PHYMNGMNT_REGADDR_SHIFT) & _ETH_PHYMNGMNT_REGADDR_MASK;
879 
880  //Start a read operation
881  ETH->PHYMNGMNT = value;
882  //Wait for the read to complete
883  while(!(ETH->NETWORKSTATUS & _ETH_NETWORKSTATUS_MANDONE_MASK));
884 
885  //Return PHY register contents
886  return ETH->PHYMNGMNT & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
887 }
#define EFM32GG11_ETH_RX_BUFFER_COUNT
uint16_t efm32gg11EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
MacAddr addr
MAC address.
Definition: ethernet.h:222
error_t efm32gg11EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
const NicDriver efm32gg11EthDriver
EFM32GG11 Ethernet MAC driver.
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:297
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define EFM32GG11_ETH_TX_BUFFER_SIZE
error_t efm32gg11EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ETH_RX_LENGTH
void efm32gg11EthDisableIrq(NetInterface *interface)
Disable interrupts.
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
void efm32gg11EthTick(NetInterface *interface)
EFM32GG11 Ethernet MAC timer handler.
#define txBuffer
void efm32gg11EthEventHandler(NetInterface *interface)
EFM32GG11 Ethernet MAC event handler.
#define ETH_TX_LAST
#define EFM32GG11_ETH_IRQ_SUB_PRIORITY
void efm32gg11EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define EFM32GG11_ETH_IRQ_PRIORITY_GROUPING
#define ETH_TX_USED
#define sleep(delay)
Definition: os_port.h:128
#define ETH_RX_ADDRESS
#define EFM32GG11_ETH_RX_BUFFER_SIZE
#define EFM32GG11_ETH_IRQ_GROUP_PRIORITY
#define TRUE
Definition: os_port.h:50
#define ETH_RX_WRAP
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define EFM32GG11_ETH_TX_BUFFER_COUNT
Transmit buffer descriptor.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void efm32gg11EthInitGpio(NetInterface *interface)
error_t efm32gg11EthInit(NetInterface *interface)
EFM32GG11 Ethernet MAC initialization.
NIC driver.
Definition: nic.h:164
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void efm32gg11EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MIN(a, b)
Definition: os_port.h:62
Receive buffer descriptor.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void ETH_IRQHandler(void)
EFM32GG11 Ethernet MAC interrupt service routine.
#define ETH_TX_LENGTH
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
#define ETH_RX_EOF
#define TRACE_INFO(...)
Definition: debug.h:94
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:71
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:76
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
#define ETH_RX_OWNERSHIP
#define ETH_TX_WRAP
unsigned int uint_t
Definition: compiler_port.h:45
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define ETH_RX_SOF
#define osExitIsr(flag)
EFM32 Giant Gecko 11 Ethernet MAC controller.
void efm32gg11EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t efm32gg11EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define osEnterIsr()
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
error_t efm32gg11EthReceivePacket(NetInterface *interface)
Receive a packet.
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106