f28m35x_eth_driver.c
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1 /**
2  * @file f28m35x_eth_driver.c
3  * @brief F28M35x Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "inc/hw_ethernet.h"
34 #include "inc/hw_ints.h"
35 #include "inc/hw_memmap.h"
36 #include "inc/hw_types.h"
37 #include "driverlib/gpio.h"
38 #include "driverlib/interrupt.h"
39 #include "driverlib/sysctl.h"
40 #include "core/net.h"
42 #include "debug.h"
43 
44 //Underlying network interface
45 static NetInterface *nicDriverInterface;
46 
47 //IAR EWARM compiler?
48 #if defined(__ICCARM__)
49 
50 //Transmit buffer
51 #pragma data_alignment = 4
52 static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2];
53 //Receive buffer
54 #pragma data_alignment = 4
55 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE];
56 
57 //Keil MDK-ARM or GCC compiler?
58 #else
59 
60 //Transmit buffer
61 static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2] __attribute__((aligned(4)));
62 //Receive buffer
63 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE] __attribute__((aligned(4)));
64 
65 #endif
66 
67 
68 /**
69  * @brief F28M35x Ethernet MAC driver
70  **/
71 
73 {
75  ETH_MTU,
86  TRUE,
87  TRUE,
88  TRUE,
89  FALSE
90 };
91 
92 
93 /**
94  * @brief F28M35x Ethernet MAC controller initialization
95  * @param[in] interface Underlying network interface
96  * @return Error code
97  **/
98 
100 {
101  error_t error;
102  uint_t div;
103 #ifdef ti_sysbios_BIOS___VERS
104  Hwi_Params hwiParams;
105 #endif
106 
107  //Debug message
108  TRACE_INFO("Initializing F28M35x Ethernet MAC controller...\r\n");
109 
110  //Save underlying network interface
111  nicDriverInterface = interface;
112 
113  //Enable Ethernet controller clock
114  SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH);
115  //Reset Ethernet controller
116  SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);
117 
118  //GPIO configuration
119  f28m35xEthInitGpio(interface);
120 
121  //The MDC clock frequency cannot exceed 2.5MHz
122  div = SysCtlClockGet(20000000) / (2 * 2500000) - 1;
123  //Adjust MDC clock frequency
124  MAC_MDV_R = div & MAC_MDV_DIV_M;
125 
126  //PHY transceiver initialization
127  error = interface->phyDriver->init(interface);
128  //Failed to initialize PHY transceiver?
129  if(error)
130  return error;
131 
132  //Set the MAC address
133  MAC_IA0_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
134  MAC_IA1_R = interface->macAddr.w[2];
135 
136  //Enable automatic CRC generation and packet padding
137  MAC_TCTL_R = MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN;
138  //Flush the receive FIFO and enable CRC verification
139  MAC_RCTL_R = MAC_RCTL_RSTFIFO | MAC_RCTL_BADCRC;
140 
141  //Configure Ethernet interrupts
142  MAC_IM_R = MAC_IM_TXEMPM | MAC_IM_RXINTM;
143 
144 #ifdef ti_sysbios_BIOS___VERS
145  //Configure Ethernet interrupt
146  Hwi_Params_init(&hwiParams);
147  hwiParams.enableInt = FALSE;
148  hwiParams.priority = F28M35X_ETH_IRQ_PRIORITY;
149 
150  //Register interrupt handler
151  Hwi_create(INT_ETH, (Hwi_FuncPtr) f28m35xEthIrqHandler, &hwiParams, NULL);
152 #else
153  //Register interrupt handler
154  IntRegister(INT_ETH, f28m35xEthIrqHandler);
155 
156  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
157  IntPriorityGroupingSet(F28M35X_ETH_IRQ_PRIORITY_GROUPING);
158  //Configure Ethernet interrupt priority
159  IntPrioritySet(INT_ETH, F28M35X_ETH_IRQ_PRIORITY);
160 #endif
161 
162  //Enable transmitter
163  MAC_TCTL_R |= MAC_TCTL_TXEN;
164  //Enable receiver
165  MAC_RCTL_R |= MAC_RCTL_RXEN;
166 
167  //Accept any packets from the upper layer
168  osSetEvent(&interface->nicTxEvent);
169 
170  //Successful initialization
171  return NO_ERROR;
172 }
173 
174 
175 //TMDXCNCDH52C1 evaluation board?
176 #if defined(USE_TMDXCNCDH52C1)
177 
178 /**
179  * @brief GPIO configuration
180  * @param[in] interface Underlying network interface
181  **/
182 
183 void f28m35xEthInitGpio(NetInterface *interface)
184 {
185  //Enable GPIO clocks
186  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
187  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
188  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
189  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
190  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
191  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
192 
193  //Configure MII_TXD3 (PC4)
194  GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
195  GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
196  GPIOPinConfigure(GPIO_PC4_MIITXD3);
197 
198  //Configure MII_MDIO (PE6)
199  GPIODirModeSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
200  GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
201  GPIOPinConfigure(GPIO_PE6_MIIMDIO);
202 
203  //Configure MII_RXD3 (PF5)
204  GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
205  GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
206  GPIOPinConfigure(GPIO_PF5_MIIRXD3);
207 
208  //Configure MII_RXD2 (PG0)
209  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
210  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
211  GPIOPinConfigure(GPIO_PG0_MIIRXD2);
212 
213  //Configure MII_RXD1 (PG1)
214  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
215  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_PIN_TYPE_STD);
216  GPIOPinConfigure(GPIO_PG1_MIIRXD1);
217 
218  //Configure MII_RXDV (PG3)
219  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
220  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
221  GPIOPinConfigure(GPIO_PG3_MIIRXDV);
222 
223  //Configure MII_TXER (PG7)
224  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
225  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
226  GPIOPinConfigure(GPIO_PG7_MIITXER);
227 
228  //Configure MII_RXD0 (PH1)
229  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
230  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_PIN_TYPE_STD);
231  GPIOPinConfigure(GPIO_PH1_MIIRXD0);
232 
233  //Configure MII_TXD2 (PH3)
234  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
235  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
236  GPIOPinConfigure(GPIO_PH3_MIITXD2);
237 
238  //Configure MII_TXD1 (PH4)
239  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
240  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
241  GPIOPinConfigure(GPIO_PH4_MIITXD1);
242 
243  //Configure MII_TXD0 (PH5)
244  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
245  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
246  GPIOPinConfigure(GPIO_PH5_MIITXD0);
247 
248  //Configure MII_TXEN (PH6)
249  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
250  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
251  GPIOPinConfigure(GPIO_PH6_MIITXEN);
252 
253  //Configure MII_TXCK (PH7)
254  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
255  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
256  GPIOPinConfigure(GPIO_PH7_MIITXCK);
257 
258  //Configure MII_RXER (PJ0)
259  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
260  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
261  GPIOPinConfigure(GPIO_PJ0_MIIRXER);
262 
263  //Configure MII_RXCK (PJ2)
264  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_2, GPIO_DIR_MODE_HW);
265  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_2, GPIO_PIN_TYPE_STD);
266  GPIOPinConfigure(GPIO_PJ2_MIIRXCK);
267 
268  //Configure MII_MDC (PJ3)
269  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
270  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
271  GPIOPinConfigure(GPIO_PJ3_MIIMDC);
272 
273  //Configure MII_COL (PJ4)
274  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
275  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
276  GPIOPinConfigure(GPIO_PJ4_MIICOL);
277 
278  //Configure MII_CRS (PJ5)
279  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
280  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
281  GPIOPinConfigure(GPIO_PJ5_MIICRS);
282 
283  //Configure MII_PHYINTR (PJ6)
284  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
285  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
286  GPIOPinConfigure(GPIO_PJ6_MIIPHYINTRn);
287 
288  //Configure MII_PHYRSTn (PJ7)
289  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
290  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
291  GPIOPinConfigure(GPIO_PJ7_MIIPHYRSTn);
292 }
293 
294 #endif
295 
296 
297 /**
298  * @brief F28M35x Ethernet MAC timer handler
299  *
300  * This routine is periodically called by the TCP/IP stack to
301  * handle periodic operations such as polling the link state
302  *
303  * @param[in] interface Underlying network interface
304  **/
305 
306 void f28m35xEthTick(NetInterface *interface)
307 {
308  //Handle periodic operations
309  interface->phyDriver->tick(interface);
310 }
311 
312 
313 /**
314  * @brief Enable interrupts
315  * @param[in] interface Underlying network interface
316  **/
317 
319 {
320 #ifdef ti_sysbios_BIOS___VERS
321  //Enable Ethernet MAC interrupts
322  Hwi_enableInterrupt(INT_ETH);
323 #else
324  //Enable Ethernet MAC interrupts
325  IntEnable(INT_ETH);
326 #endif
327 
328  //Enable Ethernet PHY interrupts
329  interface->phyDriver->enableIrq(interface);
330 }
331 
332 
333 /**
334  * @brief Disable interrupts
335  * @param[in] interface Underlying network interface
336  **/
337 
339 {
340 #ifdef ti_sysbios_BIOS___VERS
341  //Disable Ethernet MAC interrupts
342  Hwi_disableInterrupt(INT_ETH);
343 #else
344  //Disable Ethernet MAC interrupts
345  IntDisable(INT_ETH);
346 #endif
347 
348  //Disable Ethernet PHY interrupts
349  interface->phyDriver->disableIrq(interface);
350 }
351 
352 
353 /**
354  * @brief F28M35x Ethernet MAC interrupt service routine
355  **/
356 
358 {
359  bool_t flag;
360  uint32_t status;
361 
362  //Enter interrupt service routine
363  osEnterIsr();
364 
365  //This flag will be set if a higher priority task must be woken
366  flag = FALSE;
367 
368  //Read interrupt status register
369  status = MAC_RIS_R;
370 
371  //Transmit FIFO empty?
372  if(status & MAC_RIS_TXEMP)
373  {
374  //Acknowledge TXEMP interrupt
375  MAC_IACK_R = MAC_IACK_TXEMP;
376 
377  //Check whether the transmit FIFO is available for writing
378  if(!(MAC_TR_R & MAC_TR_NEWTX))
379  {
380  //Notify the TCP/IP stack that the transmitter is ready to send
381  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
382  }
383  }
384 
385  //Packet received?
386  if(status & MAC_RIS_RXINT)
387  {
388  //Disable RXINT interrupt
389  MAC_IM_R &= ~MAC_IM_RXINTM;
390 
391  //Set event flag
392  nicDriverInterface->nicEvent = TRUE;
393  //Notify the TCP/IP stack of the event
394  flag |= osSetEventFromIsr(&netEvent);
395  }
396 
397  //Leave interrupt service routine
398  osExitIsr(flag);
399 }
400 
401 
402 /**
403  * @brief F28M35x Ethernet MAC event handler
404  * @param[in] interface Underlying network interface
405  **/
406 
408 {
409  //Packet received?
410  if(MAC_RIS_R & MAC_RIS_RXINT)
411  {
412  //Acknowledge RXINT interrupt
413  MAC_IACK_R = MAC_IACK_RXINT;
414 
415  //Process all the pending packets
416  while(MAC_NP_R & MAC_NP_NPR_M)
417  {
418  //Read incoming packet
419  f28m35xEthReceivePacket(interface);
420  }
421  }
422 
423  //Re-enable Ethernet interrupts
424  MAC_IM_R = MAC_IM_TXEMPM | MAC_IM_RXINTM;
425 }
426 
427 
428 /**
429  * @brief Send a packet
430  * @param[in] interface Underlying network interface
431  * @param[in] buffer Multi-part buffer containing the data to send
432  * @param[in] offset Offset to the first data byte
433  * @return Error code
434  **/
435 
437  const NetBuffer *buffer, size_t offset)
438 {
439  size_t i;
440  size_t length;
441  uint32_t *p;
442 
443  //Retrieve the length of the packet
444  length = netBufferGetLength(buffer) - offset;
445 
446  //Check the frame length
447  if(length < sizeof(EthHeader) || length > ETH_MAX_FRAME_SIZE)
448  {
449  //The transmitter can accept another packet
450  osSetEvent(&interface->nicTxEvent);
451  //Report an error
452  return ERROR_INVALID_LENGTH;
453  }
454 
455  //Make sure the transmit FIFO is available for writing
456  if(MAC_TR_R & MAC_TR_NEWTX)
457  return ERROR_FAILURE;
458 
459  //Copy user data
460  netBufferRead(txBuffer + 2, buffer, offset, length);
461 
462  //The packet is preceded by a 16-bit length field
463  txBuffer[0] = LSB(length - sizeof(EthHeader));
464  txBuffer[1] = MSB(length - sizeof(EthHeader));
465 
466  //Point to the beginning of the packet
467  p = (uint32_t *) txBuffer;
468  //Compute the length of the packet in 32-bit words
469  length = (length + 5) / 4;
470 
471  //Copy packet to transmit FIFO
472  for(i = 0; i < length; i++)
473  MAC_DATA_R = p[i];
474 
475  //Start transmitting
476  MAC_TR_R = MAC_TR_NEWTX;
477 
478  //Data successfully written
479  return NO_ERROR;
480 }
481 
482 
483 /**
484  * @brief Receive a packet
485  * @param[in] interface Underlying network interface
486  * @return Error code
487  **/
488 
490 {
491  error_t error;
492  size_t i;
493  size_t n;
494  size_t length;
495  uint32_t data;
496  uint16_t *p;
497 
498  //Make sure the FIFO is not empty
499  if(MAC_NP_R & MAC_NP_NPR_M)
500  {
501  //Read the first word
502  data = MAC_DATA_R;
503  //Retrieve the total length of the packet
504  length = data & 0xFFFF;
505 
506  //Make sure the length field is valid
507  if(length > 2)
508  {
509  //Point to the beginning of the buffer
510  p = (uint16_t *) rxBuffer;
511 
512  //Retrieve the length of the frame
513  length -= 2;
514  //Limit the number of data to be read
516 
517  //Copy the first half word
518  if(n > 0)
519  *(p++) = (uint16_t) (data >> 16);
520 
521  //Copy data from receive FIFO
522  for(i = 2; i < n; i += 4)
523  {
524  //Read a 32-bit word from the FIFO
525  data = MAC_DATA_R;
526  //Write the 32-bit to the receive buffer
527  *(p++) = (uint16_t) data;
528  *(p++) = (uint16_t) (data >> 16);
529  }
530 
531  //Skip the remaining bytes
532  while(i < length)
533  {
534  //Read a 32-bit word from the FIFO
535  data = MAC_DATA_R;
536  //Increment byte counter
537  i += 4;
538  }
539 
540  //Valid packet received
541  error = NO_ERROR;
542  }
543  else
544  {
545  //Disable receiver
546  MAC_RCTL_R &= ~MAC_RCTL_RXEN;
547  //Flush the receive FIFO
548  MAC_RCTL_R |= MAC_RCTL_RSTFIFO;
549  //Re-enable receiver
550  MAC_RCTL_R |= MAC_RCTL_RXEN;
551 
552  //The packet is not valid
553  error = ERROR_INVALID_PACKET;
554  }
555  }
556  else
557  {
558  //No more data in the receive buffer
559  error = ERROR_BUFFER_EMPTY;
560  }
561 
562  //Check whether a valid packet has been received
563  if(!error)
564  {
565  //Pass the packet to the upper layer
566  nicProcessPacket(interface, rxBuffer, n);
567  }
568 
569  //Return status code
570  return error;
571 }
572 
573 
574 /**
575  * @brief Configure MAC address filtering
576  * @param[in] interface Underlying network interface
577  * @return Error code
578  **/
579 
581 {
582  uint_t i;
583  bool_t acceptMulticast;
584 
585  //This flag will be set if multicast addresses should be accepted
586  acceptMulticast = FALSE;
587 
588  //The MAC address filter contains the list of MAC addresses to accept
589  //when receiving an Ethernet frame
590  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
591  {
592  //Valid entry?
593  if(interface->macAddrFilter[i].refCount > 0)
594  {
595  //Accept multicast addresses
596  acceptMulticast = TRUE;
597  //We are done
598  break;
599  }
600  }
601 
602  //Enable the reception of multicast frames if necessary
603  if(acceptMulticast)
604  MAC_RCTL_R |= MAC_RCTL_AMUL;
605  else
606  MAC_RCTL_R &= ~MAC_RCTL_AMUL;
607 
608  //Successful processing
609  return NO_ERROR;
610 }
611 
612 
613 /**
614  * @brief Adjust MAC configuration parameters for proper operation
615  * @param[in] interface Underlying network interface
616  * @return Error code
617  **/
618 
620 {
621  //Half-duplex or full-duplex mode?
622  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
623  MAC_TCTL_R |= MAC_TCTL_DUPLEX;
624  else
625  MAC_TCTL_R &= ~MAC_TCTL_DUPLEX;
626 
627  //Successful processing
628  return NO_ERROR;
629 }
630 
631 
632 /**
633  * @brief Write PHY register
634  * @param[in] phyAddr PHY address
635  * @param[in] regAddr Register address
636  * @param[in] data Register value
637  **/
638 
639 void f28m35xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
640 {
641  //Set PHY address
642  MAC_MAR_R = phyAddr;
643  //Data to be written in the PHY register
644  MAC_MTXD_R = data & MAC_MTXD_MDTX_M;
645  //Start a write operation
646  MAC_MCTL_R = (regAddr << 3) | MAC_MCTL_WRITE | MAC_MCTL_START;
647 
648  //Wait for the write to complete
649  while(MAC_MCTL_R & MAC_MCTL_START);
650 }
651 
652 
653 /**
654  * @brief Read PHY register
655  * @param[in] phyAddr PHY address
656  * @param[in] regAddr Register address
657  * @return Register value
658  **/
659 
660 uint16_t f28m35xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
661 {
662  //Set PHY address
663  MAC_MAR_R = phyAddr;
664  //Start a read operation
665  MAC_MCTL_R = (regAddr << 3) | MAC_MCTL_START;
666 
667  //Wait for the read to complete
668  while(MAC_MCTL_R & MAC_MCTL_START);
669 
670  //Return PHY register contents
671  return MAC_MRXD_R & MAC_MRXD_MDRX_M;
672 }
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
__start_packed struct @114 EthHeader
Ethernet frame header.
error_t f28m35xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define MAC_TR_R
#define MAC_MTXD_R
#define MSB(x)
Definition: os_port.h:56
TCP/IP stack core.
error_t f28m35xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t f28m35xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Debugging facilities.
#define MAC_MDV_R
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
Generic error code.
Definition: error.h:43
#define MAC_TCTL_R
#define txBuffer
#define MAC_MAR_R
#define LSB(x)
Definition: os_port.h:52
#define MAC_MRXD_R
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define MAC_MCTL_R
void f28m35xEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t f28m35xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define MAC_NP_R
#define MAC_IACK_R
void f28m35xEthTick(NetInterface *interface)
F28M35x Ethernet MAC timer handler.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define MAC_IA0_R
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void f28m35xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define F28M35X_ETH_IRQ_PRIORITY
#define F28M35X_ETH_IRQ_PRIORITY_GROUPING
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
error_t f28m35xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Success.
Definition: error.h:42
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
#define MAC_RIS_R
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
error_t f28m35xEthInit(NetInterface *interface)
F28M35x Ethernet MAC controller initialization.
void f28m35xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define osExitIsr(flag)
#define MAC_DATA_R
F28M35x Ethernet MAC controller.
void f28m35xEthInitGpio(NetInterface *interface)
#define osEnterIsr()
void f28m35xEthIrqHandler(void)
F28M35x Ethernet MAC interrupt service routine.
#define MAC_IA1_R
const NicDriver f28m35xEthDriver
F28M35x Ethernet MAC driver.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define MAC_RCTL_R
void f28m35xEthEventHandler(NetInterface *interface)
F28M35x Ethernet MAC event handler.
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
#define MAC_IM_R