f28m35x_eth_driver.c
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1 /**
2  * @file f28m35x_eth_driver.c
3  * @brief F28M35x Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "inc/hw_ethernet.h"
36 #include "inc/hw_ints.h"
37 #include "inc/hw_memmap.h"
38 #include "inc/hw_types.h"
39 #include "driverlib/gpio.h"
40 #include "driverlib/interrupt.h"
41 #include "driverlib/sysctl.h"
42 #include "core/net.h"
44 #include "debug.h"
45 
46 //Underlying network interface
47 static NetInterface *nicDriverInterface;
48 
49 //IAR EWARM compiler?
50 #if defined(__ICCARM__)
51 
52 //Transmit buffer
53 #pragma data_alignment = 4
54 static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2];
55 //Receive buffer
56 #pragma data_alignment = 4
57 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE];
58 
59 //Keil MDK-ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
63 static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2] __attribute__((aligned(4)));
64 //Receive buffer
65 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE] __attribute__((aligned(4)));
66 
67 #endif
68 
69 
70 /**
71  * @brief F28M35x Ethernet MAC driver
72  **/
73 
75 {
77  ETH_MTU,
88  TRUE,
89  TRUE,
90  TRUE,
91  FALSE
92 };
93 
94 
95 /**
96  * @brief F28M35x Ethernet MAC controller initialization
97  * @param[in] interface Underlying network interface
98  * @return Error code
99  **/
100 
102 {
103  error_t error;
104  uint_t div;
105 #ifdef ti_sysbios_BIOS___VERS
106  Hwi_Params hwiParams;
107 #endif
108 
109  //Debug message
110  TRACE_INFO("Initializing F28M35x Ethernet MAC controller...\r\n");
111 
112  //Save underlying network interface
113  nicDriverInterface = interface;
114 
115  //Enable Ethernet controller clock
116  SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH);
117  //Reset Ethernet controller
118  SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);
119 
120  //GPIO configuration
121  f28m35xEthInitGpio(interface);
122 
123  //The MDC clock frequency cannot exceed 2.5MHz
124  div = SysCtlClockGet(20000000) / (2 * 2500000) - 1;
125  //Adjust MDC clock frequency
126  MAC_MDV_R = div & MAC_MDV_DIV_M;
127 
128  //PHY transceiver initialization
129  error = interface->phyDriver->init(interface);
130  //Failed to initialize PHY transceiver?
131  if(error)
132  return error;
133 
134  //Set the MAC address of the station
135  MAC_IA0_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
136  MAC_IA1_R = interface->macAddr.w[2];
137 
138  //Enable automatic CRC generation and packet padding
139  MAC_TCTL_R = MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN;
140  //Flush the receive FIFO and enable CRC verification
141  MAC_RCTL_R = MAC_RCTL_RSTFIFO | MAC_RCTL_BADCRC;
142 
143  //Configure Ethernet interrupts
144  MAC_IM_R = MAC_IM_TXEMPM | MAC_IM_RXINTM;
145 
146 #ifdef ti_sysbios_BIOS___VERS
147  //Configure Ethernet interrupt
148  Hwi_Params_init(&hwiParams);
149  hwiParams.enableInt = FALSE;
150  hwiParams.priority = F28M35X_ETH_IRQ_PRIORITY;
151 
152  //Register interrupt handler
153  Hwi_create(INT_ETH, (Hwi_FuncPtr) f28m35xEthIrqHandler, &hwiParams, NULL);
154 #else
155  //Register interrupt handler
156  IntRegister(INT_ETH, f28m35xEthIrqHandler);
157 
158  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
159  IntPriorityGroupingSet(F28M35X_ETH_IRQ_PRIORITY_GROUPING);
160  //Configure Ethernet interrupt priority
161  IntPrioritySet(INT_ETH, F28M35X_ETH_IRQ_PRIORITY);
162 #endif
163 
164  //Enable transmitter
165  MAC_TCTL_R |= MAC_TCTL_TXEN;
166  //Enable receiver
167  MAC_RCTL_R |= MAC_RCTL_RXEN;
168 
169  //Accept any packets from the upper layer
170  osSetEvent(&interface->nicTxEvent);
171 
172  //Successful initialization
173  return NO_ERROR;
174 }
175 
176 
177 //TMDXCNCDH52C1 evaluation board?
178 #if defined(USE_TMDXCNCDH52C1)
179 
180 /**
181  * @brief GPIO configuration
182  * @param[in] interface Underlying network interface
183  **/
184 
185 void f28m35xEthInitGpio(NetInterface *interface)
186 {
187  //Enable GPIO clocks
188  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
189  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
190  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
191  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
192  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
193  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
194 
195  //Configure MII_TXD3 (PC4)
196  GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
197  GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
198  GPIOPinConfigure(GPIO_PC4_MIITXD3);
199 
200  //Configure MII_MDIO (PE6)
201  GPIODirModeSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
202  GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
203  GPIOPinConfigure(GPIO_PE6_MIIMDIO);
204 
205  //Configure MII_RXD3 (PF5)
206  GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
207  GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
208  GPIOPinConfigure(GPIO_PF5_MIIRXD3);
209 
210  //Configure MII_RXD2 (PG0)
211  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
212  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
213  GPIOPinConfigure(GPIO_PG0_MIIRXD2);
214 
215  //Configure MII_RXD1 (PG1)
216  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
217  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_PIN_TYPE_STD);
218  GPIOPinConfigure(GPIO_PG1_MIIRXD1);
219 
220  //Configure MII_RXDV (PG3)
221  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
222  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
223  GPIOPinConfigure(GPIO_PG3_MIIRXDV);
224 
225  //Configure MII_TXER (PG7)
226  GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
227  GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
228  GPIOPinConfigure(GPIO_PG7_MIITXER);
229 
230  //Configure MII_RXD0 (PH1)
231  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
232  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_PIN_TYPE_STD);
233  GPIOPinConfigure(GPIO_PH1_MIIRXD0);
234 
235  //Configure MII_TXD2 (PH3)
236  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
237  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
238  GPIOPinConfigure(GPIO_PH3_MIITXD2);
239 
240  //Configure MII_TXD1 (PH4)
241  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
242  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
243  GPIOPinConfigure(GPIO_PH4_MIITXD1);
244 
245  //Configure MII_TXD0 (PH5)
246  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
247  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
248  GPIOPinConfigure(GPIO_PH5_MIITXD0);
249 
250  //Configure MII_TXEN (PH6)
251  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
252  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
253  GPIOPinConfigure(GPIO_PH6_MIITXEN);
254 
255  //Configure MII_TXCK (PH7)
256  GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
257  GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
258  GPIOPinConfigure(GPIO_PH7_MIITXCK);
259 
260  //Configure MII_RXER (PJ0)
261  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
262  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
263  GPIOPinConfigure(GPIO_PJ0_MIIRXER);
264 
265  //Configure MII_RXCK (PJ2)
266  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_2, GPIO_DIR_MODE_HW);
267  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_2, GPIO_PIN_TYPE_STD);
268  GPIOPinConfigure(GPIO_PJ2_MIIRXCK);
269 
270  //Configure MII_MDC (PJ3)
271  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
272  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
273  GPIOPinConfigure(GPIO_PJ3_MIIMDC);
274 
275  //Configure MII_COL (PJ4)
276  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
277  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
278  GPIOPinConfigure(GPIO_PJ4_MIICOL);
279 
280  //Configure MII_CRS (PJ5)
281  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
282  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
283  GPIOPinConfigure(GPIO_PJ5_MIICRS);
284 
285  //Configure MII_PHYINTR (PJ6)
286  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
287  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
288  GPIOPinConfigure(GPIO_PJ6_MIIPHYINTRn);
289 
290  //Configure MII_PHYRSTn (PJ7)
291  GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
292  GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
293  GPIOPinConfigure(GPIO_PJ7_MIIPHYRSTn);
294 }
295 
296 #endif
297 
298 
299 /**
300  * @brief F28M35x Ethernet MAC timer handler
301  *
302  * This routine is periodically called by the TCP/IP stack to
303  * handle periodic operations such as polling the link state
304  *
305  * @param[in] interface Underlying network interface
306  **/
307 
308 void f28m35xEthTick(NetInterface *interface)
309 {
310  //Handle periodic operations
311  interface->phyDriver->tick(interface);
312 }
313 
314 
315 /**
316  * @brief Enable interrupts
317  * @param[in] interface Underlying network interface
318  **/
319 
321 {
322 #ifdef ti_sysbios_BIOS___VERS
323  //Enable Ethernet MAC interrupts
324  Hwi_enableInterrupt(INT_ETH);
325 #else
326  //Enable Ethernet MAC interrupts
327  IntEnable(INT_ETH);
328 #endif
329 
330  //Enable Ethernet PHY interrupts
331  interface->phyDriver->enableIrq(interface);
332 }
333 
334 
335 /**
336  * @brief Disable interrupts
337  * @param[in] interface Underlying network interface
338  **/
339 
341 {
342 #ifdef ti_sysbios_BIOS___VERS
343  //Disable Ethernet MAC interrupts
344  Hwi_disableInterrupt(INT_ETH);
345 #else
346  //Disable Ethernet MAC interrupts
347  IntDisable(INT_ETH);
348 #endif
349 
350  //Disable Ethernet PHY interrupts
351  interface->phyDriver->disableIrq(interface);
352 }
353 
354 
355 /**
356  * @brief F28M35x Ethernet MAC interrupt service routine
357  **/
358 
360 {
361  bool_t flag;
362  uint32_t status;
363 
364  //Interrupt service routine prologue
365  osEnterIsr();
366 
367  //This flag will be set if a higher priority task must be woken
368  flag = FALSE;
369 
370  //Read interrupt status register
371  status = MAC_RIS_R;
372 
373  //Transmit FIFO empty?
374  if(status & MAC_RIS_TXEMP)
375  {
376  //Acknowledge TXEMP interrupt
377  MAC_IACK_R = MAC_IACK_TXEMP;
378 
379  //Check whether the transmit FIFO is available for writing
380  if(!(MAC_TR_R & MAC_TR_NEWTX))
381  {
382  //Notify the TCP/IP stack that the transmitter is ready to send
383  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
384  }
385  }
386 
387  //Packet received?
388  if(status & MAC_RIS_RXINT)
389  {
390  //Disable RXINT interrupt
391  MAC_IM_R &= ~MAC_IM_RXINTM;
392 
393  //Set event flag
394  nicDriverInterface->nicEvent = TRUE;
395  //Notify the TCP/IP stack of the event
396  flag |= osSetEventFromIsr(&netEvent);
397  }
398 
399  //Interrupt service routine epilogue
400  osExitIsr(flag);
401 }
402 
403 
404 /**
405  * @brief F28M35x Ethernet MAC event handler
406  * @param[in] interface Underlying network interface
407  **/
408 
410 {
411  //Packet received?
412  if(MAC_RIS_R & MAC_RIS_RXINT)
413  {
414  //Acknowledge RXINT interrupt
415  MAC_IACK_R = MAC_IACK_RXINT;
416 
417  //Process all the pending packets
418  while(MAC_NP_R & MAC_NP_NPR_M)
419  {
420  //Read incoming packet
421  f28m35xEthReceivePacket(interface);
422  }
423  }
424 
425  //Re-enable Ethernet interrupts
426  MAC_IM_R = MAC_IM_TXEMPM | MAC_IM_RXINTM;
427 }
428 
429 
430 /**
431  * @brief Send a packet
432  * @param[in] interface Underlying network interface
433  * @param[in] buffer Multi-part buffer containing the data to send
434  * @param[in] offset Offset to the first data byte
435  * @return Error code
436  **/
437 
439  const NetBuffer *buffer, size_t offset)
440 {
441  size_t i;
442  size_t length;
443  uint32_t *p;
444 
445  //Retrieve the length of the packet
446  length = netBufferGetLength(buffer) - offset;
447 
448  //Check the frame length
449  if(length < sizeof(EthHeader) || length > ETH_MAX_FRAME_SIZE)
450  {
451  //The transmitter can accept another packet
452  osSetEvent(&interface->nicTxEvent);
453  //Report an error
454  return ERROR_INVALID_LENGTH;
455  }
456 
457  //Make sure the transmit FIFO is available for writing
458  if(MAC_TR_R & MAC_TR_NEWTX)
459  return ERROR_FAILURE;
460 
461  //Copy user data
462  netBufferRead(txBuffer + 2, buffer, offset, length);
463 
464  //The packet is preceded by a 16-bit length field
465  txBuffer[0] = LSB(length - sizeof(EthHeader));
466  txBuffer[1] = MSB(length - sizeof(EthHeader));
467 
468  //Point to the beginning of the packet
469  p = (uint32_t *) txBuffer;
470  //Compute the length of the packet in 32-bit words
471  length = (length + 5) / 4;
472 
473  //Copy packet to transmit FIFO
474  for(i = 0; i < length; i++)
475  MAC_DATA_R = p[i];
476 
477  //Start transmitting
478  MAC_TR_R = MAC_TR_NEWTX;
479 
480  //Data successfully written
481  return NO_ERROR;
482 }
483 
484 
485 /**
486  * @brief Receive a packet
487  * @param[in] interface Underlying network interface
488  * @return Error code
489  **/
490 
492 {
493  error_t error;
494  size_t i;
495  size_t n;
496  size_t length;
497  uint32_t data;
498  uint16_t *p;
499 
500  //Make sure the FIFO is not empty
501  if(MAC_NP_R & MAC_NP_NPR_M)
502  {
503  //Read the first word
504  data = MAC_DATA_R;
505  //Retrieve the total length of the packet
506  length = data & 0xFFFF;
507 
508  //Make sure the length field is valid
509  if(length > 2)
510  {
511  //Point to the beginning of the buffer
512  p = (uint16_t *) rxBuffer;
513 
514  //Retrieve the length of the frame
515  length -= 2;
516  //Limit the number of data to be read
518 
519  //Copy the first half word
520  if(n > 0)
521  *(p++) = (uint16_t) (data >> 16);
522 
523  //Copy data from receive FIFO
524  for(i = 2; i < n; i += 4)
525  {
526  //Read a 32-bit word from the FIFO
527  data = MAC_DATA_R;
528  //Write the 32-bit to the receive buffer
529  *(p++) = (uint16_t) data;
530  *(p++) = (uint16_t) (data >> 16);
531  }
532 
533  //Skip the remaining bytes
534  while(i < length)
535  {
536  //Read a 32-bit word from the FIFO
537  data = MAC_DATA_R;
538  //Increment byte counter
539  i += 4;
540  }
541 
542  //Valid packet received
543  error = NO_ERROR;
544  }
545  else
546  {
547  //Disable receiver
548  MAC_RCTL_R &= ~MAC_RCTL_RXEN;
549  //Flush the receive FIFO
550  MAC_RCTL_R |= MAC_RCTL_RSTFIFO;
551  //Re-enable receiver
552  MAC_RCTL_R |= MAC_RCTL_RXEN;
553 
554  //The packet is not valid
555  error = ERROR_INVALID_PACKET;
556  }
557  }
558  else
559  {
560  //No more data in the receive buffer
561  error = ERROR_BUFFER_EMPTY;
562  }
563 
564  //Check whether a valid packet has been received
565  if(!error)
566  {
567  //Pass the packet to the upper layer
568  nicProcessPacket(interface, rxBuffer, n);
569  }
570 
571  //Return status code
572  return error;
573 }
574 
575 
576 /**
577  * @brief Configure MAC address filtering
578  * @param[in] interface Underlying network interface
579  * @return Error code
580  **/
581 
583 {
584  uint_t i;
585  bool_t acceptMulticast;
586 
587  //Debug message
588  TRACE_DEBUG("Updating MAC filter...\r\n");
589 
590  //Set the MAC address of the station
591  MAC_IA0_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
592  MAC_IA1_R = interface->macAddr.w[2];
593 
594  //This flag will be set if multicast addresses should be accepted
595  acceptMulticast = FALSE;
596 
597  //The MAC address filter contains the list of MAC addresses to accept
598  //when receiving an Ethernet frame
599  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
600  {
601  //Valid entry?
602  if(interface->macAddrFilter[i].refCount > 0)
603  {
604  //Accept multicast addresses
605  acceptMulticast = TRUE;
606  //We are done
607  break;
608  }
609  }
610 
611  //Enable the reception of multicast frames if necessary
612  if(acceptMulticast)
613  MAC_RCTL_R |= MAC_RCTL_AMUL;
614  else
615  MAC_RCTL_R &= ~MAC_RCTL_AMUL;
616 
617  //Successful processing
618  return NO_ERROR;
619 }
620 
621 
622 /**
623  * @brief Adjust MAC configuration parameters for proper operation
624  * @param[in] interface Underlying network interface
625  * @return Error code
626  **/
627 
629 {
630  //Half-duplex or full-duplex mode?
631  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
632  MAC_TCTL_R |= MAC_TCTL_DUPLEX;
633  else
634  MAC_TCTL_R &= ~MAC_TCTL_DUPLEX;
635 
636  //Successful processing
637  return NO_ERROR;
638 }
639 
640 
641 /**
642  * @brief Write PHY register
643  * @param[in] opcode Access type (2 bits)
644  * @param[in] phyAddr PHY address (5 bits)
645  * @param[in] regAddr Register address (5 bits)
646  * @param[in] data Register value
647  **/
648 
649 void f28m35xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
650  uint8_t regAddr, uint16_t data)
651 {
652  //Valid opcode?
653  if(opcode == SMI_OPCODE_WRITE)
654  {
655  //Set PHY address
656  MAC_MAR_R = phyAddr;
657  //Data to be written in the PHY register
658  MAC_MTXD_R = data & MAC_MTXD_MDTX_M;
659  //Start a write operation
660  MAC_MCTL_R = (regAddr << 3) | MAC_MCTL_WRITE | MAC_MCTL_START;
661 
662  //Wait for the write to complete
663  while(MAC_MCTL_R & MAC_MCTL_START)
664  {
665  }
666  }
667  else
668  {
669  //The MAC peripheral only supports standard Clause 22 opcodes
670  }
671 }
672 
673 
674 /**
675  * @brief Read PHY register
676  * @param[in] opcode Access type (2 bits)
677  * @param[in] phyAddr PHY address (5 bits)
678  * @param[in] regAddr Register address (5 bits)
679  * @return Register value
680  **/
681 
682 uint16_t f28m35xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
683  uint8_t regAddr)
684 {
685  uint16_t data;
686 
687  //Valid opcode?
688  if(opcode == SMI_OPCODE_READ)
689  {
690  //Set PHY address
691  MAC_MAR_R = phyAddr;
692  //Start a read operation
693  MAC_MCTL_R = (regAddr << 3) | MAC_MCTL_START;
694 
695  //Wait for the read to complete
696  while(MAC_MCTL_R & MAC_MCTL_START)
697  {
698  }
699 
700  //Get register value
701  data = MAC_MRXD_R & MAC_MRXD_MDRX_M;
702  }
703  else
704  {
705  //The MAC peripheral only supports standard Clause 22 opcodes
706  data = 0;
707  }
708 
709  //Return the value of the PHY register
710  return data;
711 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: dtls_misc.h:149
error_t f28m35xEthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define F28M35X_ETH_IRQ_PRIORITY_GROUPING
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
error_t f28m35xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define MAC_TR_R
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define MAC_RCTL_R
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t f28m35xEthInit(NetInterface *interface)
F28M35x Ethernet MAC controller initialization.
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
void f28m35xEthEventHandler(NetInterface *interface)
F28M35x Ethernet MAC event handler.
const NicDriver f28m35xEthDriver
F28M35x Ethernet MAC driver.
uint16_t f28m35xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MAC_IM_R
void f28m35xEthIrqHandler(void)
F28M35x Ethernet MAC interrupt service routine.
void f28m35xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:62
void f28m35xEthInitGpio(NetInterface *interface)
error_t f28m35xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define MAC_NP_R
#define FALSE
Definition: os_port.h:46
#define MAC_MTXD_R
error_t
Error codes.
Definition: error.h:42
#define MAC_RIS_R
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define txBuffer
@ ERROR_INVALID_PACKET
Definition: error.h:138
#define NetInterface
Definition: net.h:36
@ ERROR_INVALID_LENGTH
Definition: error.h:109
error_t f28m35xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
#define MAC_MAR_R
#define MSB(x)
Definition: os_port.h:58
#define SMI_OPCODE_READ
Definition: nic.h:63
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define LSB(x)
Definition: os_port.h:54
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
void f28m35xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MAC_DATA_R
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define MAC_IACK_R
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
#define MAC_IA1_R
F28M35x Ethernet MAC controller.
#define osEnterIsr()
#define MAC_MDV_R
void f28m35xEthEnableIrq(NetInterface *interface)
Enable interrupts.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MAC_MCTL_R
unsigned int uint_t
Definition: compiler_port.h:45
__start_packed struct @110 EthHeader
Ethernet frame header.
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
#define MAC_MRXD_R
#define F28M35X_ETH_IRQ_PRIORITY
NIC driver.
Definition: nic.h:179
#define MAC_TCTL_R
#define MAC_IA0_R
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79
void f28m35xEthTick(NetInterface *interface)
F28M35x Ethernet MAC timer handler.