lpc176x_eth_driver.c
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1 /**
2  * @file lpc176x_eth_driver.c
3  * @brief LPC1764/66/67/68/69 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "lpc17xx.h"
34 #include "core/net.h"
36 #include "debug.h"
37 
38 //Underlying network interface
39 static NetInterface *nicDriverInterface;
40 
41 //IAR EWARM compiler?
42 #if defined(__ICCARM__)
43 
44 //Transmit buffer
45 #pragma data_alignment = 4
47 //Receive buffer
48 #pragma data_alignment = 4
50 //Transmit descriptors
51 #pragma data_alignment = 4
53 //Transmit status array
54 #pragma data_alignment = 4
56 //Receive descriptors
57 #pragma data_alignment = 4
59 //Receive status array
60 #pragma data_alignment = 8
62 
63 //Keil MDK-ARM or GCC compiler?
64 #else
65 
66 //Transmit buffer
68  __attribute__((aligned(4)));
69 //Receive buffer
71  __attribute__((aligned(4)));
72 //Transmit descriptors
74  __attribute__((aligned(4)));
75 //Transmit status array
77  __attribute__((aligned(4)));
78 //Receive descriptors
80  __attribute__((aligned(4)));
81 //Receive status array
83  __attribute__((aligned(8)));
84 
85 #endif
86 
87 
88 /**
89  * @brief LPC176x Ethernet MAC driver
90  **/
91 
93 {
95  ETH_MTU,
106  TRUE,
107  TRUE,
108  TRUE,
109  FALSE
110 };
111 
112 
113 /**
114  * @brief LPC176x Ethernet MAC initialization
115  * @param[in] interface Underlying network interface
116  * @return Error code
117  **/
118 
120 {
121  error_t error;
122 
123  //Debug message
124  TRACE_INFO("Initializing LPC176x Ethernet MAC...\r\n");
125 
126  //Save underlying network interface
127  nicDriverInterface = interface;
128 
129  //Power up EMAC controller
130  LPC_SC->PCONP |= PCONP_PCENET;
131 
132  //GPIO configuration
133  lpc176xEthInitGpio(interface);
134 
135  //Reset host registers, transmit datapath and receive datapath
136  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
137 
138  //Reset EMAC controller
139  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
141 
142  //Initialize MAC related registers
143  LPC_EMAC->MAC1 = 0;
144  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
145  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
146  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
147 
148  //Select RMII mode
149  LPC_EMAC->Command = COMMAND_RMII;
150 
151  //Configure MDC clock
152  LPC_EMAC->MCFG = MCFG_CLOCK_SELECT_DIV44;
153  //Reset MII management interface
154  LPC_EMAC->MCFG |= MCFG_RESET_MII_MGMT;
155  LPC_EMAC->MCFG &= ~MCFG_RESET_MII_MGMT;
156 
157  //PHY transceiver initialization
158  error = interface->phyDriver->init(interface);
159  //Failed to initialize PHY transceiver?
160  if(error)
161  return error;
162 
163  //Initialize TX and RX descriptor arrays
164  lpc176xEthInitDesc(interface);
165 
166  //Set the MAC address
167  LPC_EMAC->SA0 = interface->macAddr.w[2];
168  LPC_EMAC->SA1 = interface->macAddr.w[1];
169  LPC_EMAC->SA2 = interface->macAddr.w[0];
170 
171  //Initialize hash table
172  LPC_EMAC->HashFilterL = 0;
173  LPC_EMAC->HashFilterH = 0;
174 
175  //Configure the receive filter
176  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
178 
179  //Program the MAXF register with the maximum frame length to be accepted
180  LPC_EMAC->MAXF = 1518;
181 
182  //Reset EMAC interrupt flags
183  LPC_EMAC->IntClear = 0xFFFF;
184  //Enable desired EMAC interrupts
185  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
186 
187  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
188  NVIC_SetPriorityGrouping(LPC176X_ETH_IRQ_PRIORITY_GROUPING);
189 
190  //Configure Ethernet interrupt priority
191  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC176X_ETH_IRQ_PRIORITY_GROUPING,
193 
194  //Enable transmission and reception
195  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
196  //Allow frames to be received
197  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
198 
199  //Accept any packets from the upper layer
200  osSetEvent(&interface->nicTxEvent);
201 
202  //Successful initialization
203  return NO_ERROR;
204 }
205 
206 
207 //LPC1766-STK evaluation board?
208 #if defined(USE_LPC1766_STK)
209 
210 /**
211  * @brief GPIO configuration
212  * @param[in] interface Underlying network interface
213  **/
214 
215 void lpc176xEthInitGpio(NetInterface *interface)
216 {
217  //Configure P1.0 (ENET_TXD0), P1.1 (ENET_TXD1), P1.4 (ENET_TX_EN), P1.8 (ENET_CRS),
218  //P1.9 (ENET_RXD0), P1.10 (ENET_RXD1), P1.14 (RX_ER) and P1.15 (ENET_REF_CLK)
219  LPC_PINCON->PINSEL2 &= ~(PINSEL2_P1_0_MASK | PINSEL2_P1_1_MASK |
220  PINSEL2_P1_4_MASK | PINSEL2_P1_8_MASK | PINSEL2_P1_9_MASK |
221  PINSEL2_P1_10_MASK | PINSEL2_P1_14_MASK | PINSEL2_P1_15_MASK);
222 
223  LPC_PINCON->PINSEL2 |= PINSEL2_P1_0_ENET_TXD0 | PINSEL2_P1_1_ENET_TXD1 |
224  PINSEL2_P1_4_ENET_TX_EN | PINSEL2_P1_8_ENET_CRS | PINSEL2_P1_9_ENET_RXD0 |
225  PINSEL2_P1_10_ENET_RXD1 | PINSEL2_P1_14_ENET_RX_ER | PINSEL2_P1_15_ENET_REF_CLK;
226 
227  //Configure P1.16 (ENET_MDC) and P1.17 (ENET_MDIO)
228  LPC_PINCON->PINSEL3 &= ~(PINSEL3_P1_16_MASK | PINSEL3_P1_17_MASK);
229  LPC_PINCON->PINSEL3 |= PINSEL3_P1_16_ENET_MDC | PINSEL3_P1_17_ENET_MDIO;
230 }
231 
232 #endif
233 
234 
235 /**
236  * @brief Initialize TX and RX descriptors
237  * @param[in] interface Underlying network interface
238  **/
239 
241 {
242  uint_t i;
243 
244  //Initialize TX descriptors
245  for(i = 0; i < LPC176X_ETH_TX_BUFFER_COUNT; i++)
246  {
247  //Base address of the buffer containing transmit data
248  txDesc[i].packet = (uint32_t) txBuffer[i];
249  //Transmit descriptor control word
250  txDesc[i].control = 0;
251  //Transmit status information word
252  txStatus[i].info = 0;
253  }
254 
255  //Initialize RX descriptors
256  for(i = 0; i < LPC176X_ETH_RX_BUFFER_COUNT; i++)
257  {
258  //Base address of the buffer for storing receive data
259  rxDesc[i].packet = (uint32_t) rxBuffer[i];
260  //Receive descriptor control word
262  //Receive status information word
263  rxStatus[i].info = 0;
264  //Receive status HashCRC word
265  rxStatus[i].hashCrc = 0;
266  }
267 
268  //Initialize EMAC transmit descriptor registers
269  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
270  LPC_EMAC->TxStatus = (uint32_t) txStatus;
271  LPC_EMAC->TxDescriptorNumber = LPC176X_ETH_TX_BUFFER_COUNT - 1;
272  LPC_EMAC->TxProduceIndex = 0;
273 
274  //Initialize EMAC receive descriptor registers
275  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
276  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
277  LPC_EMAC->RxDescriptorNumber = LPC176X_ETH_RX_BUFFER_COUNT - 1;
278  LPC_EMAC->RxConsumeIndex = 0;
279 }
280 
281 
282 /**
283  * @brief LPC176x Ethernet MAC timer handler
284  *
285  * This routine is periodically called by the TCP/IP stack to
286  * handle periodic operations such as polling the link state
287  *
288  * @param[in] interface Underlying network interface
289  **/
290 
291 void lpc176xEthTick(NetInterface *interface)
292 {
293  //Handle periodic operations
294  interface->phyDriver->tick(interface);
295 }
296 
297 
298 /**
299  * @brief Enable interrupts
300  * @param[in] interface Underlying network interface
301  **/
302 
304 {
305  //Enable Ethernet MAC interrupts
306  NVIC_EnableIRQ(ENET_IRQn);
307  //Enable Ethernet PHY interrupts
308  interface->phyDriver->enableIrq(interface);
309 }
310 
311 
312 /**
313  * @brief Disable interrupts
314  * @param[in] interface Underlying network interface
315  **/
316 
318 {
319  //Disable Ethernet MAC interrupts
320  NVIC_DisableIRQ(ENET_IRQn);
321  //Disable Ethernet PHY interrupts
322  interface->phyDriver->disableIrq(interface);
323 }
324 
325 
326 /**
327  * @brief LPC176x Ethernet MAC interrupt service routine
328  **/
329 
330 void ENET_IRQHandler(void)
331 {
332  uint_t i;
333  bool_t flag;
334  uint32_t status;
335 
336  //Enter interrupt service routine
337  osEnterIsr();
338 
339  //This flag will be set if a higher priority task must be woken
340  flag = FALSE;
341 
342  //Read interrupt status register
343  status = LPC_EMAC->IntStatus;
344 
345  //A packet has been transmitted?
346  if(status & INT_TX_DONE)
347  {
348  //Clear TxDone interrupt flag
349  LPC_EMAC->IntClear = INT_TX_DONE;
350 
351  //Get the index of the next descriptor
352  i = LPC_EMAC->TxProduceIndex + 1;
353 
354  //Wrap around if necessary
356  i = 0;
357 
358  //Check whether the TX buffer is available for writing
359  if(i != LPC_EMAC->TxConsumeIndex)
360  {
361  //Notify the TCP/IP stack that the transmitter is ready to send
362  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
363  }
364  }
365 
366  //A packet has been received?
367  if(status & INT_RX_DONE)
368  {
369  //Disable RxDone interrupts
370  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
371 
372  //Set event flag
373  nicDriverInterface->nicEvent = TRUE;
374  //Notify the TCP/IP stack of the event
375  flag |= osSetEventFromIsr(&netEvent);
376  }
377 
378  //Leave interrupt service routine
379  osExitIsr(flag);
380 }
381 
382 
383 /**
384  * @brief LPC176x Ethernet MAC event handler
385  * @param[in] interface Underlying network interface
386  **/
387 
389 {
390  error_t error;
391 
392  //Packet received?
393  if(LPC_EMAC->IntStatus & INT_RX_DONE)
394  {
395  //Clear RxDone interrupt flag
396  LPC_EMAC->IntClear = INT_RX_DONE;
397 
398  //Process all pending packets
399  do
400  {
401  //Read incoming packet
402  error = lpc176xEthReceivePacket(interface);
403 
404  //No more data in the receive buffer?
405  } while(error != ERROR_BUFFER_EMPTY);
406  }
407 
408  //Re-enable TxDone and RxDone interrupts
409  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
410 }
411 
412 
413 /**
414  * @brief Send a packet
415  * @param[in] interface Underlying network interface
416  * @param[in] buffer Multi-part buffer containing the data to send
417  * @param[in] offset Offset to the first data byte
418  * @return Error code
419  **/
420 
422  const NetBuffer *buffer, size_t offset)
423 {
424  uint_t i;
425  uint_t j;
426  size_t length;
427 
428  //Retrieve the length of the packet
429  length = netBufferGetLength(buffer) - offset;
430 
431  //Check the frame length
432  if(!length)
433  {
434  //The transmitter can accept another packet
435  osSetEvent(&interface->nicTxEvent);
436  //We are done since the buffer is empty
437  return NO_ERROR;
438  }
440  {
441  //The transmitter can accept another packet
442  osSetEvent(&interface->nicTxEvent);
443  //Report an error
444  return ERROR_INVALID_LENGTH;
445  }
446 
447  //Get the index of the current descriptor
448  i = LPC_EMAC->TxProduceIndex;
449  //Get the index of the next descriptor
450  j = i + 1;
451 
452  //Wrap around if necessary
454  j = 0;
455 
456  //Check whether the transmit descriptor array is full
457  if(j == LPC_EMAC->TxConsumeIndex)
458  return ERROR_FAILURE;
459 
460  //Copy user data to the transmit buffer
461  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
462 
463  //Write the transmit control word
464  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
466 
467  //Increment index and wrap around if necessary
468  if(++i >= LPC176X_ETH_TX_BUFFER_COUNT)
469  i = 0;
470 
471  //Save the resulting value
472  LPC_EMAC->TxProduceIndex = i;
473 
474  //Get the index of the next descriptor
475  j = i + 1;
476 
477  //Wrap around if necessary
479  j = 0;
480 
481  //Check whether the next buffer is available for writing
482  if(j != LPC_EMAC->TxConsumeIndex)
483  {
484  //The transmitter can accept another packet
485  osSetEvent(&interface->nicTxEvent);
486  }
487 
488  //Successful write operation
489  return NO_ERROR;
490 }
491 
492 
493 /**
494  * @brief Receive a packet
495  * @param[in] interface Underlying network interface
496  * @return Error code
497  **/
498 
500 {
501  error_t error;
502  size_t n;
503  uint_t i;
504 
505  //Point to the current descriptor
506  i = LPC_EMAC->RxConsumeIndex;
507 
508  //Make sure the current buffer is available for reading
509  if(i != LPC_EMAC->RxProduceIndex)
510  {
511  //Retrieve the length of the frame
512  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
513  //Limit the number of data to read
515 
516  //Pass the packet to the upper layer
517  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n);
518 
519  //Increment index and wrap around if necessary
520  if(++i >= LPC176X_ETH_RX_BUFFER_COUNT)
521  i = 0;
522 
523  //Save the resulting value
524  LPC_EMAC->RxConsumeIndex = i;
525 
526  //Valid packet received
527  error = NO_ERROR;
528  }
529  else
530  {
531  //No more data in the receive buffer
532  error = ERROR_BUFFER_EMPTY;
533  }
534 
535  //Return status code
536  return error;
537 }
538 
539 
540 /**
541  * @brief Configure MAC address filtering
542  * @param[in] interface Underlying network interface
543  * @return Error code
544  **/
545 
547 {
548  uint_t i;
549  uint_t k;
550  uint32_t crc;
551  uint32_t hashTable[2];
552  MacFilterEntry *entry;
553 
554  //Debug message
555  TRACE_DEBUG("Updating LPC176x hash table...\r\n");
556 
557  //Clear hash table
558  hashTable[0] = 0;
559  hashTable[1] = 0;
560 
561  //The MAC address filter contains the list of MAC addresses to accept
562  //when receiving an Ethernet frame
563  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
564  {
565  //Point to the current entry
566  entry = &interface->macAddrFilter[i];
567 
568  //Valid entry?
569  if(entry->refCount > 0)
570  {
571  //Compute CRC over the current MAC address
572  crc = lpc176xEthCalcCrc(&entry->addr, sizeof(MacAddr));
573  //Bits [28:23] are used to form the hash
574  k = (crc >> 23) & 0x3F;
575  //Update hash table contents
576  hashTable[k / 32] |= (1 << (k % 32));
577  }
578  }
579 
580  //Write the hash table
581  LPC_EMAC->HashFilterL = hashTable[0];
582  LPC_EMAC->HashFilterH = hashTable[1];
583 
584  //Debug message
585  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
586  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
587 
588  //Successful processing
589  return NO_ERROR;
590 }
591 
592 
593 /**
594  * @brief Adjust MAC configuration parameters for proper operation
595  * @param[in] interface Underlying network interface
596  * @return Error code
597  **/
598 
600 {
601  //10BASE-T or 100BASE-TX operation mode?
602  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
603  LPC_EMAC->SUPP = SUPP_SPEED;
604  else
605  LPC_EMAC->SUPP = 0;
606 
607  //Half-duplex or full-duplex mode?
608  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
609  {
610  //The MAC operates in full-duplex mode
611  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
612  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
613  //Configure Back-to-Back Inter-Packet Gap
614  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
615  }
616  else
617  {
618  //The MAC operates in half-duplex mode
619  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
620  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
621  //Configure Back-to-Back Inter-Packet Gap
622  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
623  }
624 
625  //Successful processing
626  return NO_ERROR;
627 }
628 
629 
630 /**
631  * @brief Write PHY register
632  * @param[in] phyAddr PHY address
633  * @param[in] regAddr Register address
634  * @param[in] data Register value
635  **/
636 
637 void lpc176xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
638 {
639  //Clear MCMD register
640  LPC_EMAC->MCMD = 0;
641 
642  //PHY address
643  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
644  //Register address
645  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
646  //Data to be written in the PHY register
647  LPC_EMAC->MWTD = data & MWTD_WRITE_DATA;
648 
649  //Wait for the write to complete
650  while(LPC_EMAC->MIND & MIND_BUSY);
651 }
652 
653 
654 /**
655  * @brief Read PHY register
656  * @param[in] phyAddr PHY address
657  * @param[in] regAddr Register address
658  * @return Register value
659  **/
660 
661 uint16_t lpc176xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
662 {
663  //PHY address
664  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
665  //Register address
666  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
667 
668  //Start a read operation
669  LPC_EMAC->MCMD = MCMD_READ;
670  //Wait for the read to complete
671  while(LPC_EMAC->MIND & MIND_BUSY);
672  //Clear MCMD register
673  LPC_EMAC->MCMD = 0;
674 
675  //Return PHY register contents
676  return LPC_EMAC->MRDD & MRDD_READ_DATA;
677 }
678 
679 
680 /**
681  * @brief CRC calculation
682  * @param[in] data Pointer to the data over which to calculate the CRC
683  * @param[in] length Number of bytes to process
684  * @return Resulting CRC value
685  **/
686 
687 uint32_t lpc176xEthCalcCrc(const void *data, size_t length)
688 {
689  uint_t i;
690  uint_t j;
691 
692  //Point to the data over which to calculate the CRC
693  const uint8_t *p = (uint8_t *) data;
694  //CRC preset value
695  uint32_t crc = 0xFFFFFFFF;
696 
697  //Loop through data
698  for(i = 0; i < length; i++)
699  {
700  //The message is processed bit by bit
701  for(j = 0; j < 8; j++)
702  {
703  //Update CRC value
704  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
705  crc = (crc << 1) ^ 0x04C11DB7;
706  else
707  crc = crc << 1;
708  }
709  }
710 
711  //Return CRC value
712  return crc;
713 }
error_t lpc176xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define MWTD_WRITE_DATA
#define IPGT_HALF_DUPLEX
#define MAC1_RESET_MCS_TX
void lpc176xEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define RFC_ACCEPT_PERFECT_EN
#define COMMAND_TX_ENABLE
TCP/IP stack core.
#define LPC176X_ETH_RX_BUFFER_COUNT
Debugging facilities.
#define MCFG_CLOCK_SELECT_DIV44
void lpc176xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
LPC1764/66/67/68/69 Ethernet MAC controller.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
void lpc176xEthEventHandler(NetInterface *interface)
LPC176x Ethernet MAC event handler.
Generic error code.
Definition: error.h:43
#define RX_STATUS_SIZE
#define txBuffer
uint16_t lpc176xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MAC1_SIMULATION_RESET
#define MAC2_CRC_ENABLE
#define CLRT_DEFAULT_VALUE
#define MAC2_PAD_CRC_ENABLE
#define MAC1_RECEIVE_ENABLE
#define IPGR_DEFAULT_VALUE
#define LPC176X_ETH_TX_BUFFER_COUNT
#define MCMD_READ
error_t lpc176xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define INT_RX_DONE
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define TX_CTRL_CRC
#define MRDD_READ_DATA
Transmit descriptor.
#define MADR_REGISTER_ADDRESS
#define COMMAND_REG_RESET
#define LPC176X_ETH_RX_BUFFER_SIZE
#define LPC176X_ETH_TX_BUFFER_SIZE
#define MIND_BUSY
#define MADR_PHY_ADDRESS
#define MAC2_FULL_DUPLEX
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define TX_CTRL_LAST
#define TX_CTRL_PAD
error_t lpc176xEthReceivePacket(NetInterface *interface)
Receive a packet.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define COMMAND_RMII
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
const NicDriver lpc176xEthDriver
LPC176x Ethernet MAC driver.
#define RFC_ACCEPT_BROADCAST_EN
#define LPC176X_ETH_IRQ_PRIORITY_GROUPING
#define COMMAND_FULL_DUPLEX
error_t lpc176xEthInit(NetInterface *interface)
LPC176x Ethernet MAC initialization.
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
uint32_t lpc176xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define MAC1_RESET_MCS_RX
#define MAC1_RESET_RX
#define COMMAND_RX_RESET
void lpc176xEthInitGpio(NetInterface *interface)
void ENET_IRQHandler(void)
LPC176x Ethernet MAC interrupt service routine.
#define RFC_ACCEPT_MULTICAST_HASH_EN
unsigned int uint_t
Definition: compiler_port.h:43
#define INT_TX_DONE
__start_packed struct @112 MacAddr
MAC address.
error_t lpc176xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define IPGT_FULL_DUPLEX
uint8_t data[]
Definition: dtls_misc.h:167
#define MCFG_RESET_MII_MGMT
#define NetInterface
Definition: net.h:34
#define TX_CTRL_SIZE
#define MAC1_SOFT_RESET
#define RX_CTRL_INTERRUPT
void lpc176xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Receive status.
Transmit status.
#define TX_CTRL_INTERRUPT
#define MAC1_RESET_TX
#define SUPP_SPEED
void lpc176xEthTick(NetInterface *interface)
LPC176x Ethernet MAC timer handler.
#define osExitIsr(flag)
#define COMMAND_TX_RESET
Receive descriptor.
#define osEnterIsr()
#define LPC176X_ETH_IRQ_GROUP_PRIORITY
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define COMMAND_RX_ENABLE
#define LPC176X_ETH_IRQ_SUB_PRIORITY
void lpc176xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98