lpc176x_eth_driver.c
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1 /**
2  * @file lpc176x_eth_driver.c
3  * @brief LPC1764/66/67/68/69 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "lpc17xx.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit descriptors
53 #pragma data_alignment = 4
55 //Transmit status array
56 #pragma data_alignment = 4
58 //Receive descriptors
59 #pragma data_alignment = 4
61 //Receive status array
62 #pragma data_alignment = 8
64 
65 //Keil MDK-ARM or GCC compiler?
66 #else
67 
68 //Transmit buffer
70  __attribute__((aligned(4)));
71 //Receive buffer
73  __attribute__((aligned(4)));
74 //Transmit descriptors
76  __attribute__((aligned(4)));
77 //Transmit status array
79  __attribute__((aligned(4)));
80 //Receive descriptors
82  __attribute__((aligned(4)));
83 //Receive status array
85  __attribute__((aligned(8)));
86 
87 #endif
88 
89 
90 /**
91  * @brief LPC176x Ethernet MAC driver
92  **/
93 
95 {
97  ETH_MTU,
108  TRUE,
109  TRUE,
110  TRUE,
111  FALSE
112 };
113 
114 
115 /**
116  * @brief LPC176x Ethernet MAC initialization
117  * @param[in] interface Underlying network interface
118  * @return Error code
119  **/
120 
122 {
123  error_t error;
124 
125  //Debug message
126  TRACE_INFO("Initializing LPC176x Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Power up EMAC controller
132  LPC_SC->PCONP |= PCONP_PCENET;
133 
134  //GPIO configuration
135  lpc176xEthInitGpio(interface);
136 
137  //Reset host registers, transmit datapath and receive datapath
138  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
139 
140  //Reset EMAC controller
141  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
143 
144  //Initialize MAC related registers
145  LPC_EMAC->MAC1 = 0;
146  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
147  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
148  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
149 
150  //Select RMII mode
151  LPC_EMAC->Command = COMMAND_RMII;
152 
153  //Configure MDC clock
154  LPC_EMAC->MCFG = MCFG_CLOCK_SELECT_DIV44;
155  //Reset MII management interface
156  LPC_EMAC->MCFG |= MCFG_RESET_MII_MGMT;
157  LPC_EMAC->MCFG &= ~MCFG_RESET_MII_MGMT;
158 
159  //Valid Ethernet PHY or switch driver?
160  if(interface->phyDriver != NULL)
161  {
162  //Ethernet PHY initialization
163  error = interface->phyDriver->init(interface);
164  }
165  else if(interface->switchDriver != NULL)
166  {
167  //Ethernet switch initialization
168  error = interface->switchDriver->init(interface);
169  }
170  else
171  {
172  //The interface is not properly configured
173  error = ERROR_FAILURE;
174  }
175 
176  //Any error to report?
177  if(error)
178  {
179  return error;
180  }
181 
182  //Initialize TX and RX descriptor arrays
183  lpc176xEthInitDesc(interface);
184 
185  //Set the MAC address of the station
186  LPC_EMAC->SA0 = interface->macAddr.w[2];
187  LPC_EMAC->SA1 = interface->macAddr.w[1];
188  LPC_EMAC->SA2 = interface->macAddr.w[0];
189 
190  //Initialize hash table
191  LPC_EMAC->HashFilterL = 0;
192  LPC_EMAC->HashFilterH = 0;
193 
194  //Configure the receive filter
195  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
197 
198  //Program the MAXF register with the maximum frame length to be accepted
199  LPC_EMAC->MAXF = LPC176X_ETH_RX_BUFFER_SIZE;
200 
201  //Reset EMAC interrupt flags
202  LPC_EMAC->IntClear = 0xFFFF;
203  //Enable desired EMAC interrupts
204  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
205 
206  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
207  NVIC_SetPriorityGrouping(LPC176X_ETH_IRQ_PRIORITY_GROUPING);
208 
209  //Configure Ethernet interrupt priority
210  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC176X_ETH_IRQ_PRIORITY_GROUPING,
212 
213  //Enable transmission and reception
214  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
215  //Allow frames to be received
216  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
217 
218  //Accept any packets from the upper layer
219  osSetEvent(&interface->nicTxEvent);
220 
221  //Successful initialization
222  return NO_ERROR;
223 }
224 
225 
226 //LPC1766-STK or LPCXpresso1769 evaluation board?
227 #if defined(USE_LPC1766_STK) || defined(USE_LPCXPRESSO_1769)
228 
229 /**
230  * @brief GPIO configuration
231  * @param[in] interface Underlying network interface
232  **/
233 
234 void lpc176xEthInitGpio(NetInterface *interface)
235 {
236  //Configure P1.0 (ENET_TXD0), P1.1 (ENET_TXD1), P1.4 (ENET_TX_EN), P1.8 (ENET_CRS),
237  //P1.9 (ENET_RXD0), P1.10 (ENET_RXD1), P1.14 (RX_ER) and P1.15 (ENET_REF_CLK)
238  LPC_PINCON->PINSEL2 &= ~(PINSEL2_P1_0_MASK | PINSEL2_P1_1_MASK |
239  PINSEL2_P1_4_MASK | PINSEL2_P1_8_MASK | PINSEL2_P1_9_MASK |
240  PINSEL2_P1_10_MASK | PINSEL2_P1_14_MASK | PINSEL2_P1_15_MASK);
241 
242  LPC_PINCON->PINSEL2 |= PINSEL2_P1_0_ENET_TXD0 | PINSEL2_P1_1_ENET_TXD1 |
243  PINSEL2_P1_4_ENET_TX_EN | PINSEL2_P1_8_ENET_CRS | PINSEL2_P1_9_ENET_RXD0 |
244  PINSEL2_P1_10_ENET_RXD1 | PINSEL2_P1_14_ENET_RX_ER | PINSEL2_P1_15_ENET_REF_CLK;
245 
246  //Configure P1.16 (ENET_MDC) and P1.17 (ENET_MDIO)
247  LPC_PINCON->PINSEL3 &= ~(PINSEL3_P1_16_MASK | PINSEL3_P1_17_MASK);
248  LPC_PINCON->PINSEL3 |= PINSEL3_P1_16_ENET_MDC | PINSEL3_P1_17_ENET_MDIO;
249 }
250 
251 #endif
252 
253 
254 /**
255  * @brief Initialize TX and RX descriptors
256  * @param[in] interface Underlying network interface
257  **/
258 
260 {
261  uint_t i;
262 
263  //Initialize TX descriptors
264  for(i = 0; i < LPC176X_ETH_TX_BUFFER_COUNT; i++)
265  {
266  //Base address of the buffer containing transmit data
267  txDesc[i].packet = (uint32_t) txBuffer[i];
268  //Transmit descriptor control word
269  txDesc[i].control = 0;
270  //Transmit status information word
271  txStatus[i].info = 0;
272  }
273 
274  //Initialize RX descriptors
275  for(i = 0; i < LPC176X_ETH_RX_BUFFER_COUNT; i++)
276  {
277  //Base address of the buffer for storing receive data
278  rxDesc[i].packet = (uint32_t) rxBuffer[i];
279  //Receive descriptor control word
281  //Receive status information word
282  rxStatus[i].info = 0;
283  //Receive status HashCRC word
284  rxStatus[i].hashCrc = 0;
285  }
286 
287  //Initialize EMAC transmit descriptor registers
288  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
289  LPC_EMAC->TxStatus = (uint32_t) txStatus;
290  LPC_EMAC->TxDescriptorNumber = LPC176X_ETH_TX_BUFFER_COUNT - 1;
291  LPC_EMAC->TxProduceIndex = 0;
292 
293  //Initialize EMAC receive descriptor registers
294  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
295  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
296  LPC_EMAC->RxDescriptorNumber = LPC176X_ETH_RX_BUFFER_COUNT - 1;
297  LPC_EMAC->RxConsumeIndex = 0;
298 }
299 
300 
301 /**
302  * @brief LPC176x Ethernet MAC timer handler
303  *
304  * This routine is periodically called by the TCP/IP stack to handle periodic
305  * operations such as polling the link state
306  *
307  * @param[in] interface Underlying network interface
308  **/
309 
310 void lpc176xEthTick(NetInterface *interface)
311 {
312  //Valid Ethernet PHY or switch driver?
313  if(interface->phyDriver != NULL)
314  {
315  //Handle periodic operations
316  interface->phyDriver->tick(interface);
317  }
318  else if(interface->switchDriver != NULL)
319  {
320  //Handle periodic operations
321  interface->switchDriver->tick(interface);
322  }
323  else
324  {
325  //Just for sanity
326  }
327 }
328 
329 
330 /**
331  * @brief Enable interrupts
332  * @param[in] interface Underlying network interface
333  **/
334 
336 {
337  //Enable Ethernet MAC interrupts
338  NVIC_EnableIRQ(ENET_IRQn);
339 
340  //Valid Ethernet PHY or switch driver?
341  if(interface->phyDriver != NULL)
342  {
343  //Enable Ethernet PHY interrupts
344  interface->phyDriver->enableIrq(interface);
345  }
346  else if(interface->switchDriver != NULL)
347  {
348  //Enable Ethernet switch interrupts
349  interface->switchDriver->enableIrq(interface);
350  }
351  else
352  {
353  //Just for sanity
354  }
355 }
356 
357 
358 /**
359  * @brief Disable interrupts
360  * @param[in] interface Underlying network interface
361  **/
362 
364 {
365  //Disable Ethernet MAC interrupts
366  NVIC_DisableIRQ(ENET_IRQn);
367 
368  //Valid Ethernet PHY or switch driver?
369  if(interface->phyDriver != NULL)
370  {
371  //Disable Ethernet PHY interrupts
372  interface->phyDriver->disableIrq(interface);
373  }
374  else if(interface->switchDriver != NULL)
375  {
376  //Disable Ethernet switch interrupts
377  interface->switchDriver->disableIrq(interface);
378  }
379  else
380  {
381  //Just for sanity
382  }
383 }
384 
385 
386 /**
387  * @brief LPC176x Ethernet MAC interrupt service routine
388  **/
389 
390 void ENET_IRQHandler(void)
391 {
392  uint_t i;
393  bool_t flag;
394  uint32_t status;
395 
396  //Interrupt service routine prologue
397  osEnterIsr();
398 
399  //This flag will be set if a higher priority task must be woken
400  flag = FALSE;
401 
402  //Read interrupt status register
403  status = LPC_EMAC->IntStatus;
404 
405  //Packet transmitted?
406  if((status & INT_TX_DONE) != 0)
407  {
408  //Clear TxDone interrupt flag
409  LPC_EMAC->IntClear = INT_TX_DONE;
410 
411  //Get the index of the next descriptor
412  i = LPC_EMAC->TxProduceIndex + 1;
413 
414  //Wrap around if necessary
416  {
417  i = 0;
418  }
419 
420  //Check whether the TX buffer is available for writing
421  if(i != LPC_EMAC->TxConsumeIndex)
422  {
423  //Notify the TCP/IP stack that the transmitter is ready to send
424  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
425  }
426  }
427 
428  //Packet received?
429  if((status & INT_RX_DONE) != 0)
430  {
431  //Disable RxDone interrupts
432  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
433 
434  //Set event flag
435  nicDriverInterface->nicEvent = TRUE;
436  //Notify the TCP/IP stack of the event
437  flag |= osSetEventFromIsr(&netEvent);
438  }
439 
440  //Interrupt service routine epilogue
441  osExitIsr(flag);
442 }
443 
444 
445 /**
446  * @brief LPC176x Ethernet MAC event handler
447  * @param[in] interface Underlying network interface
448  **/
449 
451 {
452  error_t error;
453 
454  //Packet received?
455  if((LPC_EMAC->IntStatus & INT_RX_DONE) != 0)
456  {
457  //Clear RxDone interrupt flag
458  LPC_EMAC->IntClear = INT_RX_DONE;
459 
460  //Process all pending packets
461  do
462  {
463  //Read incoming packet
464  error = lpc176xEthReceivePacket(interface);
465 
466  //No more data in the receive buffer?
467  } while(error != ERROR_BUFFER_EMPTY);
468  }
469 
470  //Re-enable TxDone and RxDone interrupts
471  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
472 }
473 
474 
475 /**
476  * @brief Send a packet
477  * @param[in] interface Underlying network interface
478  * @param[in] buffer Multi-part buffer containing the data to send
479  * @param[in] offset Offset to the first data byte
480  * @param[in] ancillary Additional options passed to the stack along with
481  * the packet
482  * @return Error code
483  **/
484 
486  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
487 {
488  uint_t i;
489  uint_t j;
490  size_t length;
491 
492  //Retrieve the length of the packet
493  length = netBufferGetLength(buffer) - offset;
494 
495  //Check the frame length
496  if(!length)
497  {
498  //The transmitter can accept another packet
499  osSetEvent(&interface->nicTxEvent);
500  //We are done since the buffer is empty
501  return NO_ERROR;
502  }
504  {
505  //The transmitter can accept another packet
506  osSetEvent(&interface->nicTxEvent);
507  //Report an error
508  return ERROR_INVALID_LENGTH;
509  }
510 
511  //Get the index of the current descriptor
512  i = LPC_EMAC->TxProduceIndex;
513  //Get the index of the next descriptor
514  j = i + 1;
515 
516  //Wrap around if necessary
518  {
519  j = 0;
520  }
521 
522  //Check whether the transmit descriptor array is full
523  if(j == LPC_EMAC->TxConsumeIndex)
524  {
525  return ERROR_FAILURE;
526  }
527 
528  //Copy user data to the transmit buffer
529  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
530 
531  //Write the transmit control word
532  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
534 
535  //Increment index and wrap around if necessary
536  if(++i >= LPC176X_ETH_TX_BUFFER_COUNT)
537  {
538  i = 0;
539  }
540 
541  //Save the resulting value
542  LPC_EMAC->TxProduceIndex = i;
543 
544  //Get the index of the next descriptor
545  j = i + 1;
546 
547  //Wrap around if necessary
549  {
550  j = 0;
551  }
552 
553  //Check whether the next buffer is available for writing
554  if(j != LPC_EMAC->TxConsumeIndex)
555  {
556  //The transmitter can accept another packet
557  osSetEvent(&interface->nicTxEvent);
558  }
559 
560  //Successful write operation
561  return NO_ERROR;
562 }
563 
564 
565 /**
566  * @brief Receive a packet
567  * @param[in] interface Underlying network interface
568  * @return Error code
569  **/
570 
572 {
573  error_t error;
574  size_t n;
575  uint_t i;
576  NetRxAncillary ancillary;
577 
578  //Point to the current descriptor
579  i = LPC_EMAC->RxConsumeIndex;
580 
581  //Make sure the current buffer is available for reading
582  if(i != LPC_EMAC->RxProduceIndex)
583  {
584  //Retrieve the length of the frame
585  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
586  //Limit the number of data to read
588 
589  //Additional options can be passed to the stack along with the packet
590  ancillary = NET_DEFAULT_RX_ANCILLARY;
591 
592  //Pass the packet to the upper layer
593  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n, &ancillary);
594 
595  //Increment index and wrap around if necessary
596  if(++i >= LPC176X_ETH_RX_BUFFER_COUNT)
597  {
598  i = 0;
599  }
600 
601  //Save the resulting value
602  LPC_EMAC->RxConsumeIndex = i;
603 
604  //Valid packet received
605  error = NO_ERROR;
606  }
607  else
608  {
609  //No more data in the receive buffer
610  error = ERROR_BUFFER_EMPTY;
611  }
612 
613  //Return status code
614  return error;
615 }
616 
617 
618 /**
619  * @brief Configure MAC address filtering
620  * @param[in] interface Underlying network interface
621  * @return Error code
622  **/
623 
625 {
626  uint_t i;
627  uint_t k;
628  uint32_t crc;
629  uint32_t hashTable[2];
630  MacFilterEntry *entry;
631 
632  //Debug message
633  TRACE_DEBUG("Updating MAC filter...\r\n");
634 
635  //Set the MAC address of the station
636  LPC_EMAC->SA0 = interface->macAddr.w[2];
637  LPC_EMAC->SA1 = interface->macAddr.w[1];
638  LPC_EMAC->SA2 = interface->macAddr.w[0];
639 
640  //Clear hash table
641  hashTable[0] = 0;
642  hashTable[1] = 0;
643 
644  //The MAC address filter contains the list of MAC addresses to accept
645  //when receiving an Ethernet frame
646  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
647  {
648  //Point to the current entry
649  entry = &interface->macAddrFilter[i];
650 
651  //Valid entry?
652  if(entry->refCount > 0)
653  {
654  //Compute CRC over the current MAC address
655  crc = lpc176xEthCalcCrc(&entry->addr, sizeof(MacAddr));
656  //Bits [28:23] are used to form the hash
657  k = (crc >> 23) & 0x3F;
658  //Update hash table contents
659  hashTable[k / 32] |= (1 << (k % 32));
660  }
661  }
662 
663  //Write the hash table
664  LPC_EMAC->HashFilterL = hashTable[0];
665  LPC_EMAC->HashFilterH = hashTable[1];
666 
667  //Debug message
668  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
669  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
670 
671  //Successful processing
672  return NO_ERROR;
673 }
674 
675 
676 /**
677  * @brief Adjust MAC configuration parameters for proper operation
678  * @param[in] interface Underlying network interface
679  * @return Error code
680  **/
681 
683 {
684  //10BASE-T or 100BASE-TX operation mode?
685  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
686  {
687  LPC_EMAC->SUPP = SUPP_SPEED;
688  }
689  else
690  {
691  LPC_EMAC->SUPP = 0;
692  }
693 
694  //Half-duplex or full-duplex mode?
695  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
696  {
697  //The MAC operates in full-duplex mode
698  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
699  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
700  //Configure Back-to-Back Inter-Packet Gap
701  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
702  }
703  else
704  {
705  //The MAC operates in half-duplex mode
706  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
707  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
708  //Configure Back-to-Back Inter-Packet Gap
709  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
710  }
711 
712  //Successful processing
713  return NO_ERROR;
714 }
715 
716 
717 /**
718  * @brief Write PHY register
719  * @param[in] opcode Access type (2 bits)
720  * @param[in] phyAddr PHY address (5 bits)
721  * @param[in] regAddr Register address (5 bits)
722  * @param[in] data Register value
723  **/
724 
725 void lpc176xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
726  uint8_t regAddr, uint16_t data)
727 {
728  //Valid opcode?
729  if(opcode == SMI_OPCODE_WRITE)
730  {
731  //Clear MCMD register
732  LPC_EMAC->MCMD = 0;
733 
734  //PHY address
735  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
736  //Register address
737  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
738  //Data to be written in the PHY register
739  LPC_EMAC->MWTD = data & MWTD_WRITE_DATA;
740 
741  //Wait for the write to complete
742  while((LPC_EMAC->MIND & MIND_BUSY) != 0)
743  {
744  }
745  }
746  else
747  {
748  //The MAC peripheral only supports standard Clause 22 opcodes
749  }
750 }
751 
752 
753 /**
754  * @brief Read PHY register
755  * @param[in] opcode Access type (2 bits)
756  * @param[in] phyAddr PHY address (5 bits)
757  * @param[in] regAddr Register address (5 bits)
758  * @return Register value
759  **/
760 
761 uint16_t lpc176xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
762  uint8_t regAddr)
763 {
764  uint16_t data;
765 
766  //Valid opcode?
767  if(opcode == SMI_OPCODE_READ)
768  {
769  //PHY address
770  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
771  //Register address
772  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
773 
774  //Start a read operation
775  LPC_EMAC->MCMD = MCMD_READ;
776  //Wait for the read to complete
777  while((LPC_EMAC->MIND & MIND_BUSY) != 0)
778  {
779  }
780 
781  //Clear MCMD register
782  LPC_EMAC->MCMD = 0;
783 
784  //Get register value
785  data = LPC_EMAC->MRDD & MRDD_READ_DATA;
786  }
787  else
788  {
789  //The MAC peripheral only supports standard Clause 22 opcodes
790  data = 0;
791  }
792 
793  //Return the value of the PHY register
794  return data;
795 }
796 
797 
798 /**
799  * @brief CRC calculation
800  * @param[in] data Pointer to the data over which to calculate the CRC
801  * @param[in] length Number of bytes to process
802  * @return Resulting CRC value
803  **/
804 
805 uint32_t lpc176xEthCalcCrc(const void *data, size_t length)
806 {
807  uint_t i;
808  uint_t j;
809  uint32_t crc;
810  const uint8_t *p;
811 
812  //Point to the data over which to calculate the CRC
813  p = (uint8_t *) data;
814  //CRC preset value
815  crc = 0xFFFFFFFF;
816 
817  //Loop through data
818  for(i = 0; i < length; i++)
819  {
820  //The message is processed bit by bit
821  for(j = 0; j < 8; j++)
822  {
823  //Update CRC value
824  if((((crc >> 31) ^ (p[i] >> j)) & 0x01) != 0)
825  {
826  crc = (crc << 1) ^ 0x04C11DB7;
827  }
828  else
829  {
830  crc = crc << 1;
831  }
832  }
833  }
834 
835  //Return CRC value
836  return crc;
837 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
Transmit descriptor.
#define MADR_PHY_ADDRESS
LPC1764/66/67/68/69 Ethernet MAC driver.
#define MCFG_CLOCK_SELECT_DIV44
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
#define TX_CTRL_SIZE
#define LPC176X_ETH_IRQ_SUB_PRIORITY
uint8_t data[]
Definition: ethernet.h:209
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void lpc176xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t lpc176xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define IPGR_DEFAULT_VALUE
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define COMMAND_TX_ENABLE
__start_packed struct @5 MacAddr
MAC address.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define IPGT_FULL_DUPLEX
uint32_t lpc176xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define MAC1_SOFT_RESET
#define TX_CTRL_CRC
#define COMMAND_RMII
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define osExitIsr(flag)
#define TX_CTRL_INTERRUPT
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define RX_CTRL_INTERRUPT
#define MAC1_RESET_TX
#define MAC1_RECEIVE_ENABLE
#define SUPP_SPEED
#define MWTD_WRITE_DATA
#define MAC2_FULL_DUPLEX
#define CLRT_DEFAULT_VALUE
#define FALSE
Definition: os_port.h:46
#define MAC1_SIMULATION_RESET
void lpc176xEthTick(NetInterface *interface)
LPC176x Ethernet MAC timer handler.
error_t
Error codes.
Definition: error.h:42
#define COMMAND_RX_RESET
#define COMMAND_RX_ENABLE
Receive status.
Transmit status.
error_t lpc176xEthInit(NetInterface *interface)
LPC176x Ethernet MAC initialization.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
Receive descriptor.
#define LPC176X_ETH_TX_BUFFER_COUNT
#define RFC_ACCEPT_BROADCAST_EN
#define txBuffer
void lpc176xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
#define INT_TX_DONE
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define COMMAND_TX_RESET
void lpc176xEthInitGpio(NetInterface *interface)
#define MAC1_RESET_MCS_TX
error_t lpc176xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MAC2_PAD_CRC_ENABLE
#define COMMAND_FULL_DUPLEX
#define MIN(a, b)
Definition: os_port.h:62
#define TX_CTRL_LAST
#define TX_CTRL_PAD
#define MAC1_RESET_MCS_RX
#define rxBuffer
uint16_t lpc176xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define LPC176X_ETH_RX_BUFFER_SIZE
void lpc176xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
#define MIND_BUSY
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define LPC176X_ETH_TX_BUFFER_SIZE
uint16_t regAddr
#define LPC176X_ETH_IRQ_GROUP_PRIORITY
#define RX_STATUS_SIZE
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define MRDD_READ_DATA
#define osEnterIsr()
#define MAC2_CRC_ENABLE
const NicDriver lpc176xEthDriver
LPC176x Ethernet MAC driver.
error_t lpc176xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define LPC176X_ETH_IRQ_PRIORITY_GROUPING
#define IPGT_HALF_DUPLEX
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MCFG_RESET_MII_MGMT
#define MCMD_READ
#define RFC_ACCEPT_MULTICAST_HASH_EN
#define INT_RX_DONE
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
void ENET_IRQHandler(void)
LPC176x Ethernet MAC interrupt service routine.
#define COMMAND_REG_RESET
NIC driver.
Definition: nic.h:257
void lpc176xEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define MADR_REGISTER_ADDRESS
#define RFC_ACCEPT_PERFECT_EN
#define MAC1_RESET_RX
error_t lpc176xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define LPC176X_ETH_RX_BUFFER_COUNT
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
void lpc176xEthEventHandler(NetInterface *interface)
LPC176x Ethernet MAC event handler.
Ethernet interface.
Definition: nic.h:82