mcimx6ul_eth1_driver.c
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1 /**
2  * @file mcimx6ul_eth1_driver.c
3  * @brief i.MX6UL Ethernet MAC controller (ENET1 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = "NonCacheable"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = "NonCacheable"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = "NonCacheable"
59 static uint32_t txBufferDesc[MCIMX6UL_ETH1_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = "NonCacheable"
63 static uint32_t rxBufferDesc[MCIMX6UL_ETH1_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__("NonCacheable")));
71 //RX buffer
73  __attribute__((aligned(16), __section__("NonCacheable")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MCIMX6UL_ETH1_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__("NonCacheable")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MCIMX6UL_ETH1_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__("NonCacheable")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX6UL Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX6UL Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX6UL Ethernet MAC #1...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mcimx6ulEth1InitGpio(interface);
136 
137  //Reset ENET module
138  ENET1->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET1->ECR & ENET_ECR_RESET_MASK)
141  {
142  }
143 
144  //Receive control register
145  ENET1->RCR = ENET_RCR_MAX_FL(MCIMX6UL_ETH1_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET1->TCR = 0;
150  //Configure MDC clock frequency
151  ENET1->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //PHY transceiver initialization
154  error = interface->phyDriver->init(interface);
155  //Failed to initialize PHY transceiver?
156  if(error)
157  return error;
158 
159  //Set the MAC address of the station (upper 16 bits)
160  value = interface->macAddr.b[5];
161  value |= (interface->macAddr.b[4] << 8);
162  ENET1->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
163 
164  //Set the MAC address of the station (lower 32 bits)
165  value = interface->macAddr.b[3];
166  value |= (interface->macAddr.b[2] << 8);
167  value |= (interface->macAddr.b[1] << 16);
168  value |= (interface->macAddr.b[0] << 24);
169  ENET1->PALR = ENET_PALR_PADDR1(value);
170 
171  //Hash table for unicast address filtering
172  ENET1->IALR = 0;
173  ENET1->IAUR = 0;
174  //Hash table for multicast address filtering
175  ENET1->GALR = 0;
176  ENET1->GAUR = 0;
177 
178  //Disable transmit accelerator functions
179  ENET1->TACC = 0;
180  //Disable receive accelerator functions
181  ENET1->RACC = 0;
182 
183  //Use enhanced buffer descriptors
184  ENET1->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
185  //Clear MIC counters
186  ENET1->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
187 
188  //Initialize buffer descriptors
189  mcimx6ulEth1InitBufferDesc(interface);
190 
191  //Clear any pending interrupts
192  ENET1->EIR = 0xFFFFFFFF;
193  //Enable desired interrupts
194  ENET1->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
195 
196  //Configure ENET interrupt priority
197  GIC_SetPriority(ENET1_IRQn, MCIMX6UL_ETH1_IRQ_PRIORITY);
198 
199  //Enable Ethernet MAC
200  ENET1->ECR |= ENET_ECR_ETHEREN_MASK;
201  //Instruct the DMA to poll the receive descriptor list
202  ENET1->RDAR = ENET_RDAR_RDAR_MASK;
203 
204  //Accept any packets from the upper layer
205  osSetEvent(&interface->nicTxEvent);
206 
207  //Successful initialization
208  return NO_ERROR;
209 }
210 
211 
212 //MCIMX6UL-EVKB or MCIMX6ULL-EVK evaluation board?
213 #if defined(USE_MCIMX6UL_EVKB) || defined(USE_MCIMX6ULL_EVK)
214 
215 /**
216  * @brief GPIO configuration
217  * @param[in] interface Underlying network interface
218  **/
219 
220 void mcimx6ulEth1InitGpio(NetInterface *interface)
221 {
222  gpio_pin_config_t pinConfig;
223  clock_enet_pll_config_t pllConfig;
224 
225  //Configure ENET PLL (50MHz)
226  pllConfig.enableClkOutput0 = true;
227  pllConfig.enableClkOutput1 = true;
228  pllConfig.enableClkOutput2 = false;
229  pllConfig.loopDivider0 = 1;
230  pllConfig.loopDivider1 = 1;
231  CLOCK_InitEnetPll(&pllConfig);
232 
233  //Enable ENET1_TX_CLK output driver
234  IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1);
235 
236  //Enable IOMUXC clock
237  CLOCK_EnableClock(kCLOCK_Iomuxc);
238 
239  //Configure ENET1_TX_CLK pin as ENET1_REF_CLK1
240  IOMUXC_SetPinMux(IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1, 1);
241 
242  //Set ENET1_TX_CLK pad properties
243  IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1,
244  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
245  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
246  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
247  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
248  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
249  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
250  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
251  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
252 
253  //Configure ENET1_TX_EN pin as ENET1_TX_EN
254  IOMUXC_SetPinMux(IOMUXC_ENET1_TX_EN_ENET1_TX_EN, 0);
255 
256  //Set ENET1_TX_EN pad properties
257  IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_EN_ENET1_TX_EN,
258  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
259  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
260  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
261  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
262  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
263  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
264  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
265  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
266 
267  //Configure ENET1_TX_DATA0 pin as ENET1_TDATA00
268  IOMUXC_SetPinMux(IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00, 0);
269 
270  //Set ENET1_TX_DATA0 pad properties
271  IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00,
272  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
273  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
274  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
275  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
276  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
277  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
278  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
279  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
280 
281  //Configure ENET1_TX_DATA1 pin as ENET1_TDATA01
282  IOMUXC_SetPinMux(IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01, 0);
283 
284  //Set ENET1_TX_DATA1 pad properties
285  IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01,
286  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
287  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
288  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
289  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
290  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
291  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
292  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
293  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
294 
295  //Configure ENET1_RX_EN pin as ENET1_RX_EN
296  IOMUXC_SetPinMux(IOMUXC_ENET1_RX_EN_ENET1_RX_EN, 0);
297 
298  //Set ENET1_RX_EN pad properties
299  IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_EN_ENET1_RX_EN,
300  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
301  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
302  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
303  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
304  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
305  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
306  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
307  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
308 
309  //Configure ENET1_RX_ER pin as ENET1_RX_ER
310  IOMUXC_SetPinMux(IOMUXC_ENET1_RX_ER_ENET1_RX_ER, 0);
311 
312  //Set ENET1_RX_ER pad properties
313  IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_ER_ENET1_RX_ER,
314  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
315  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
316  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
317  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
318  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
319  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
320  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
321  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
322 
323  //Configure ENET1_RX_DATA0 pin as ENET1_RDATA00
324  IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00, 0);
325 
326  //Set ENET1_RX_DATA0 pad properties
327  IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00,
328  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
329  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
330  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
331  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
332  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
333  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
334  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
335  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
336 
337  //Configure ENET1_RX_DATA1 pin as ENET1_RDATA01
338  IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01, 0);
339 
340  //Set ENET1_RX_DATA1 pad properties
341  IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01,
342  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
343  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
344  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
345  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
346  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
347  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
348  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
349  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
350 
351  //Configure GPIO1_IO06 pin as ENET1_MDIO
352  IOMUXC_SetPinMux(IOMUXC_GPIO1_IO06_ENET1_MDIO, 0);
353 
354  //Set GPIO1_IO06 pad properties
355  IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO06_ENET1_MDIO,
356  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
357  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
358  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
359  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
360  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
361  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
362  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
363  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
364 
365  //Configure GPIO1_IO07 pin as ENET1_MDC
366  IOMUXC_SetPinMux(IOMUXC_GPIO1_IO07_ENET1_MDC, 0);
367 
368  //Set GPIO1_IO07 pad properties
369  IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO07_ENET1_MDC,
370  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
371  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
372  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
373  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
374  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
375  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
376  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
377  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
378 
379 #if defined(USE_MCIMX6UL_EVKB)
380  //Configure SNVS_TAMPER5 pin as GPIO5_IO05
381  IOMUXC_SetPinMux(IOMUXC_SNVS_TAMPER5_GPIO5_IO05, 0);
382 
383  //Set SNVS_TAMPER5 pad properties
384  IOMUXC_SetPinConfig(IOMUXC_SNVS_TAMPER5_GPIO5_IO05,
385  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
386  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
387  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
388  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
389  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
390  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
391  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
392  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
393 
394 #elif defined(USE_MCIMX6ULL_EVK)
395  //Configure SNVS_TAMPER5 pin as GPIO5_IO05
396  IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER5_GPIO5_IO05, 0);
397 
398  //Set SNVS_TAMPER5 pad properties
399  IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER5_GPIO5_IO05,
400  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
401  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
402  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
403  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
404  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
405  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
406  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
407  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
408 #endif
409 
410  //Configure ENET1_INT as an input
411  pinConfig.direction = kGPIO_DigitalInput;
412  pinConfig.outputLogic = 0;
413  pinConfig.interruptMode = kGPIO_NoIntmode;
414  GPIO_PinInit(GPIO5, 5, &pinConfig);
415 }
416 
417 #endif
418 
419 
420 /**
421  * @brief Initialize buffer descriptors
422  * @param[in] interface Underlying network interface
423  **/
424 
426 {
427  uint_t i;
428  uint32_t address;
429 
430  //Clear TX and RX buffer descriptors
431  memset(txBufferDesc, 0, sizeof(txBufferDesc));
432  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
433 
434  //Initialize TX buffer descriptors
435  for(i = 0; i < MCIMX6UL_ETH1_TX_BUFFER_COUNT; i++)
436  {
437  //Calculate the address of the current TX buffer
438  address = (uint32_t) txBuffer[i];
439  //Transmit buffer address
440  txBufferDesc[i][1] = address;
441  //Generate interrupts
442  txBufferDesc[i][2] = ENET_TBD2_INT;
443  }
444 
445  //Mark the last descriptor entry with the wrap flag
446  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
447  //Initialize TX buffer index
448  txBufferIndex = 0;
449 
450  //Initialize RX buffer descriptors
451  for(i = 0; i < MCIMX6UL_ETH1_RX_BUFFER_COUNT; i++)
452  {
453  //Calculate the address of the current RX buffer
454  address = (uint32_t) rxBuffer[i];
455  //The descriptor is initially owned by the DMA
456  rxBufferDesc[i][0] = ENET_RBD0_E;
457  //Receive buffer address
458  rxBufferDesc[i][1] = address;
459  //Generate interrupts
460  rxBufferDesc[i][2] = ENET_RBD2_INT;
461  }
462 
463  //Mark the last descriptor entry with the wrap flag
464  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
465  //Initialize RX buffer index
466  rxBufferIndex = 0;
467 
468  //Start location of the TX descriptor list
469  ENET1->TDSR = (uint32_t) txBufferDesc;
470  //Start location of the RX descriptor list
471  ENET1->RDSR = (uint32_t) rxBufferDesc;
472  //Maximum receive buffer size
473  ENET1->MRBR = MCIMX6UL_ETH1_RX_BUFFER_SIZE;
474 }
475 
476 
477 /**
478  * @brief i.MX6UL Ethernet MAC timer handler
479  *
480  * This routine is periodically called by the TCP/IP stack to
481  * handle periodic operations such as polling the link state
482  *
483  * @param[in] interface Underlying network interface
484  **/
485 
487 {
488  //Handle periodic operations
489  interface->phyDriver->tick(interface);
490 }
491 
492 
493 /**
494  * @brief Enable interrupts
495  * @param[in] interface Underlying network interface
496  **/
497 
499 {
500  //Enable Ethernet MAC interrupts
501  GIC_EnableIRQ(ENET1_IRQn);
502  //Enable Ethernet PHY interrupts
503  interface->phyDriver->enableIrq(interface);
504 }
505 
506 
507 /**
508  * @brief Disable interrupts
509  * @param[in] interface Underlying network interface
510  **/
511 
513 {
514  //Disable Ethernet MAC interrupts
515  GIC_DisableIRQ(ENET1_IRQn);
516  //Disable Ethernet PHY interrupts
517  interface->phyDriver->disableIrq(interface);
518 }
519 
520 
521 /**
522  * @brief Ethernet MAC interrupt (ENET1 instance)
523  * @param[in] giccIar Value of the GICC_IAR register
524  * @param[in] userParam User parameter
525  **/
526 
527 void ENET1_DriverIRQHandler (uint32_t giccIar, void *userParam)
528 {
529  bool_t flag;
530  uint32_t events;
531 
532  //Interrupt service routine prologue
533  osEnterIsr();
534 
535  //This flag will be set if a higher priority task must be woken
536  flag = FALSE;
537  //Read interrupt event register
538  events = ENET1->EIR;
539 
540  //A packet has been transmitted?
541  if(events & ENET_EIR_TXF_MASK)
542  {
543  //Clear TXF interrupt flag
544  ENET1->EIR = ENET_EIR_TXF_MASK;
545 
546  //Check whether the TX buffer is available for writing
547  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
548  {
549  //Notify the TCP/IP stack that the transmitter is ready to send
550  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
551  }
552 
553  //Instruct the DMA to poll the transmit descriptor list
554  ENET1->TDAR = ENET_TDAR_TDAR_MASK;
555  }
556 
557  //A packet has been received?
558  if(events & ENET_EIR_RXF_MASK)
559  {
560  //Disable RXF interrupt
561  ENET1->EIMR &= ~ENET_EIMR_RXF_MASK;
562 
563  //Set event flag
564  nicDriverInterface->nicEvent = TRUE;
565  //Notify the TCP/IP stack of the event
566  flag = osSetEventFromIsr(&netEvent);
567  }
568 
569  //System bus error?
570  if(events & ENET_EIR_EBERR_MASK)
571  {
572  //Disable EBERR interrupt
573  ENET1->EIMR &= ~ENET_EIMR_EBERR_MASK;
574 
575  //Set event flag
576  nicDriverInterface->nicEvent = TRUE;
577  //Notify the TCP/IP stack of the event
578  flag |= osSetEventFromIsr(&netEvent);
579  }
580 
581  //Interrupt service routine epilogue
582  osExitIsr(flag);
583 }
584 
585 
586 /**
587  * @brief i.MX6UL Ethernet MAC event handler
588  * @param[in] interface Underlying network interface
589  **/
590 
592 {
593  error_t error;
594  uint32_t status;
595 
596  //Read interrupt event register
597  status = ENET1->EIR;
598 
599  //Packet received?
600  if(status & ENET_EIR_RXF_MASK)
601  {
602  //Clear RXF interrupt flag
603  ENET1->EIR = ENET_EIR_RXF_MASK;
604 
605  //Process all pending packets
606  do
607  {
608  //Read incoming packet
609  error = mcimx6ulEth1ReceivePacket(interface);
610 
611  //No more data in the receive buffer?
612  } while(error != ERROR_BUFFER_EMPTY);
613  }
614 
615  //System bus error?
616  if(status & ENET_EIR_EBERR_MASK)
617  {
618  //Clear EBERR interrupt flag
619  ENET1->EIR = ENET_EIR_EBERR_MASK;
620 
621  //Disable Ethernet MAC
622  ENET1->ECR &= ~ENET_ECR_ETHEREN_MASK;
623  //Reset buffer descriptors
624  mcimx6ulEth1InitBufferDesc(interface);
625  //Resume normal operation
626  ENET1->ECR |= ENET_ECR_ETHEREN_MASK;
627  //Instruct the DMA to poll the receive descriptor list
628  ENET1->RDAR = ENET_RDAR_RDAR_MASK;
629  }
630 
631  //Re-enable Ethernet MAC interrupts
632  ENET1->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
633 }
634 
635 
636 /**
637  * @brief Send a packet
638  * @param[in] interface Underlying network interface
639  * @param[in] buffer Multi-part buffer containing the data to send
640  * @param[in] offset Offset to the first data byte
641  * @return Error code
642  **/
643 
645  const NetBuffer *buffer, size_t offset)
646 {
647  static uint8_t temp[MCIMX6UL_ETH1_TX_BUFFER_SIZE];
648  size_t length;
649 
650  //Retrieve the length of the packet
651  length = netBufferGetLength(buffer) - offset;
652 
653  //Check the frame length
655  {
656  //The transmitter can accept another packet
657  osSetEvent(&interface->nicTxEvent);
658  //Report an error
659  return ERROR_INVALID_LENGTH;
660  }
661 
662  //Make sure the current buffer is available for writing
663  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
664  return ERROR_FAILURE;
665 
666  //Copy user data to the transmit buffer
667  netBufferRead(temp, buffer, offset, length);
668  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
669 
670  //Clear BDU flag
671  txBufferDesc[txBufferIndex][4] = 0;
672 
673  //Check current index
674  if(txBufferIndex < (MCIMX6UL_ETH1_TX_BUFFER_COUNT - 1))
675  {
676  //Give the ownership of the descriptor to the DMA engine
677  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
679 
680  //Point to the next buffer
681  txBufferIndex++;
682  }
683  else
684  {
685  //Give the ownership of the descriptor to the DMA engine
686  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
688 
689  //Wrap around
690  txBufferIndex = 0;
691  }
692 
693  //Data synchronization barrier
694  __DSB();
695 
696  //Instruct the DMA to poll the transmit descriptor list
697  ENET1->TDAR = ENET_TDAR_TDAR_MASK;
698 
699  //Check whether the next buffer is available for writing
700  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
701  {
702  //The transmitter can accept another packet
703  osSetEvent(&interface->nicTxEvent);
704  }
705 
706  //Successful processing
707  return NO_ERROR;
708 }
709 
710 
711 /**
712  * @brief Receive a packet
713  * @param[in] interface Underlying network interface
714  * @return Error code
715  **/
716 
718 {
719  static uint8_t temp[MCIMX6UL_ETH1_RX_BUFFER_SIZE];
720  error_t error;
721  size_t n;
722 
723  //Make sure the current buffer is available for reading
724  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
725  {
726  //The frame should not span multiple buffers
727  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
728  {
729  //Check whether an error occurred
730  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
732  {
733  //Retrieve the length of the frame
734  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
735  //Limit the number of data to read
737 
738  //Copy data from the receive buffer
739  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
740 
741  //Pass the packet to the upper layer
742  nicProcessPacket(interface, temp, n);
743 
744  //Valid packet received
745  error = NO_ERROR;
746  }
747  else
748  {
749  //The received packet contains an error
750  error = ERROR_INVALID_PACKET;
751  }
752  }
753  else
754  {
755  //The packet is not valid
756  error = ERROR_INVALID_PACKET;
757  }
758 
759  //Clear BDU flag
760  rxBufferDesc[rxBufferIndex][4] = 0;
761 
762  //Check current index
763  if(rxBufferIndex < (MCIMX6UL_ETH1_RX_BUFFER_COUNT - 1))
764  {
765  //Give the ownership of the descriptor back to the DMA engine
766  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
767  //Point to the next buffer
768  rxBufferIndex++;
769  }
770  else
771  {
772  //Give the ownership of the descriptor back to the DMA engine
773  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
774  //Wrap around
775  rxBufferIndex = 0;
776  }
777 
778  //Instruct the DMA to poll the receive descriptor list
779  ENET1->RDAR = ENET_RDAR_RDAR_MASK;
780  }
781  else
782  {
783  //No more data in the receive buffer
784  error = ERROR_BUFFER_EMPTY;
785  }
786 
787  //Return status code
788  return error;
789 }
790 
791 
792 /**
793  * @brief Configure MAC address filtering
794  * @param[in] interface Underlying network interface
795  * @return Error code
796  **/
797 
799 {
800  uint_t i;
801  uint_t k;
802  uint32_t crc;
803  uint32_t unicastHashTable[2];
804  uint32_t multicastHashTable[2];
805  MacFilterEntry *entry;
806 
807  //Debug message
808  TRACE_DEBUG("Updating MAC filter...\r\n");
809 
810  //Clear hash table (unicast address filtering)
811  unicastHashTable[0] = 0;
812  unicastHashTable[1] = 0;
813 
814  //Clear hash table (multicast address filtering)
815  multicastHashTable[0] = 0;
816  multicastHashTable[1] = 0;
817 
818  //The MAC address filter contains the list of MAC addresses to accept
819  //when receiving an Ethernet frame
820  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
821  {
822  //Point to the current entry
823  entry = &interface->macAddrFilter[i];
824 
825  //Valid entry?
826  if(entry->refCount > 0)
827  {
828  //Compute CRC over the current MAC address
829  crc = mcimx6ulEth1CalcCrc(&entry->addr, sizeof(MacAddr));
830 
831  //The upper 6 bits in the CRC register are used to index the
832  //contents of the hash table
833  k = (crc >> 26) & 0x3F;
834 
835  //Multicast address?
836  if(macIsMulticastAddr(&entry->addr))
837  {
838  //Update the multicast hash table
839  multicastHashTable[k / 32] |= (1 << (k % 32));
840  }
841  else
842  {
843  //Update the unicast hash table
844  unicastHashTable[k / 32] |= (1 << (k % 32));
845  }
846  }
847  }
848 
849  //Write the hash table (unicast address filtering)
850  ENET1->IALR = unicastHashTable[0];
851  ENET1->IAUR = unicastHashTable[1];
852 
853  //Write the hash table (multicast address filtering)
854  ENET1->GALR = multicastHashTable[0];
855  ENET1->GAUR = multicastHashTable[1];
856 
857  //Debug message
858  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET1->IALR);
859  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET1->IAUR);
860  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET1->GALR);
861  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET1->GAUR);
862 
863  //Successful processing
864  return NO_ERROR;
865 }
866 
867 
868 /**
869  * @brief Adjust MAC configuration parameters for proper operation
870  * @param[in] interface Underlying network interface
871  * @return Error code
872  **/
873 
875 {
876  //Disable Ethernet MAC while modifying configuration registers
877  ENET1->ECR &= ~ENET_ECR_ETHEREN_MASK;
878 
879  //10BASE-T or 100BASE-TX operation mode?
880  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
881  {
882  //100 Mbps operation
883  ENET1->RCR &= ~ENET_RCR_RMII_10T_MASK;
884  }
885  else
886  {
887  //10 Mbps operation
888  ENET1->RCR |= ENET_RCR_RMII_10T_MASK;
889  }
890 
891  //Half-duplex or full-duplex mode?
892  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
893  {
894  //Full-duplex mode
895  ENET1->TCR |= ENET_TCR_FDEN_MASK;
896  //Receive path operates independently of transmit
897  ENET1->RCR &= ~ENET_RCR_DRT_MASK;
898  }
899  else
900  {
901  //Half-duplex mode
902  ENET1->TCR &= ~ENET_TCR_FDEN_MASK;
903  //Disable reception of frames while transmitting
904  ENET1->RCR |= ENET_RCR_DRT_MASK;
905  }
906 
907  //Reset buffer descriptors
908  mcimx6ulEth1InitBufferDesc(interface);
909 
910  //Re-enable Ethernet MAC
911  ENET1->ECR |= ENET_ECR_ETHEREN_MASK;
912  //Instruct the DMA to poll the receive descriptor list
913  ENET1->RDAR = ENET_RDAR_RDAR_MASK;
914 
915  //Successful processing
916  return NO_ERROR;
917 }
918 
919 
920 /**
921  * @brief Write PHY register
922  * @param[in] opcode Access type (2 bits)
923  * @param[in] phyAddr PHY address (5 bits)
924  * @param[in] regAddr Register address (5 bits)
925  * @param[in] data Register value
926  **/
927 
928 void mcimx6ulEth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
929  uint8_t regAddr, uint16_t data)
930 {
931  uint32_t temp;
932 
933  //Valid opcode?
934  if(opcode == SMI_OPCODE_WRITE)
935  {
936  //Set up a write operation
937  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
938  //PHY address
939  temp |= ENET_MMFR_PA(phyAddr);
940  //Register address
941  temp |= ENET_MMFR_RA(regAddr);
942  //Register value
943  temp |= ENET_MMFR_DATA(data);
944 
945  //Clear MII interrupt flag
946  ENET1->EIR = ENET_EIR_MII_MASK;
947  //Start a write operation
948  ENET1->MMFR = temp;
949 
950  //Wait for the write to complete
951  while(!(ENET1->EIR & ENET_EIR_MII_MASK))
952  {
953  }
954  }
955  else
956  {
957  //The MAC peripheral only supports standard Clause 22 opcodes
958  }
959 }
960 
961 
962 /**
963  * @brief Read PHY register
964  * @param[in] opcode Access type (2 bits)
965  * @param[in] phyAddr PHY address (5 bits)
966  * @param[in] regAddr Register address (5 bits)
967  * @return Register value
968  **/
969 
970 uint16_t mcimx6ulEth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
971  uint8_t regAddr)
972 {
973  uint16_t data;
974  uint32_t temp;
975 
976  //Valid opcode?
977  if(opcode == SMI_OPCODE_READ)
978  {
979  //Set up a read operation
980  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
981  //PHY address
982  temp |= ENET_MMFR_PA(phyAddr);
983  //Register address
984  temp |= ENET_MMFR_RA(regAddr);
985 
986  //Clear MII interrupt flag
987  ENET1->EIR = ENET_EIR_MII_MASK;
988  //Start a read operation
989  ENET1->MMFR = temp;
990 
991  //Wait for the read to complete
992  while(!(ENET1->EIR & ENET_EIR_MII_MASK))
993  {
994  }
995 
996  //Get register value
997  data = ENET1->MMFR & ENET_MMFR_DATA_MASK;
998  }
999  else
1000  {
1001  //The MAC peripheral only supports standard Clause 22 opcodes
1002  data = 0;
1003  }
1004 
1005  //Return the value of the PHY register
1006  return data;
1007 }
1008 
1009 
1010 /**
1011  * @brief CRC calculation
1012  * @param[in] data Pointer to the data over which to calculate the CRC
1013  * @param[in] length Number of bytes to process
1014  * @return Resulting CRC value
1015  **/
1016 
1017 uint32_t mcimx6ulEth1CalcCrc(const void *data, size_t length)
1018 {
1019  uint_t i;
1020  uint_t j;
1021 
1022  //Point to the data over which to calculate the CRC
1023  const uint8_t *p = (uint8_t *) data;
1024  //CRC preset value
1025  uint32_t crc = 0xFFFFFFFF;
1026 
1027  //Loop through data
1028  for(i = 0; i < length; i++)
1029  {
1030  //Update CRC value
1031  crc ^= p[i];
1032  //The message is processed bit by bit
1033  for(j = 0; j < 8; j++)
1034  {
1035  if(crc & 0x00000001)
1036  crc = (crc >> 1) ^ 0xEDB88320;
1037  else
1038  crc = crc >> 1;
1039  }
1040  }
1041 
1042  //Return CRC value
1043  return crc;
1044 }
#define MCIMX6UL_ETH1_TX_BUFFER_COUNT
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ENET_RBD0_L
#define ENET_RBD0_W
error_t mcimx6ulEth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ENET_RBD0_OV
TCP/IP stack core.
void mcimx6ulEth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Debugging facilities.
uint8_t p
Definition: ndp.h:298
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MCIMX6UL_ETH1_RX_BUFFER_COUNT
uint16_t mcimx6ulEth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define ENET_TBD2_INT
#define MCIMX6UL_ETH1_RX_BUFFER_SIZE
#define txBuffer
#define SMI_OPCODE_READ
Definition: nic.h:63
i.MX6UL Ethernet MAC controller (ENET1 instance)
const NicDriver mcimx6ulEth1Driver
i.MX6UL Ethernet MAC driver
#define ENET_RBD0_LG
__start_packed struct @108 MacAddr
MAC address.
error_t mcimx6ulEth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define ENET_RBD0_E
error_t mcimx6ulEth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ENET_TBD0_R
#define ENET_RBD0_NO
void mcimx6ulEth1EnableIrq(NetInterface *interface)
Enable interrupts.
#define MCIMX6UL_ETH1_IRQ_PRIORITY
uint8_t opcode
Definition: dns_common.h:172
void mcimx6ulEth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define ENET_TBD0_DATA_LENGTH
#define ENET_RBD0_CR
void mcimx6ulEth1DisableIrq(NetInterface *interface)
Disable interrupts.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
NIC driver.
Definition: nic.h:179
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:79
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:74
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
unsigned int uint_t
Definition: compiler_port.h:45
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
void mcimx6ulEth1InitGpio(NetInterface *interface)
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
error_t mcimx6ulEth1ReceivePacket(NetInterface *interface)
Receive a packet.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define MCIMX6UL_ETH1_TX_BUFFER_SIZE
void mcimx6ulEth1EventHandler(NetInterface *interface)
i.MX6UL Ethernet MAC event handler
uint32_t mcimx6ulEth1CalcCrc(const void *data, size_t length)
CRC calculation.
#define osExitIsr(flag)
#define osEnterIsr()
void mcimx6ulEth1Tick(NetInterface *interface)
i.MX6UL Ethernet MAC timer handler
error_t mcimx6ulEth1Init(NetInterface *interface)
i.MX6UL Ethernet MAC initialization
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
void ENET1_DriverIRQHandler(uint32_t giccIar, void *userParam)
Ethernet MAC interrupt (ENET1 instance)
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106