mimxrt1020_eth_driver.c
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1 /**
2  * @file mimxrt1020_eth_driver.c
3  * @brief i.MX RT1020 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = ".ram_no_cache"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = ".ram_no_cache"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = ".ram_no_cache"
59 static uint32_t txBufferDesc[MIMXRT1020_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = ".ram_no_cache"
63 static uint32_t rxBufferDesc[MIMXRT1020_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__(".ram_no_cache")));
71 //RX buffer
73  __attribute__((aligned(16), __section__(".ram_no_cache")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1020_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__(".ram_no_cache")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1020_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__(".ram_no_cache")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1020 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1020 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1020 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1020EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET->ECR & ENET_ECR_RESET_MASK);
141 
142  //Receive control register
143  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1020_ETH_RX_BUFFER_SIZE) |
144  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
145 
146  //Transmit control register
147  ENET->TCR = 0;
148  //Configure MDC clock frequency
149  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
150 
151  //PHY transceiver initialization
152  error = interface->phyDriver->init(interface);
153  //Failed to initialize PHY transceiver?
154  if(error)
155  return error;
156 
157  //Set the MAC address of the station (upper 16 bits)
158  value = interface->macAddr.b[5];
159  value |= (interface->macAddr.b[4] << 8);
160  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
161 
162  //Set the MAC address of the station (lower 32 bits)
163  value = interface->macAddr.b[3];
164  value |= (interface->macAddr.b[2] << 8);
165  value |= (interface->macAddr.b[1] << 16);
166  value |= (interface->macAddr.b[0] << 24);
167  ENET->PALR = ENET_PALR_PADDR1(value);
168 
169  //Hash table for unicast address filtering
170  ENET->IALR = 0;
171  ENET->IAUR = 0;
172  //Hash table for multicast address filtering
173  ENET->GALR = 0;
174  ENET->GAUR = 0;
175 
176  //Disable transmit accelerator functions
177  ENET->TACC = 0;
178  //Disable receive accelerator functions
179  ENET->RACC = 0;
180 
181  //Use enhanced buffer descriptors
182  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
183  //Clear MIC counters
184  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
185 
186  //Initialize buffer descriptors
187  mimxrt1020EthInitBufferDesc(interface);
188 
189  //Clear any pending interrupts
190  ENET->EIR = 0xFFFFFFFF;
191  //Enable desired interrupts
192  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
193 
194  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
195  NVIC_SetPriorityGrouping(MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING);
196 
197  //Configure ENET interrupt priority
198  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING,
200 
201  //Enable Ethernet MAC
202  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
203  //Instruct the DMA to poll the receive descriptor list
204  ENET->RDAR = ENET_RDAR_RDAR_MASK;
205 
206  //Accept any packets from the upper layer
207  osSetEvent(&interface->nicTxEvent);
208 
209  //Successful initialization
210  return NO_ERROR;
211 }
212 
213 
214 //MIMXRT1020-EVK evaluation board?
215 #if defined(USE_MIMXRT1020_EVK)
216 
217 /**
218  * @brief GPIO configuration
219  * @param[in] interface Underlying network interface
220  **/
221 
222 void mimxrt1020EthInitGpio(NetInterface *interface)
223 {
224  gpio_pin_config_t pinConfig;
225  clock_enet_pll_config_t pllConfig;
226 
227  //Configure ENET PLL (50MHz)
228  pllConfig.enableClkOutput = true;
229  pllConfig.enableClkOutput500M = false;
230  pllConfig.enableClkOutput25M = false;
231  pllConfig.loopDivider = 1;
232  pllConfig.src = 0;
233  CLOCK_InitEnetPll(&pllConfig);
234 
235  //Enable ENET1_TX_CLK output driver
236  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
237 
238  //Enable IOMUXC clock
239  CLOCK_EnableClock(kCLOCK_Iomuxc);
240 
241  //Configure GPIO_AD_B0_08 pin as ENET_REF_CLK1
242  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1);
243 
244  //Set GPIO_AD_B0_08 pad properties
245  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1,
246  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
247  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
248  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
249  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
250  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
251  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
252  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
253  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
254 
255  //Configure GPIO_AD_B0_09 pin as ENET_RDATA01
256  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0);
257 
258  //Set GPIO_AD_B0_09 pad properties
259  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01,
260  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
261  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
262  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
263  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
264  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
265  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
266  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
267  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
268 
269  //Configure GPIO_AD_B0_10 pin as ENET_RDATA00
270  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0);
271 
272  //Set GPIO_AD_B0_10 pad properties
273  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00,
274  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
275  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
276  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
277  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
278  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
279  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
280  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
281  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
282 
283  //Configure GPIO_AD_B0_11 pin as ENET_RX_EN
284  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0);
285 
286  //Set GPIO_AD_B0_11 pad properties
287  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN,
288  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
289  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
290  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
291  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
292  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
293  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
294  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
295  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
296 
297  //Configure GPIO_AD_B0_12 pin as ENET_RX_ER
298  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0);
299 
300  //Set GPIO_AD_B0_12 pad properties
301  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER,
302  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
303  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
304  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
305  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
306  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
307  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
308  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
309  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
310 
311  //Configure GPIO_AD_B0_13 pin as ENET_TX_EN
312  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0);
313 
314  //Set GPIO_AD_B0_13 pad properties
315  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN,
316  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
317  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
318  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
319  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
320  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
321  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
322  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
323  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
324 
325  //Configure GPIO_AD_B0_14 pin as ENET_TX_DATA00
326  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0);
327 
328  //Set GPIO_AD_B0_14 pad properties
329  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00,
330  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
331  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
332  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
333  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
334  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
335  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
336  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
337  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
338 
339  //Configure GPIO_AD_B0_15 pin as ENET_TX_DATA01
340  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0);
341 
342  //Set GPIO_AD_B0_15 pad properties
343  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01,
344  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
345  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
346  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
347  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
348  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
349  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
350  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
351  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
352 
353  //Configure GPIO_EMC_40 pin as ENET_MDIO
354  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0);
355 
356  //Set GPIO_EMC_40 pad properties
357  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO,
358  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
359  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
360  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
361  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
362  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
363  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
364  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
365  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
366 
367  //Configure GPIO_EMC_41 pin as ENET_MDC
368  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0);
369 
370  //Set GPIO_EMC_41 pad properties
371  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC,
372  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
373  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
374  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
375  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
376  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
377  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
378  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
379  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
380 
381  //Configure GPIO_AD_B0_04 pin as GPIO1_IO04
382  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0);
383 
384  //Set GPIO_AD_B0_09 pad properties
385  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04,
386  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
387  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
388  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
389  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
390  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
391  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
392  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
393  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
394 
395  //Configure GPIO_AD_B1_06 pin as GPIO1_IO22
396  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0);
397 
398  //Set GPIO_AD_B1_06 pad properties
399  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22,
400  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
401  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
402  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
403  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
404  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
405  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
406  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
407  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
408 
409  //Configure ENET_RST as an output
410  pinConfig.direction = kGPIO_DigitalOutput;
411  pinConfig.outputLogic = 0;
412  pinConfig.interruptMode = kGPIO_NoIntmode;
413  GPIO_PinInit(GPIO1, 4, &pinConfig);
414 
415  //Configure ENET_INT as an input
416  pinConfig.direction = kGPIO_DigitalInput;
417  pinConfig.outputLogic = 0;
418  pinConfig.interruptMode = kGPIO_NoIntmode;
419  GPIO_PinInit(GPIO1, 22, &pinConfig);
420 
421  //Reset PHY transceiver (hard reset)
422  GPIO_PinWrite(GPIO1, 4, 0);
423  sleep(10);
424  GPIO_PinWrite(GPIO1, 4, 1);
425  sleep(10);
426 }
427 
428 #endif
429 
430 
431 /**
432  * @brief Initialize buffer descriptors
433  * @param[in] interface Underlying network interface
434  **/
435 
437 {
438  uint_t i;
439  uint32_t address;
440 
441  //Clear TX and RX buffer descriptors
442  memset(txBufferDesc, 0, sizeof(txBufferDesc));
443  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
444 
445  //Initialize TX buffer descriptors
446  for(i = 0; i < MIMXRT1020_ETH_TX_BUFFER_COUNT; i++)
447  {
448  //Calculate the address of the current TX buffer
449  address = (uint32_t) txBuffer[i];
450  //Transmit buffer address
451  txBufferDesc[i][1] = address;
452  //Generate interrupts
453  txBufferDesc[i][2] = ENET_TBD2_INT;
454  }
455 
456  //Mark the last descriptor entry with the wrap flag
457  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
458  //Initialize TX buffer index
459  txBufferIndex = 0;
460 
461  //Initialize RX buffer descriptors
462  for(i = 0; i < MIMXRT1020_ETH_RX_BUFFER_COUNT; i++)
463  {
464  //Calculate the address of the current RX buffer
465  address = (uint32_t) rxBuffer[i];
466  //The descriptor is initially owned by the DMA
467  rxBufferDesc[i][0] = ENET_RBD0_E;
468  //Receive buffer address
469  rxBufferDesc[i][1] = address;
470  //Generate interrupts
471  rxBufferDesc[i][2] = ENET_RBD2_INT;
472  }
473 
474  //Mark the last descriptor entry with the wrap flag
475  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
476  //Initialize RX buffer index
477  rxBufferIndex = 0;
478 
479  //Start location of the TX descriptor list
480  ENET->TDSR = (uint32_t) txBufferDesc;
481  //Start location of the RX descriptor list
482  ENET->RDSR = (uint32_t) rxBufferDesc;
483  //Maximum receive buffer size
484  ENET->MRBR = MIMXRT1020_ETH_RX_BUFFER_SIZE;
485 }
486 
487 
488 /**
489  * @brief i.MX RT1020 Ethernet MAC timer handler
490  *
491  * This routine is periodically called by the TCP/IP stack to
492  * handle periodic operations such as polling the link state
493  *
494  * @param[in] interface Underlying network interface
495  **/
496 
498 {
499  //Handle periodic operations
500  interface->phyDriver->tick(interface);
501 }
502 
503 
504 /**
505  * @brief Enable interrupts
506  * @param[in] interface Underlying network interface
507  **/
508 
510 {
511  //Enable Ethernet MAC interrupts
512  NVIC_EnableIRQ(ENET_IRQn);
513  //Enable Ethernet PHY interrupts
514  interface->phyDriver->enableIrq(interface);
515 }
516 
517 
518 /**
519  * @brief Disable interrupts
520  * @param[in] interface Underlying network interface
521  **/
522 
524 {
525  //Disable Ethernet MAC interrupts
526  NVIC_DisableIRQ(ENET_IRQn);
527  //Disable Ethernet PHY interrupts
528  interface->phyDriver->disableIrq(interface);
529 }
530 
531 
532 /**
533  * @brief Ethernet MAC interrupt
534  **/
535 
536 void ENET_IRQHandler(void)
537 {
538  bool_t flag;
539  uint32_t events;
540 
541  //Enter interrupt service routine
542  osEnterIsr();
543 
544  //This flag will be set if a higher priority task must be woken
545  flag = FALSE;
546  //Read interrupt event register
547  events = ENET->EIR;
548 
549  //A packet has been transmitted?
550  if(events & ENET_EIR_TXF_MASK)
551  {
552  //Clear TXF interrupt flag
553  ENET->EIR = ENET_EIR_TXF_MASK;
554 
555  //Check whether the TX buffer is available for writing
556  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
557  {
558  //Notify the TCP/IP stack that the transmitter is ready to send
559  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
560  }
561 
562  //Instruct the DMA to poll the transmit descriptor list
563  ENET->TDAR = ENET_TDAR_TDAR_MASK;
564  }
565 
566  //A packet has been received?
567  if(events & ENET_EIR_RXF_MASK)
568  {
569  //Disable RXF interrupt
570  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
571 
572  //Set event flag
573  nicDriverInterface->nicEvent = TRUE;
574  //Notify the TCP/IP stack of the event
575  flag = osSetEventFromIsr(&netEvent);
576  }
577 
578  //System bus error?
579  if(events & ENET_EIR_EBERR_MASK)
580  {
581  //Disable EBERR interrupt
582  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
583 
584  //Set event flag
585  nicDriverInterface->nicEvent = TRUE;
586  //Notify the TCP/IP stack of the event
587  flag |= osSetEventFromIsr(&netEvent);
588  }
589 
590  //Leave interrupt service routine
591  osExitIsr(flag);
592 }
593 
594 
595 /**
596  * @brief i.MX RT1020 Ethernet MAC event handler
597  * @param[in] interface Underlying network interface
598  **/
599 
601 {
602  error_t error;
603  uint32_t status;
604 
605  //Read interrupt event register
606  status = ENET->EIR;
607 
608  //Packet received?
609  if(status & ENET_EIR_RXF_MASK)
610  {
611  //Clear RXF interrupt flag
612  ENET->EIR = ENET_EIR_RXF_MASK;
613 
614  //Process all pending packets
615  do
616  {
617  //Read incoming packet
618  error = mimxrt1020EthReceivePacket(interface);
619 
620  //No more data in the receive buffer?
621  } while(error != ERROR_BUFFER_EMPTY);
622  }
623 
624  //System bus error?
625  if(status & ENET_EIR_EBERR_MASK)
626  {
627  //Clear EBERR interrupt flag
628  ENET->EIR = ENET_EIR_EBERR_MASK;
629 
630  //Disable Ethernet MAC
631  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
632  //Reset buffer descriptors
633  mimxrt1020EthInitBufferDesc(interface);
634  //Resume normal operation
635  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
636  //Instruct the DMA to poll the receive descriptor list
637  ENET->RDAR = ENET_RDAR_RDAR_MASK;
638  }
639 
640  //Re-enable Ethernet MAC interrupts
641  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
642 }
643 
644 
645 /**
646  * @brief Send a packet
647  * @param[in] interface Underlying network interface
648  * @param[in] buffer Multi-part buffer containing the data to send
649  * @param[in] offset Offset to the first data byte
650  * @return Error code
651  **/
652 
654  const NetBuffer *buffer, size_t offset)
655 {
656  static uint8_t temp[MIMXRT1020_ETH_TX_BUFFER_SIZE];
657  size_t length;
658 
659  //Retrieve the length of the packet
660  length = netBufferGetLength(buffer) - offset;
661 
662  //Check the frame length
664  {
665  //The transmitter can accept another packet
666  osSetEvent(&interface->nicTxEvent);
667  //Report an error
668  return ERROR_INVALID_LENGTH;
669  }
670 
671  //Make sure the current buffer is available for writing
672  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
673  return ERROR_FAILURE;
674 
675  //Copy user data to the transmit buffer
676  netBufferRead(temp, buffer, offset, length);
677  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
678 
679  //Clear BDU flag
680  txBufferDesc[txBufferIndex][4] = 0;
681 
682  //Check current index
683  if(txBufferIndex < (MIMXRT1020_ETH_TX_BUFFER_COUNT - 1))
684  {
685  //Give the ownership of the descriptor to the DMA engine
686  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
688 
689  //Point to the next buffer
690  txBufferIndex++;
691  }
692  else
693  {
694  //Give the ownership of the descriptor to the DMA engine
695  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
697 
698  //Wrap around
699  txBufferIndex = 0;
700  }
701 
702  //Data synchronization barrier
703  __DSB();
704 
705  //Instruct the DMA to poll the transmit descriptor list
706  ENET->TDAR = ENET_TDAR_TDAR_MASK;
707 
708  //Check whether the next buffer is available for writing
709  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
710  {
711  //The transmitter can accept another packet
712  osSetEvent(&interface->nicTxEvent);
713  }
714 
715  //Successful processing
716  return NO_ERROR;
717 }
718 
719 
720 /**
721  * @brief Receive a packet
722  * @param[in] interface Underlying network interface
723  * @return Error code
724  **/
725 
727 {
728  static uint8_t temp[MIMXRT1020_ETH_RX_BUFFER_SIZE];
729  error_t error;
730  size_t n;
731 
732  //Make sure the current buffer is available for reading
733  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
734  {
735  //The frame should not span multiple buffers
736  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
737  {
738  //Check whether an error occurred
739  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
741  {
742  //Retrieve the length of the frame
743  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
744  //Limit the number of data to read
746 
747  //Copy data from the receive buffer
748  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
749 
750  //Pass the packet to the upper layer
751  nicProcessPacket(interface, temp, n);
752 
753  //Valid packet received
754  error = NO_ERROR;
755  }
756  else
757  {
758  //The received packet contains an error
759  error = ERROR_INVALID_PACKET;
760  }
761  }
762  else
763  {
764  //The packet is not valid
765  error = ERROR_INVALID_PACKET;
766  }
767 
768  //Clear BDU flag
769  rxBufferDesc[rxBufferIndex][4] = 0;
770 
771  //Check current index
772  if(rxBufferIndex < (MIMXRT1020_ETH_RX_BUFFER_COUNT - 1))
773  {
774  //Give the ownership of the descriptor back to the DMA engine
775  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
776  //Point to the next buffer
777  rxBufferIndex++;
778  }
779  else
780  {
781  //Give the ownership of the descriptor back to the DMA engine
782  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
783  //Wrap around
784  rxBufferIndex = 0;
785  }
786 
787  //Instruct the DMA to poll the receive descriptor list
788  ENET->RDAR = ENET_RDAR_RDAR_MASK;
789  }
790  else
791  {
792  //No more data in the receive buffer
793  error = ERROR_BUFFER_EMPTY;
794  }
795 
796  //Return status code
797  return error;
798 }
799 
800 
801 /**
802  * @brief Configure MAC address filtering
803  * @param[in] interface Underlying network interface
804  * @return Error code
805  **/
806 
808 {
809  uint_t i;
810  uint_t k;
811  uint32_t crc;
812  uint32_t unicastHashTable[2];
813  uint32_t multicastHashTable[2];
814  MacFilterEntry *entry;
815 
816  //Debug message
817  TRACE_DEBUG("Updating MAC filter...\r\n");
818 
819  //Clear hash table (unicast address filtering)
820  unicastHashTable[0] = 0;
821  unicastHashTable[1] = 0;
822 
823  //Clear hash table (multicast address filtering)
824  multicastHashTable[0] = 0;
825  multicastHashTable[1] = 0;
826 
827  //The MAC address filter contains the list of MAC addresses to accept
828  //when receiving an Ethernet frame
829  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
830  {
831  //Point to the current entry
832  entry = &interface->macAddrFilter[i];
833 
834  //Valid entry?
835  if(entry->refCount > 0)
836  {
837  //Compute CRC over the current MAC address
838  crc = mimxrt1020EthCalcCrc(&entry->addr, sizeof(MacAddr));
839 
840  //The upper 6 bits in the CRC register are used to index the
841  //contents of the hash table
842  k = (crc >> 26) & 0x3F;
843 
844  //Multicast address?
845  if(macIsMulticastAddr(&entry->addr))
846  {
847  //Update the multicast hash table
848  multicastHashTable[k / 32] |= (1 << (k % 32));
849  }
850  else
851  {
852  //Update the unicast hash table
853  unicastHashTable[k / 32] |= (1 << (k % 32));
854  }
855  }
856  }
857 
858  //Write the hash table (unicast address filtering)
859  ENET->IALR = unicastHashTable[0];
860  ENET->IAUR = unicastHashTable[1];
861 
862  //Write the hash table (multicast address filtering)
863  ENET->GALR = multicastHashTable[0];
864  ENET->GAUR = multicastHashTable[1];
865 
866  //Debug message
867  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
868  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
869  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
870  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
871 
872  //Successful processing
873  return NO_ERROR;
874 }
875 
876 
877 /**
878  * @brief Adjust MAC configuration parameters for proper operation
879  * @param[in] interface Underlying network interface
880  * @return Error code
881  **/
882 
884 {
885  //Disable Ethernet MAC while modifying configuration registers
886  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
887 
888  //10BASE-T or 100BASE-TX operation mode?
889  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
890  {
891  //100 Mbps operation
892  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
893  }
894  else
895  {
896  //10 Mbps operation
897  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
898  }
899 
900  //Half-duplex or full-duplex mode?
901  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
902  {
903  //Full-duplex mode
904  ENET->TCR |= ENET_TCR_FDEN_MASK;
905  //Receive path operates independently of transmit
906  ENET->RCR &= ~ENET_RCR_DRT_MASK;
907  }
908  else
909  {
910  //Half-duplex mode
911  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
912  //Disable reception of frames while transmitting
913  ENET->RCR |= ENET_RCR_DRT_MASK;
914  }
915 
916  //Reset buffer descriptors
917  mimxrt1020EthInitBufferDesc(interface);
918 
919  //Re-enable Ethernet MAC
920  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
921  //Instruct the DMA to poll the receive descriptor list
922  ENET->RDAR = ENET_RDAR_RDAR_MASK;
923 
924  //Successful processing
925  return NO_ERROR;
926 }
927 
928 
929 /**
930  * @brief Write PHY register
931  * @param[in] phyAddr PHY address
932  * @param[in] regAddr Register address
933  * @param[in] data Register value
934  **/
935 
936 void mimxrt1020EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
937 {
938  uint32_t value;
939 
940  //Set up a write operation
941  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
942  //PHY address
943  value |= ENET_MMFR_PA(phyAddr);
944  //Register address
945  value |= ENET_MMFR_RA(regAddr);
946  //Register value
947  value |= ENET_MMFR_DATA(data);
948 
949  //Clear MII interrupt flag
950  ENET->EIR = ENET_EIR_MII_MASK;
951  //Start a write operation
952  ENET->MMFR = value;
953  //Wait for the write to complete
954  while(!(ENET->EIR & ENET_EIR_MII_MASK));
955 }
956 
957 
958 /**
959  * @brief Read PHY register
960  * @param[in] phyAddr PHY address
961  * @param[in] regAddr Register address
962  * @return Register value
963  **/
964 
965 uint16_t mimxrt1020EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
966 {
967  uint32_t value;
968 
969  //Set up a read operation
970  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
971  //PHY address
972  value |= ENET_MMFR_PA(phyAddr);
973  //Register address
974  value |= ENET_MMFR_RA(regAddr);
975 
976  //Clear MII interrupt flag
977  ENET->EIR = ENET_EIR_MII_MASK;
978  //Start a read operation
979  ENET->MMFR = value;
980  //Wait for the read to complete
981  while(!(ENET->EIR & ENET_EIR_MII_MASK));
982 
983  //Return PHY register contents
984  return ENET->MMFR & ENET_MMFR_DATA_MASK;
985 }
986 
987 
988 /**
989  * @brief CRC calculation
990  * @param[in] data Pointer to the data over which to calculate the CRC
991  * @param[in] length Number of bytes to process
992  * @return Resulting CRC value
993  **/
994 
995 uint32_t mimxrt1020EthCalcCrc(const void *data, size_t length)
996 {
997  uint_t i;
998  uint_t j;
999 
1000  //Point to the data over which to calculate the CRC
1001  const uint8_t *p = (uint8_t *) data;
1002  //CRC preset value
1003  uint32_t crc = 0xFFFFFFFF;
1004 
1005  //Loop through data
1006  for(i = 0; i < length; i++)
1007  {
1008  //Update CRC value
1009  crc ^= p[i];
1010  //The message is processed bit by bit
1011  for(j = 0; j < 8; j++)
1012  {
1013  if(crc & 0x00000001)
1014  crc = (crc >> 1) ^ 0xEDB88320;
1015  else
1016  crc = crc >> 1;
1017  }
1018  }
1019 
1020  //Return CRC value
1021  return crc;
1022 }
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ENET_RBD0_L
#define ENET_RBD0_W
error_t mimxrt1020EthInit(NetInterface *interface)
i.MX RT1020 Ethernet MAC initialization
#define ENET_RBD0_OV
TCP/IP stack core.
void mimxrt1020EthInitGpio(NetInterface *interface)
Debugging facilities.
error_t mimxrt1020EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t p
Definition: ndp.h:297
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define ENET_TBD2_INT
#define txBuffer
const NicDriver mimxrt1020EthDriver
i.MX RT1020 Ethernet MAC driver
i.MX RT1020 Ethernet MAC controller
#define sleep(delay)
Definition: os_port.h:128
#define MIMXRT1020_ETH_RX_BUFFER_COUNT
void mimxrt1020EthTick(NetInterface *interface)
i.MX RT1020 Ethernet MAC timer handler
#define ENET_RBD0_LG
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define ENET_RBD0_E
#define ENET_TBD0_R
#define ENET_RBD0_NO
void mimxrt1020EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ENET_TBD0_DATA_LENGTH
#define MIMXRT1020_ETH_IRQ_GROUP_PRIORITY
uint32_t mimxrt1020EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_CR
void mimxrt1020EthEventHandler(NetInterface *interface)
i.MX RT1020 Ethernet MAC event handler
#define MIMXRT1020_ETH_IRQ_SUB_PRIORITY
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
error_t mimxrt1020EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
NIC driver.
Definition: nic.h:164
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t mimxrt1020EthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void mimxrt1020EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void mimxrt1020EthEnableIrq(NetInterface *interface)
Enable interrupts.
void mimxrt1020EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t mimxrt1020EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:71
#define MIMXRT1020_ETH_TX_BUFFER_SIZE
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:76
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
error_t mimxrt1020EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
unsigned int uint_t
Definition: compiler_port.h:45
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:169
#define MIMXRT1020_ETH_TX_BUFFER_COUNT
#define NetInterface
Definition: net.h:36
#define MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING
uint8_t value[]
Definition: dtls_misc.h:143
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define osExitIsr(flag)
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
#define osEnterIsr()
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define MIMXRT1020_ETH_RX_BUFFER_SIZE