mimxrt1020_eth_driver.c
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1 /**
2  * @file mimxrt1020_eth_driver.c
3  * @brief i.MX RT1020 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = ".ram_no_cache"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = ".ram_no_cache"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = ".ram_no_cache"
59 static uint32_t txBufferDesc[MIMXRT1020_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = ".ram_no_cache"
63 static uint32_t rxBufferDesc[MIMXRT1020_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__(".ram_no_cache")));
71 //RX buffer
73  __attribute__((aligned(16), __section__(".ram_no_cache")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1020_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__(".ram_no_cache")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1020_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__(".ram_no_cache")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1020 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1020 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1020 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1020EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET->ECR & ENET_ECR_RESET_MASK)
141  {
142  }
143 
144  //Receive control register
145  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1020_ETH_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET->TCR = 0;
150  //Configure MDC clock frequency
151  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //PHY transceiver initialization
154  error = interface->phyDriver->init(interface);
155  //Failed to initialize PHY transceiver?
156  if(error)
157  return error;
158 
159  //Set the MAC address of the station (upper 16 bits)
160  value = interface->macAddr.b[5];
161  value |= (interface->macAddr.b[4] << 8);
162  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
163 
164  //Set the MAC address of the station (lower 32 bits)
165  value = interface->macAddr.b[3];
166  value |= (interface->macAddr.b[2] << 8);
167  value |= (interface->macAddr.b[1] << 16);
168  value |= (interface->macAddr.b[0] << 24);
169  ENET->PALR = ENET_PALR_PADDR1(value);
170 
171  //Hash table for unicast address filtering
172  ENET->IALR = 0;
173  ENET->IAUR = 0;
174  //Hash table for multicast address filtering
175  ENET->GALR = 0;
176  ENET->GAUR = 0;
177 
178  //Disable transmit accelerator functions
179  ENET->TACC = 0;
180  //Disable receive accelerator functions
181  ENET->RACC = 0;
182 
183  //Use enhanced buffer descriptors
184  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
185  //Clear MIC counters
186  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
187 
188  //Initialize buffer descriptors
189  mimxrt1020EthInitBufferDesc(interface);
190 
191  //Clear any pending interrupts
192  ENET->EIR = 0xFFFFFFFF;
193  //Enable desired interrupts
194  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
195 
196  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
197  NVIC_SetPriorityGrouping(MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING);
198 
199  //Configure ENET interrupt priority
200  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING,
202 
203  //Enable Ethernet MAC
204  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
205  //Instruct the DMA to poll the receive descriptor list
206  ENET->RDAR = ENET_RDAR_RDAR_MASK;
207 
208  //Accept any packets from the upper layer
209  osSetEvent(&interface->nicTxEvent);
210 
211  //Successful initialization
212  return NO_ERROR;
213 }
214 
215 
216 //MIMXRT1020-EVK evaluation board?
217 #if defined(USE_MIMXRT1020_EVK)
218 
219 /**
220  * @brief GPIO configuration
221  * @param[in] interface Underlying network interface
222  **/
223 
224 void mimxrt1020EthInitGpio(NetInterface *interface)
225 {
226  gpio_pin_config_t pinConfig;
227  clock_enet_pll_config_t pllConfig;
228 
229  //Configure ENET PLL (50MHz)
230  pllConfig.enableClkOutput = true;
231  pllConfig.enableClkOutput500M = false;
232  pllConfig.enableClkOutput25M = false;
233  pllConfig.loopDivider = 1;
234  pllConfig.src = 0;
235  CLOCK_InitEnetPll(&pllConfig);
236 
237  //Enable ENET1_TX_CLK output driver
238  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
239 
240  //Enable IOMUXC clock
241  CLOCK_EnableClock(kCLOCK_Iomuxc);
242 
243  //Configure GPIO_AD_B0_08 pin as ENET_REF_CLK1
244  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1);
245 
246  //Set GPIO_AD_B0_08 pad properties
247  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1,
248  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
249  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
250  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
251  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
252  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
253  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
254  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
255  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
256 
257  //Configure GPIO_AD_B0_09 pin as ENET_RDATA01
258  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0);
259 
260  //Set GPIO_AD_B0_09 pad properties
261  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01,
262  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
263  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
264  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
265  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
266  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
267  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
268  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
269  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
270 
271  //Configure GPIO_AD_B0_10 pin as ENET_RDATA00
272  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0);
273 
274  //Set GPIO_AD_B0_10 pad properties
275  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00,
276  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
277  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
278  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
279  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
280  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
281  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
282  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
283  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
284 
285  //Configure GPIO_AD_B0_11 pin as ENET_RX_EN
286  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0);
287 
288  //Set GPIO_AD_B0_11 pad properties
289  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN,
290  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
291  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
292  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
293  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
294  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
295  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
296  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
297  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
298 
299  //Configure GPIO_AD_B0_12 pin as ENET_RX_ER
300  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0);
301 
302  //Set GPIO_AD_B0_12 pad properties
303  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER,
304  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
305  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
306  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
307  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
308  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
309  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
310  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
311  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
312 
313  //Configure GPIO_AD_B0_13 pin as ENET_TX_EN
314  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0);
315 
316  //Set GPIO_AD_B0_13 pad properties
317  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN,
318  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
319  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
320  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
321  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
322  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
323  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
324  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
325  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
326 
327  //Configure GPIO_AD_B0_14 pin as ENET_TX_DATA00
328  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0);
329 
330  //Set GPIO_AD_B0_14 pad properties
331  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00,
332  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
333  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
334  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
335  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
336  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
337  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
338  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
339  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
340 
341  //Configure GPIO_AD_B0_15 pin as ENET_TX_DATA01
342  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0);
343 
344  //Set GPIO_AD_B0_15 pad properties
345  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01,
346  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
347  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
348  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
349  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
350  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
351  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
352  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
353  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
354 
355  //Configure GPIO_EMC_40 pin as ENET_MDIO
356  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0);
357 
358  //Set GPIO_EMC_40 pad properties
359  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO,
360  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
361  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
362  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
363  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
364  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
365  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
366  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
367  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
368 
369  //Configure GPIO_EMC_41 pin as ENET_MDC
370  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0);
371 
372  //Set GPIO_EMC_41 pad properties
373  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC,
374  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
375  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
376  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
377  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
378  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
379  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
380  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
381  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
382 
383  //Configure GPIO_AD_B0_04 pin as GPIO1_IO04
384  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0);
385 
386  //Set GPIO_AD_B0_09 pad properties
387  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04,
388  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
389  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
390  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
391  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
392  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
393  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
394  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
395  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
396 
397  //Configure GPIO_AD_B1_06 pin as GPIO1_IO22
398  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0);
399 
400  //Set GPIO_AD_B1_06 pad properties
401  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22,
402  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
403  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
404  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
405  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
406  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
407  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
408  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
409  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
410 
411  //Configure ENET_RST as an output
412  pinConfig.direction = kGPIO_DigitalOutput;
413  pinConfig.outputLogic = 0;
414  pinConfig.interruptMode = kGPIO_NoIntmode;
415  GPIO_PinInit(GPIO1, 4, &pinConfig);
416 
417  //Configure ENET_INT as an input
418  pinConfig.direction = kGPIO_DigitalInput;
419  pinConfig.outputLogic = 0;
420  pinConfig.interruptMode = kGPIO_NoIntmode;
421  GPIO_PinInit(GPIO1, 22, &pinConfig);
422 
423  //Reset PHY transceiver (hard reset)
424  GPIO_PinWrite(GPIO1, 4, 0);
425  sleep(10);
426  GPIO_PinWrite(GPIO1, 4, 1);
427  sleep(10);
428 }
429 
430 #endif
431 
432 
433 /**
434  * @brief Initialize buffer descriptors
435  * @param[in] interface Underlying network interface
436  **/
437 
439 {
440  uint_t i;
441  uint32_t address;
442 
443  //Clear TX and RX buffer descriptors
444  memset(txBufferDesc, 0, sizeof(txBufferDesc));
445  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
446 
447  //Initialize TX buffer descriptors
448  for(i = 0; i < MIMXRT1020_ETH_TX_BUFFER_COUNT; i++)
449  {
450  //Calculate the address of the current TX buffer
451  address = (uint32_t) txBuffer[i];
452  //Transmit buffer address
453  txBufferDesc[i][1] = address;
454  //Generate interrupts
455  txBufferDesc[i][2] = ENET_TBD2_INT;
456  }
457 
458  //Mark the last descriptor entry with the wrap flag
459  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
460  //Initialize TX buffer index
461  txBufferIndex = 0;
462 
463  //Initialize RX buffer descriptors
464  for(i = 0; i < MIMXRT1020_ETH_RX_BUFFER_COUNT; i++)
465  {
466  //Calculate the address of the current RX buffer
467  address = (uint32_t) rxBuffer[i];
468  //The descriptor is initially owned by the DMA
469  rxBufferDesc[i][0] = ENET_RBD0_E;
470  //Receive buffer address
471  rxBufferDesc[i][1] = address;
472  //Generate interrupts
473  rxBufferDesc[i][2] = ENET_RBD2_INT;
474  }
475 
476  //Mark the last descriptor entry with the wrap flag
477  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
478  //Initialize RX buffer index
479  rxBufferIndex = 0;
480 
481  //Start location of the TX descriptor list
482  ENET->TDSR = (uint32_t) txBufferDesc;
483  //Start location of the RX descriptor list
484  ENET->RDSR = (uint32_t) rxBufferDesc;
485  //Maximum receive buffer size
486  ENET->MRBR = MIMXRT1020_ETH_RX_BUFFER_SIZE;
487 }
488 
489 
490 /**
491  * @brief i.MX RT1020 Ethernet MAC timer handler
492  *
493  * This routine is periodically called by the TCP/IP stack to
494  * handle periodic operations such as polling the link state
495  *
496  * @param[in] interface Underlying network interface
497  **/
498 
500 {
501  //Handle periodic operations
502  interface->phyDriver->tick(interface);
503 }
504 
505 
506 /**
507  * @brief Enable interrupts
508  * @param[in] interface Underlying network interface
509  **/
510 
512 {
513  //Enable Ethernet MAC interrupts
514  NVIC_EnableIRQ(ENET_IRQn);
515  //Enable Ethernet PHY interrupts
516  interface->phyDriver->enableIrq(interface);
517 }
518 
519 
520 /**
521  * @brief Disable interrupts
522  * @param[in] interface Underlying network interface
523  **/
524 
526 {
527  //Disable Ethernet MAC interrupts
528  NVIC_DisableIRQ(ENET_IRQn);
529  //Disable Ethernet PHY interrupts
530  interface->phyDriver->disableIrq(interface);
531 }
532 
533 
534 /**
535  * @brief Ethernet MAC interrupt
536  **/
537 
538 void ENET_IRQHandler(void)
539 {
540  bool_t flag;
541  uint32_t events;
542 
543  //Interrupt service routine prologue
544  osEnterIsr();
545 
546  //This flag will be set if a higher priority task must be woken
547  flag = FALSE;
548  //Read interrupt event register
549  events = ENET->EIR;
550 
551  //A packet has been transmitted?
552  if(events & ENET_EIR_TXF_MASK)
553  {
554  //Clear TXF interrupt flag
555  ENET->EIR = ENET_EIR_TXF_MASK;
556 
557  //Check whether the TX buffer is available for writing
558  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
559  {
560  //Notify the TCP/IP stack that the transmitter is ready to send
561  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
562  }
563 
564  //Instruct the DMA to poll the transmit descriptor list
565  ENET->TDAR = ENET_TDAR_TDAR_MASK;
566  }
567 
568  //A packet has been received?
569  if(events & ENET_EIR_RXF_MASK)
570  {
571  //Disable RXF interrupt
572  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
573 
574  //Set event flag
575  nicDriverInterface->nicEvent = TRUE;
576  //Notify the TCP/IP stack of the event
577  flag = osSetEventFromIsr(&netEvent);
578  }
579 
580  //System bus error?
581  if(events & ENET_EIR_EBERR_MASK)
582  {
583  //Disable EBERR interrupt
584  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
585 
586  //Set event flag
587  nicDriverInterface->nicEvent = TRUE;
588  //Notify the TCP/IP stack of the event
589  flag |= osSetEventFromIsr(&netEvent);
590  }
591 
592  //Interrupt service routine epilogue
593  osExitIsr(flag);
594 }
595 
596 
597 /**
598  * @brief i.MX RT1020 Ethernet MAC event handler
599  * @param[in] interface Underlying network interface
600  **/
601 
603 {
604  error_t error;
605  uint32_t status;
606 
607  //Read interrupt event register
608  status = ENET->EIR;
609 
610  //Packet received?
611  if(status & ENET_EIR_RXF_MASK)
612  {
613  //Clear RXF interrupt flag
614  ENET->EIR = ENET_EIR_RXF_MASK;
615 
616  //Process all pending packets
617  do
618  {
619  //Read incoming packet
620  error = mimxrt1020EthReceivePacket(interface);
621 
622  //No more data in the receive buffer?
623  } while(error != ERROR_BUFFER_EMPTY);
624  }
625 
626  //System bus error?
627  if(status & ENET_EIR_EBERR_MASK)
628  {
629  //Clear EBERR interrupt flag
630  ENET->EIR = ENET_EIR_EBERR_MASK;
631 
632  //Disable Ethernet MAC
633  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
634  //Reset buffer descriptors
635  mimxrt1020EthInitBufferDesc(interface);
636  //Resume normal operation
637  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
638  //Instruct the DMA to poll the receive descriptor list
639  ENET->RDAR = ENET_RDAR_RDAR_MASK;
640  }
641 
642  //Re-enable Ethernet MAC interrupts
643  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
644 }
645 
646 
647 /**
648  * @brief Send a packet
649  * @param[in] interface Underlying network interface
650  * @param[in] buffer Multi-part buffer containing the data to send
651  * @param[in] offset Offset to the first data byte
652  * @return Error code
653  **/
654 
656  const NetBuffer *buffer, size_t offset)
657 {
658  static uint8_t temp[MIMXRT1020_ETH_TX_BUFFER_SIZE];
659  size_t length;
660 
661  //Retrieve the length of the packet
662  length = netBufferGetLength(buffer) - offset;
663 
664  //Check the frame length
666  {
667  //The transmitter can accept another packet
668  osSetEvent(&interface->nicTxEvent);
669  //Report an error
670  return ERROR_INVALID_LENGTH;
671  }
672 
673  //Make sure the current buffer is available for writing
674  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
675  return ERROR_FAILURE;
676 
677  //Copy user data to the transmit buffer
678  netBufferRead(temp, buffer, offset, length);
679  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
680 
681  //Clear BDU flag
682  txBufferDesc[txBufferIndex][4] = 0;
683 
684  //Check current index
685  if(txBufferIndex < (MIMXRT1020_ETH_TX_BUFFER_COUNT - 1))
686  {
687  //Give the ownership of the descriptor to the DMA engine
688  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
690 
691  //Point to the next buffer
692  txBufferIndex++;
693  }
694  else
695  {
696  //Give the ownership of the descriptor to the DMA engine
697  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
699 
700  //Wrap around
701  txBufferIndex = 0;
702  }
703 
704  //Data synchronization barrier
705  __DSB();
706 
707  //Instruct the DMA to poll the transmit descriptor list
708  ENET->TDAR = ENET_TDAR_TDAR_MASK;
709 
710  //Check whether the next buffer is available for writing
711  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
712  {
713  //The transmitter can accept another packet
714  osSetEvent(&interface->nicTxEvent);
715  }
716 
717  //Successful processing
718  return NO_ERROR;
719 }
720 
721 
722 /**
723  * @brief Receive a packet
724  * @param[in] interface Underlying network interface
725  * @return Error code
726  **/
727 
729 {
730  static uint8_t temp[MIMXRT1020_ETH_RX_BUFFER_SIZE];
731  error_t error;
732  size_t n;
733 
734  //Make sure the current buffer is available for reading
735  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
736  {
737  //The frame should not span multiple buffers
738  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
739  {
740  //Check whether an error occurred
741  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
743  {
744  //Retrieve the length of the frame
745  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
746  //Limit the number of data to read
748 
749  //Copy data from the receive buffer
750  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
751 
752  //Pass the packet to the upper layer
753  nicProcessPacket(interface, temp, n);
754 
755  //Valid packet received
756  error = NO_ERROR;
757  }
758  else
759  {
760  //The received packet contains an error
761  error = ERROR_INVALID_PACKET;
762  }
763  }
764  else
765  {
766  //The packet is not valid
767  error = ERROR_INVALID_PACKET;
768  }
769 
770  //Clear BDU flag
771  rxBufferDesc[rxBufferIndex][4] = 0;
772 
773  //Check current index
774  if(rxBufferIndex < (MIMXRT1020_ETH_RX_BUFFER_COUNT - 1))
775  {
776  //Give the ownership of the descriptor back to the DMA engine
777  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
778  //Point to the next buffer
779  rxBufferIndex++;
780  }
781  else
782  {
783  //Give the ownership of the descriptor back to the DMA engine
784  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
785  //Wrap around
786  rxBufferIndex = 0;
787  }
788 
789  //Instruct the DMA to poll the receive descriptor list
790  ENET->RDAR = ENET_RDAR_RDAR_MASK;
791  }
792  else
793  {
794  //No more data in the receive buffer
795  error = ERROR_BUFFER_EMPTY;
796  }
797 
798  //Return status code
799  return error;
800 }
801 
802 
803 /**
804  * @brief Configure MAC address filtering
805  * @param[in] interface Underlying network interface
806  * @return Error code
807  **/
808 
810 {
811  uint_t i;
812  uint_t k;
813  uint32_t crc;
814  uint32_t unicastHashTable[2];
815  uint32_t multicastHashTable[2];
816  MacFilterEntry *entry;
817 
818  //Debug message
819  TRACE_DEBUG("Updating MAC filter...\r\n");
820 
821  //Clear hash table (unicast address filtering)
822  unicastHashTable[0] = 0;
823  unicastHashTable[1] = 0;
824 
825  //Clear hash table (multicast address filtering)
826  multicastHashTable[0] = 0;
827  multicastHashTable[1] = 0;
828 
829  //The MAC address filter contains the list of MAC addresses to accept
830  //when receiving an Ethernet frame
831  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
832  {
833  //Point to the current entry
834  entry = &interface->macAddrFilter[i];
835 
836  //Valid entry?
837  if(entry->refCount > 0)
838  {
839  //Compute CRC over the current MAC address
840  crc = mimxrt1020EthCalcCrc(&entry->addr, sizeof(MacAddr));
841 
842  //The upper 6 bits in the CRC register are used to index the
843  //contents of the hash table
844  k = (crc >> 26) & 0x3F;
845 
846  //Multicast address?
847  if(macIsMulticastAddr(&entry->addr))
848  {
849  //Update the multicast hash table
850  multicastHashTable[k / 32] |= (1 << (k % 32));
851  }
852  else
853  {
854  //Update the unicast hash table
855  unicastHashTable[k / 32] |= (1 << (k % 32));
856  }
857  }
858  }
859 
860  //Write the hash table (unicast address filtering)
861  ENET->IALR = unicastHashTable[0];
862  ENET->IAUR = unicastHashTable[1];
863 
864  //Write the hash table (multicast address filtering)
865  ENET->GALR = multicastHashTable[0];
866  ENET->GAUR = multicastHashTable[1];
867 
868  //Debug message
869  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
870  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
871  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
872  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
873 
874  //Successful processing
875  return NO_ERROR;
876 }
877 
878 
879 /**
880  * @brief Adjust MAC configuration parameters for proper operation
881  * @param[in] interface Underlying network interface
882  * @return Error code
883  **/
884 
886 {
887  //Disable Ethernet MAC while modifying configuration registers
888  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
889 
890  //10BASE-T or 100BASE-TX operation mode?
891  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
892  {
893  //100 Mbps operation
894  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
895  }
896  else
897  {
898  //10 Mbps operation
899  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
900  }
901 
902  //Half-duplex or full-duplex mode?
903  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
904  {
905  //Full-duplex mode
906  ENET->TCR |= ENET_TCR_FDEN_MASK;
907  //Receive path operates independently of transmit
908  ENET->RCR &= ~ENET_RCR_DRT_MASK;
909  }
910  else
911  {
912  //Half-duplex mode
913  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
914  //Disable reception of frames while transmitting
915  ENET->RCR |= ENET_RCR_DRT_MASK;
916  }
917 
918  //Reset buffer descriptors
919  mimxrt1020EthInitBufferDesc(interface);
920 
921  //Re-enable Ethernet MAC
922  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
923  //Instruct the DMA to poll the receive descriptor list
924  ENET->RDAR = ENET_RDAR_RDAR_MASK;
925 
926  //Successful processing
927  return NO_ERROR;
928 }
929 
930 
931 /**
932  * @brief Write PHY register
933  * @param[in] opcode Access type (2 bits)
934  * @param[in] phyAddr PHY address (5 bits)
935  * @param[in] regAddr Register address (5 bits)
936  * @param[in] data Register value
937  **/
938 
939 void mimxrt1020EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
940  uint8_t regAddr, uint16_t data)
941 {
942  uint32_t temp;
943 
944  //Valid opcode?
945  if(opcode == SMI_OPCODE_WRITE)
946  {
947  //Set up a write operation
948  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
949  //PHY address
950  temp |= ENET_MMFR_PA(phyAddr);
951  //Register address
952  temp |= ENET_MMFR_RA(regAddr);
953  //Register value
954  temp |= ENET_MMFR_DATA(data);
955 
956  //Clear MII interrupt flag
957  ENET->EIR = ENET_EIR_MII_MASK;
958  //Start a write operation
959  ENET->MMFR = temp;
960 
961  //Wait for the write to complete
962  while(!(ENET->EIR & ENET_EIR_MII_MASK))
963  {
964  }
965  }
966  else
967  {
968  //The MAC peripheral only supports standard Clause 22 opcodes
969  }
970 }
971 
972 
973 /**
974  * @brief Read PHY register
975  * @param[in] opcode Access type (2 bits)
976  * @param[in] phyAddr PHY address (5 bits)
977  * @param[in] regAddr Register address (5 bits)
978  * @return Register value
979  **/
980 
981 uint16_t mimxrt1020EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
982  uint8_t regAddr)
983 {
984  uint16_t data;
985  uint32_t temp;
986 
987  //Valid opcode?
988  if(opcode == SMI_OPCODE_READ)
989  {
990  //Set up a read operation
991  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
992  //PHY address
993  temp |= ENET_MMFR_PA(phyAddr);
994  //Register address
995  temp |= ENET_MMFR_RA(regAddr);
996 
997  //Clear MII interrupt flag
998  ENET->EIR = ENET_EIR_MII_MASK;
999  //Start a read operation
1000  ENET->MMFR = temp;
1001 
1002  //Wait for the read to complete
1003  while(!(ENET->EIR & ENET_EIR_MII_MASK))
1004  {
1005  }
1006 
1007  //Get register value
1008  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
1009  }
1010  else
1011  {
1012  //The MAC peripheral only supports standard Clause 22 opcodes
1013  data = 0;
1014  }
1015 
1016  //Return the value of the PHY register
1017  return data;
1018 }
1019 
1020 
1021 /**
1022  * @brief CRC calculation
1023  * @param[in] data Pointer to the data over which to calculate the CRC
1024  * @param[in] length Number of bytes to process
1025  * @return Resulting CRC value
1026  **/
1027 
1028 uint32_t mimxrt1020EthCalcCrc(const void *data, size_t length)
1029 {
1030  uint_t i;
1031  uint_t j;
1032 
1033  //Point to the data over which to calculate the CRC
1034  const uint8_t *p = (uint8_t *) data;
1035  //CRC preset value
1036  uint32_t crc = 0xFFFFFFFF;
1037 
1038  //Loop through data
1039  for(i = 0; i < length; i++)
1040  {
1041  //Update CRC value
1042  crc ^= p[i];
1043  //The message is processed bit by bit
1044  for(j = 0; j < 8; j++)
1045  {
1046  if(crc & 0x00000001)
1047  crc = (crc >> 1) ^ 0xEDB88320;
1048  else
1049  crc = crc >> 1;
1050  }
1051  }
1052 
1053  //Return CRC value
1054  return crc;
1055 }
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ENET_RBD0_L
#define ENET_RBD0_W
error_t mimxrt1020EthInit(NetInterface *interface)
i.MX RT1020 Ethernet MAC initialization
uint16_t mimxrt1020EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define ENET_RBD0_OV
TCP/IP stack core.
void mimxrt1020EthInitGpio(NetInterface *interface)
Debugging facilities.
error_t mimxrt1020EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t p
Definition: ndp.h:298
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define ENET_TBD2_INT
#define txBuffer
const NicDriver mimxrt1020EthDriver
i.MX RT1020 Ethernet MAC driver
i.MX RT1020 Ethernet MAC controller
#define sleep(delay)
Definition: os_port.h:128
#define SMI_OPCODE_READ
Definition: nic.h:63
#define MIMXRT1020_ETH_RX_BUFFER_COUNT
void mimxrt1020EthTick(NetInterface *interface)
i.MX RT1020 Ethernet MAC timer handler
#define ENET_RBD0_LG
__start_packed struct @108 MacAddr
MAC address.
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define ENET_RBD0_E
#define ENET_TBD0_R
#define ENET_RBD0_NO
uint8_t opcode
Definition: dns_common.h:172
#define ENET_TBD0_DATA_LENGTH
#define MIMXRT1020_ETH_IRQ_GROUP_PRIORITY
uint32_t mimxrt1020EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_CR
void mimxrt1020EthEventHandler(NetInterface *interface)
i.MX RT1020 Ethernet MAC event handler
#define MIMXRT1020_ETH_IRQ_SUB_PRIORITY
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
error_t mimxrt1020EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
NIC driver.
Definition: nic.h:179
void mimxrt1020EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t mimxrt1020EthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void mimxrt1020EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void mimxrt1020EthEnableIrq(NetInterface *interface)
Enable interrupts.
void mimxrt1020EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:79
#define MIMXRT1020_ETH_TX_BUFFER_SIZE
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:74
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
error_t mimxrt1020EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
unsigned int uint_t
Definition: compiler_port.h:45
uint8_t data[]
Definition: dtls_misc.h:169
#define MIMXRT1020_ETH_TX_BUFFER_COUNT
#define NetInterface
Definition: net.h:36
#define MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING
uint8_t value[]
Definition: dtls_misc.h:143
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define osExitIsr(flag)
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
#define osEnterIsr()
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define MIMXRT1020_ETH_RX_BUFFER_SIZE