mimxrt1060_eth1_driver.c
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1 /**
2  * @file mimxrt1060_eth1_driver.c
3  * @brief NXP i.MX RT1060 Ethernet MAC driver (ENET instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 64
50 #pragma location = MIMXRT1060_ETH1_RAM_SECTION
52 //RX buffer
53 #pragma data_alignment = 64
54 #pragma location = MIMXRT1060_ETH1_RAM_SECTION
56 //TX buffer descriptors
57 #pragma data_alignment = 64
58 #pragma location = MIMXRT1060_ETH1_RAM_SECTION
59 static uint32_t txBufferDesc[MIMXRT1060_ETH1_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 64
62 #pragma location = MIMXRT1060_ETH1_RAM_SECTION
63 static uint32_t rxBufferDesc[MIMXRT1060_ETH1_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(64), __section__(MIMXRT1060_ETH1_RAM_SECTION)));
71 //RX buffer
73  __attribute__((aligned(64), __section__(MIMXRT1060_ETH1_RAM_SECTION)));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1060_ETH1_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(64), __section__(MIMXRT1060_ETH1_RAM_SECTION)));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1060_ETH1_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(64), __section__(MIMXRT1060_ETH1_RAM_SECTION)));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1060 Ethernet MAC driver (ENET instance)
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1060 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1060 Ethernet MAC (ENET)...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1060Eth1InitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
141  {
142  }
143 
144  //Receive control register
145  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1060_ETH1_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET->TCR = 0;
150  //Configure MDC clock frequency
151  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //Valid Ethernet PHY or switch driver?
154  if(interface->phyDriver != NULL)
155  {
156  //Ethernet PHY initialization
157  error = interface->phyDriver->init(interface);
158  }
159  else if(interface->switchDriver != NULL)
160  {
161  //Ethernet switch initialization
162  error = interface->switchDriver->init(interface);
163  }
164  else
165  {
166  //The interface is not properly configured
167  error = ERROR_FAILURE;
168  }
169 
170  //Any error to report?
171  if(error)
172  {
173  return error;
174  }
175 
176  //Set the MAC address of the station (upper 16 bits)
177  value = interface->macAddr.b[5];
178  value |= (interface->macAddr.b[4] << 8);
179  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
180 
181  //Set the MAC address of the station (lower 32 bits)
182  value = interface->macAddr.b[3];
183  value |= (interface->macAddr.b[2] << 8);
184  value |= (interface->macAddr.b[1] << 16);
185  value |= (interface->macAddr.b[0] << 24);
186  ENET->PALR = ENET_PALR_PADDR1(value);
187 
188  //Hash table for unicast address filtering
189  ENET->IALR = 0;
190  ENET->IAUR = 0;
191  //Hash table for multicast address filtering
192  ENET->GALR = 0;
193  ENET->GAUR = 0;
194 
195  //Disable transmit accelerator functions
196  ENET->TACC = 0;
197  //Disable receive accelerator functions
198  ENET->RACC = 0;
199 
200  //Use enhanced buffer descriptors
201  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
202 
203  //Reset statistics counters
204  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
205  ENET->MIBC = 0;
206 
207  //Initialize buffer descriptors
208  mimxrt1060Eth1InitBufferDesc(interface);
209 
210  //Clear any pending interrupts
211  ENET->EIR = 0xFFFFFFFF;
212  //Enable desired interrupts
213  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
214 
215  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
216  NVIC_SetPriorityGrouping(MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING);
217 
218  //Configure ENET interrupt priority
219  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING,
221 
222  //Enable Ethernet MAC
223  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
224  //Instruct the DMA to poll the receive descriptor list
225  ENET->RDAR = ENET_RDAR_RDAR_MASK;
226 
227  //Accept any packets from the upper layer
228  osSetEvent(&interface->nicTxEvent);
229 
230  //Successful initialization
231  return NO_ERROR;
232 }
233 
234 
235 /**
236  * @brief GPIO configuration
237  * @param[in] interface Underlying network interface
238  **/
239 
240 __weak_func void mimxrt1060Eth1InitGpio(NetInterface *interface)
241 {
242 //MIMXRT1060-EVK or MIMXRT1064-EVK evaluation board?
243 #if defined(USE_MIMXRT1060_EVK) || defined(USE_MIMXRT1064_EVK)
244  gpio_pin_config_t pinConfig;
245  clock_enet_pll_config_t pllConfig;
246 
247  //Configure ENET PLL (50MHz)
248  pllConfig.enableClkOutput = true;
249  pllConfig.enableClkOutput25M = false;
250  pllConfig.loopDivider = 1;
251  pllConfig.src = 0;
252  pllConfig.enableClkOutput1 = true;
253  pllConfig.loopDivider1 = 1;
254  CLOCK_InitEnetPll(&pllConfig);
255 
256  //Enable ENET1_TX_CLK output driver
257  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
258 
259  //Enable IOMUXC clock
260  CLOCK_EnableClock(kCLOCK_Iomuxc);
261 
262  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
263  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
264 
265  //Set GPIO_B1_04 pad properties
266  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
267  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
268  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
269  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
270  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
271  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
272  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
273  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
274  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
275 
276  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
277  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
278 
279  //Set GPIO_B1_05 pad properties
280  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
281  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
282  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
283  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
284  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
285  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
286  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
287  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
288  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
289 
290  //Configure GPIO_B1_06 pin as ENET_RX_EN
291  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
292 
293  //Set GPIO_B1_06 pad properties
294  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
295  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
296  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
297  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
298  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
299  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
300  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
301  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
302  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
303 
304  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
305  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
306 
307  //Set GPIO_B1_07 pad properties
308  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
309  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
310  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
311  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
312  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
313  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
314  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
315  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
316  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
317 
318  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
319  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
320 
321  //Set GPIO_B1_08 pad properties
322  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
323  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
324  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
325  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
326  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
327  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
328  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
329  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
330  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
331 
332  //Configure GPIO_B1_09 pin as ENET_TX_EN
333  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
334 
335  //Set GPIO_B1_09 pad properties
336  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
337  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
338  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
339  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
340  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
341  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
342  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
343  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
344  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
345 
346  //Configure GPIO_B1_10 pin as ENET_REF_CLK
347  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
348 
349  //Set GPIO_B1_10 pad properties
350  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
351  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
352  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
353  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
354  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
355  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
356  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
357  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
358  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
359 
360  //Configure GPIO_B1_11 pin as ENET_RX_ER
361  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
362 
363  //Set GPIO_B1_11 pad properties
364  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
365  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
366  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
367  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
368  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
369  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
370  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
371  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
372  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
373 
374  //Configure GPIO_EMC_40 pin as ENET_MDC
375  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
376 
377  //Set GPIO_EMC_40 pad properties
378  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
379  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
380  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
381  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
382  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
383  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
384  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
385  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
386  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
387 
388  //Configure GPIO_EMC_41 pin as ENET_MDIO
389  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
390 
391  //Set GPIO_EMC_41 pad properties
392  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
393  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
394  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
395  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
396  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
397  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
398  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
399  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
400  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
401 
402  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
403  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
404 
405  //Set GPIO_AD_B0_09 pad properties
406  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
407  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
408  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
409  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
410  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
411  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
412  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
413  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
414  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
415 
416  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
417  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
418 
419  //Set GPIO_AD_B0_10 pad properties
420  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
421  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
422  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
423  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
424  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
425  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
426  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
427  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
428  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
429 
430  //Configure ENET_RST as an output
431  pinConfig.direction = kGPIO_DigitalOutput;
432  pinConfig.outputLogic = 0;
433  pinConfig.interruptMode = kGPIO_NoIntmode;
434  GPIO_PinInit(GPIO1, 9, &pinConfig);
435 
436  //Configure ENET_INT as an input
437  pinConfig.direction = kGPIO_DigitalInput;
438  pinConfig.outputLogic = 0;
439  pinConfig.interruptMode = kGPIO_NoIntmode;
440  GPIO_PinInit(GPIO1, 10, &pinConfig);
441 
442  //Reset PHY transceiver (hard reset)
443  GPIO_PinWrite(GPIO1, 9, 0);
444  sleep(10);
445  GPIO_PinWrite(GPIO1, 9, 1);
446  sleep(10);
447 #endif
448 }
449 
450 
451 /**
452  * @brief Initialize buffer descriptors
453  * @param[in] interface Underlying network interface
454  **/
455 
457 {
458  uint_t i;
459  uint32_t address;
460 
461  //Clear TX and RX buffer descriptors
462  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
463  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
464 
465  //Initialize TX buffer descriptors
466  for(i = 0; i < MIMXRT1060_ETH1_TX_BUFFER_COUNT; i++)
467  {
468  //Calculate the address of the current TX buffer
469  address = (uint32_t) txBuffer[i];
470  //Transmit buffer address
471  txBufferDesc[i][1] = address;
472  //Generate interrupts
473  txBufferDesc[i][2] = ENET_TBD2_INT;
474  }
475 
476  //Mark the last descriptor entry with the wrap flag
477  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
478  //Initialize TX buffer index
479  txBufferIndex = 0;
480 
481  //Initialize RX buffer descriptors
482  for(i = 0; i < MIMXRT1060_ETH1_RX_BUFFER_COUNT; i++)
483  {
484  //Calculate the address of the current RX buffer
485  address = (uint32_t) rxBuffer[i];
486  //The descriptor is initially owned by the DMA
487  rxBufferDesc[i][0] = ENET_RBD0_E;
488  //Receive buffer address
489  rxBufferDesc[i][1] = address;
490  //Generate interrupts
491  rxBufferDesc[i][2] = ENET_RBD2_INT;
492  }
493 
494  //Mark the last descriptor entry with the wrap flag
495  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
496  //Initialize RX buffer index
497  rxBufferIndex = 0;
498 
499  //Start location of the TX descriptor list
500  ENET->TDSR = (uint32_t) txBufferDesc;
501  //Start location of the RX descriptor list
502  ENET->RDSR = (uint32_t) rxBufferDesc;
503  //Maximum receive buffer size
504  ENET->MRBR = MIMXRT1060_ETH1_RX_BUFFER_SIZE;
505 }
506 
507 
508 /**
509  * @brief i.MX RT1060 Ethernet MAC timer handler
510  *
511  * This routine is periodically called by the TCP/IP stack to handle periodic
512  * operations such as polling the link state
513  *
514  * @param[in] interface Underlying network interface
515  **/
516 
518 {
519  //Valid Ethernet PHY or switch driver?
520  if(interface->phyDriver != NULL)
521  {
522  //Handle periodic operations
523  interface->phyDriver->tick(interface);
524  }
525  else if(interface->switchDriver != NULL)
526  {
527  //Handle periodic operations
528  interface->switchDriver->tick(interface);
529  }
530  else
531  {
532  //Just for sanity
533  }
534 }
535 
536 
537 /**
538  * @brief Enable interrupts
539  * @param[in] interface Underlying network interface
540  **/
541 
543 {
544  //Enable Ethernet MAC interrupts
545  NVIC_EnableIRQ(ENET_IRQn);
546 
547  //Valid Ethernet PHY or switch driver?
548  if(interface->phyDriver != NULL)
549  {
550  //Enable Ethernet PHY interrupts
551  interface->phyDriver->enableIrq(interface);
552  }
553  else if(interface->switchDriver != NULL)
554  {
555  //Enable Ethernet switch interrupts
556  interface->switchDriver->enableIrq(interface);
557  }
558  else
559  {
560  //Just for sanity
561  }
562 }
563 
564 
565 /**
566  * @brief Disable interrupts
567  * @param[in] interface Underlying network interface
568  **/
569 
571 {
572  //Disable Ethernet MAC interrupts
573  NVIC_DisableIRQ(ENET_IRQn);
574 
575  //Valid Ethernet PHY or switch driver?
576  if(interface->phyDriver != NULL)
577  {
578  //Disable Ethernet PHY interrupts
579  interface->phyDriver->disableIrq(interface);
580  }
581  else if(interface->switchDriver != NULL)
582  {
583  //Disable Ethernet switch interrupts
584  interface->switchDriver->disableIrq(interface);
585  }
586  else
587  {
588  //Just for sanity
589  }
590 }
591 
592 
593 /**
594  * @brief Ethernet MAC interrupt
595  **/
596 
597 void ENET_IRQHandler(void)
598 {
599  bool_t flag;
600  uint32_t events;
601 
602  //Interrupt service routine prologue
603  osEnterIsr();
604 
605  //This flag will be set if a higher priority task must be woken
606  flag = FALSE;
607  //Read interrupt event register
608  events = ENET->EIR;
609 
610  //Packet transmitted?
611  if((events & ENET_EIR_TXF_MASK) != 0)
612  {
613  //Clear TXF interrupt flag
614  ENET->EIR = ENET_EIR_TXF_MASK;
615 
616  //Check whether the TX buffer is available for writing
617  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
618  {
619  //Notify the TCP/IP stack that the transmitter is ready to send
620  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
621  }
622 
623  //Instruct the DMA to poll the transmit descriptor list
624  ENET->TDAR = ENET_TDAR_TDAR_MASK;
625  }
626 
627  //Packet received?
628  if((events & ENET_EIR_RXF_MASK) != 0)
629  {
630  //Disable RXF interrupt
631  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
632 
633  //Set event flag
634  nicDriverInterface->nicEvent = TRUE;
635  //Notify the TCP/IP stack of the event
636  flag = osSetEventFromIsr(&netEvent);
637  }
638 
639  //System bus error?
640  if((events & ENET_EIR_EBERR_MASK) != 0)
641  {
642  //Disable EBERR interrupt
643  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
644 
645  //Set event flag
646  nicDriverInterface->nicEvent = TRUE;
647  //Notify the TCP/IP stack of the event
648  flag |= osSetEventFromIsr(&netEvent);
649  }
650 
651  //Interrupt service routine epilogue
652  osExitIsr(flag);
653 }
654 
655 
656 /**
657  * @brief i.MX RT1060 Ethernet MAC event handler
658  * @param[in] interface Underlying network interface
659  **/
660 
662 {
663  error_t error;
664  uint32_t status;
665 
666  //Read interrupt event register
667  status = ENET->EIR;
668 
669  //Packet received?
670  if((status & ENET_EIR_RXF_MASK) != 0)
671  {
672  //Clear RXF interrupt flag
673  ENET->EIR = ENET_EIR_RXF_MASK;
674 
675  //Process all pending packets
676  do
677  {
678  //Read incoming packet
679  error = mimxrt1060Eth1ReceivePacket(interface);
680 
681  //No more data in the receive buffer?
682  } while(error != ERROR_BUFFER_EMPTY);
683  }
684 
685  //System bus error?
686  if((status & ENET_EIR_EBERR_MASK) != 0)
687  {
688  //Clear EBERR interrupt flag
689  ENET->EIR = ENET_EIR_EBERR_MASK;
690 
691  //Disable Ethernet MAC
692  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
693  //Reset buffer descriptors
694  mimxrt1060Eth1InitBufferDesc(interface);
695  //Resume normal operation
696  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
697  //Instruct the DMA to poll the receive descriptor list
698  ENET->RDAR = ENET_RDAR_RDAR_MASK;
699  }
700 
701  //Re-enable Ethernet MAC interrupts
702  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
703 }
704 
705 
706 /**
707  * @brief Send a packet
708  * @param[in] interface Underlying network interface
709  * @param[in] buffer Multi-part buffer containing the data to send
710  * @param[in] offset Offset to the first data byte
711  * @param[in] ancillary Additional options passed to the stack along with
712  * the packet
713  * @return Error code
714  **/
715 
717  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
718 {
719  static uint32_t temp[MIMXRT1060_ETH1_TX_BUFFER_SIZE / 4];
720  size_t length;
721 
722  //Retrieve the length of the packet
723  length = netBufferGetLength(buffer) - offset;
724 
725  //Check the frame length
727  {
728  //The transmitter can accept another packet
729  osSetEvent(&interface->nicTxEvent);
730  //Report an error
731  return ERROR_INVALID_LENGTH;
732  }
733 
734  //Make sure the current buffer is available for writing
735  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
736  {
737  return ERROR_FAILURE;
738  }
739 
740  //Copy user data to the transmit buffer
741  netBufferRead(temp, buffer, offset, length);
742  osMemcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
743 
744  //Clear BDU flag
745  txBufferDesc[txBufferIndex][4] = 0;
746 
747  //Check current index
748  if(txBufferIndex < (MIMXRT1060_ETH1_TX_BUFFER_COUNT - 1))
749  {
750  //Give the ownership of the descriptor to the DMA engine
751  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
753 
754  //Point to the next buffer
755  txBufferIndex++;
756  }
757  else
758  {
759  //Give the ownership of the descriptor to the DMA engine
760  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
762 
763  //Wrap around
764  txBufferIndex = 0;
765  }
766 
767  //Data synchronization barrier
768  __DSB();
769 
770  //Instruct the DMA to poll the transmit descriptor list
771  ENET->TDAR = ENET_TDAR_TDAR_MASK;
772 
773  //Check whether the next buffer is available for writing
774  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
775  {
776  //The transmitter can accept another packet
777  osSetEvent(&interface->nicTxEvent);
778  }
779 
780  //Successful processing
781  return NO_ERROR;
782 }
783 
784 
785 /**
786  * @brief Receive a packet
787  * @param[in] interface Underlying network interface
788  * @return Error code
789  **/
790 
792 {
793  static uint32_t temp[MIMXRT1060_ETH1_RX_BUFFER_SIZE / 4];
794  error_t error;
795  size_t n;
796  NetRxAncillary ancillary;
797 
798  //Current buffer available for reading?
799  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
800  {
801  //The frame should not span multiple buffers
802  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
803  {
804  //Check whether an error occurred
805  if((rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG | ENET_RBD0_NO |
807  {
808  //Retrieve the length of the frame
809  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
810  //Limit the number of data to read
812 
813  //Copy data from the receive buffer
814  osMemcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
815 
816  //Additional options can be passed to the stack along with the packet
817  ancillary = NET_DEFAULT_RX_ANCILLARY;
818 
819  //Pass the packet to the upper layer
820  nicProcessPacket(interface, (uint8_t *) temp, n, &ancillary);
821 
822  //Valid packet received
823  error = NO_ERROR;
824  }
825  else
826  {
827  //The received packet contains an error
828  error = ERROR_INVALID_PACKET;
829  }
830  }
831  else
832  {
833  //The packet is not valid
834  error = ERROR_INVALID_PACKET;
835  }
836 
837  //Clear BDU flag
838  rxBufferDesc[rxBufferIndex][4] = 0;
839 
840  //Check current index
841  if(rxBufferIndex < (MIMXRT1060_ETH1_RX_BUFFER_COUNT - 1))
842  {
843  //Give the ownership of the descriptor back to the DMA engine
844  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
845  //Point to the next buffer
846  rxBufferIndex++;
847  }
848  else
849  {
850  //Give the ownership of the descriptor back to the DMA engine
851  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
852  //Wrap around
853  rxBufferIndex = 0;
854  }
855 
856  //Instruct the DMA to poll the receive descriptor list
857  ENET->RDAR = ENET_RDAR_RDAR_MASK;
858  }
859  else
860  {
861  //No more data in the receive buffer
862  error = ERROR_BUFFER_EMPTY;
863  }
864 
865  //Return status code
866  return error;
867 }
868 
869 
870 /**
871  * @brief Configure MAC address filtering
872  * @param[in] interface Underlying network interface
873  * @return Error code
874  **/
875 
877 {
878  uint_t i;
879  uint_t k;
880  uint32_t crc;
881  uint32_t value;
882  uint32_t unicastHashTable[2];
883  uint32_t multicastHashTable[2];
884  MacFilterEntry *entry;
885 
886  //Debug message
887  TRACE_DEBUG("Updating MAC filter...\r\n");
888 
889  //Set the MAC address of the station (upper 16 bits)
890  value = interface->macAddr.b[5];
891  value |= (interface->macAddr.b[4] << 8);
892  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
893 
894  //Set the MAC address of the station (lower 32 bits)
895  value = interface->macAddr.b[3];
896  value |= (interface->macAddr.b[2] << 8);
897  value |= (interface->macAddr.b[1] << 16);
898  value |= (interface->macAddr.b[0] << 24);
899  ENET->PALR = ENET_PALR_PADDR1(value);
900 
901  //Clear hash table (unicast address filtering)
902  unicastHashTable[0] = 0;
903  unicastHashTable[1] = 0;
904 
905  //Clear hash table (multicast address filtering)
906  multicastHashTable[0] = 0;
907  multicastHashTable[1] = 0;
908 
909  //The MAC address filter contains the list of MAC addresses to accept
910  //when receiving an Ethernet frame
911  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
912  {
913  //Point to the current entry
914  entry = &interface->macAddrFilter[i];
915 
916  //Valid entry?
917  if(entry->refCount > 0)
918  {
919  //Compute CRC over the current MAC address
920  crc = mimxrt1060Eth1CalcCrc(&entry->addr, sizeof(MacAddr));
921 
922  //The upper 6 bits in the CRC register are used to index the
923  //contents of the hash table
924  k = (crc >> 26) & 0x3F;
925 
926  //Multicast address?
927  if(macIsMulticastAddr(&entry->addr))
928  {
929  //Update the multicast hash table
930  multicastHashTable[k / 32] |= (1 << (k % 32));
931  }
932  else
933  {
934  //Update the unicast hash table
935  unicastHashTable[k / 32] |= (1 << (k % 32));
936  }
937  }
938  }
939 
940  //Write the hash table (unicast address filtering)
941  ENET->IALR = unicastHashTable[0];
942  ENET->IAUR = unicastHashTable[1];
943 
944  //Write the hash table (multicast address filtering)
945  ENET->GALR = multicastHashTable[0];
946  ENET->GAUR = multicastHashTable[1];
947 
948  //Debug message
949  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
950  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
951  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
952  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
953 
954  //Successful processing
955  return NO_ERROR;
956 }
957 
958 
959 /**
960  * @brief Adjust MAC configuration parameters for proper operation
961  * @param[in] interface Underlying network interface
962  * @return Error code
963  **/
964 
966 {
967  //Disable Ethernet MAC while modifying configuration registers
968  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
969 
970  //10BASE-T or 100BASE-TX operation mode?
971  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
972  {
973  //100 Mbps operation
974  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
975  }
976  else
977  {
978  //10 Mbps operation
979  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
980  }
981 
982  //Half-duplex or full-duplex mode?
983  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
984  {
985  //Full-duplex mode
986  ENET->TCR |= ENET_TCR_FDEN_MASK;
987  //Receive path operates independently of transmit
988  ENET->RCR &= ~ENET_RCR_DRT_MASK;
989  }
990  else
991  {
992  //Half-duplex mode
993  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
994  //Disable reception of frames while transmitting
995  ENET->RCR |= ENET_RCR_DRT_MASK;
996  }
997 
998  //Reset buffer descriptors
999  mimxrt1060Eth1InitBufferDesc(interface);
1000 
1001  //Re-enable Ethernet MAC
1002  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
1003  //Instruct the DMA to poll the receive descriptor list
1004  ENET->RDAR = ENET_RDAR_RDAR_MASK;
1005 
1006  //Successful processing
1007  return NO_ERROR;
1008 }
1009 
1010 
1011 /**
1012  * @brief Write PHY register
1013  * @param[in] opcode Access type (2 bits)
1014  * @param[in] phyAddr PHY address (5 bits)
1015  * @param[in] regAddr Register address (5 bits)
1016  * @param[in] data Register value
1017  **/
1018 
1019 void mimxrt1060Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
1020  uint8_t regAddr, uint16_t data)
1021 {
1022  uint32_t temp;
1023 
1024  //Valid opcode?
1025  if(opcode == SMI_OPCODE_WRITE)
1026  {
1027  //Set up a write operation
1028  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
1029  //PHY address
1030  temp |= ENET_MMFR_PA(phyAddr);
1031  //Register address
1032  temp |= ENET_MMFR_RA(regAddr);
1033  //Register value
1034  temp |= ENET_MMFR_DATA(data);
1035 
1036  //Clear MII interrupt flag
1037  ENET->EIR = ENET_EIR_MII_MASK;
1038  //Start a write operation
1039  ENET->MMFR = temp;
1040 
1041  //Wait for the write to complete
1042  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
1043  {
1044  }
1045  }
1046  else
1047  {
1048  //The MAC peripheral only supports standard Clause 22 opcodes
1049  }
1050 }
1051 
1052 
1053 /**
1054  * @brief Read PHY register
1055  * @param[in] opcode Access type (2 bits)
1056  * @param[in] phyAddr PHY address (5 bits)
1057  * @param[in] regAddr Register address (5 bits)
1058  * @return Register value
1059  **/
1060 
1061 uint16_t mimxrt1060Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
1062  uint8_t regAddr)
1063 {
1064  uint16_t data;
1065  uint32_t temp;
1066 
1067  //Valid opcode?
1068  if(opcode == SMI_OPCODE_READ)
1069  {
1070  //Set up a read operation
1071  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
1072  //PHY address
1073  temp |= ENET_MMFR_PA(phyAddr);
1074  //Register address
1075  temp |= ENET_MMFR_RA(regAddr);
1076 
1077  //Clear MII interrupt flag
1078  ENET->EIR = ENET_EIR_MII_MASK;
1079  //Start a read operation
1080  ENET->MMFR = temp;
1081 
1082  //Wait for the read to complete
1083  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
1084  {
1085  }
1086 
1087  //Get register value
1088  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
1089  }
1090  else
1091  {
1092  //The MAC peripheral only supports standard Clause 22 opcodes
1093  data = 0;
1094  }
1095 
1096  //Return the value of the PHY register
1097  return data;
1098 }
1099 
1100 
1101 /**
1102  * @brief CRC calculation
1103  * @param[in] data Pointer to the data over which to calculate the CRC
1104  * @param[in] length Number of bytes to process
1105  * @return Resulting CRC value
1106  **/
1107 
1108 uint32_t mimxrt1060Eth1CalcCrc(const void *data, size_t length)
1109 {
1110  uint_t i;
1111  uint_t j;
1112  uint32_t crc;
1113  const uint8_t *p;
1114 
1115  //Point to the data over which to calculate the CRC
1116  p = (uint8_t *) data;
1117  //CRC preset value
1118  crc = 0xFFFFFFFF;
1119 
1120  //Loop through data
1121  for(i = 0; i < length; i++)
1122  {
1123  //Update CRC value
1124  crc ^= p[i];
1125 
1126  //The message is processed bit by bit
1127  for(j = 0; j < 8; j++)
1128  {
1129  if((crc & 0x01) != 0)
1130  {
1131  crc = (crc >> 1) ^ 0xEDB88320;
1132  }
1133  else
1134  {
1135  crc = crc >> 1;
1136  }
1137  }
1138  }
1139 
1140  //Return CRC value
1141  return crc;
1142 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
#define ENET_RBD0_E
#define ENET_RBD0_DATA_LENGTH
#define ENET_TBD2_INT
#define ENET_TBD0_W
#define ENET_TBD0_R
#define ENET_RBD0_L
#define ENET_RBD0_NO
#define ENET_RBD0_W
#define ENET_RBD0_LG
#define ENET_TBD0_DATA_LENGTH
#define ENET_RBD2_INT
#define ENET_RBD0_OV
#define ENET_TBD0_TC
#define ENET_RBD0_CR
#define ENET_TBD0_L
#define ENET_RBD0_TR
error_t mimxrt1060Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mimxrt1060Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
void mimxrt1060Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t mimxrt1060Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void mimxrt1060Eth1Tick(NetInterface *interface)
i.MX RT1060 Ethernet MAC timer handler
void mimxrt1060Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
void mimxrt1060Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
__weak_func void mimxrt1060Eth1InitGpio(NetInterface *interface)
GPIO configuration.
void mimxrt1060Eth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint32_t mimxrt1060Eth1CalcCrc(const void *data, size_t length)
CRC calculation.
void mimxrt1060Eth1EventHandler(NetInterface *interface)
i.MX RT1060 Ethernet MAC event handler
uint16_t mimxrt1060Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t mimxrt1060Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t mimxrt1060Eth1Init(NetInterface *interface)
i.MX RT1060 Ethernet MAC initialization
const NicDriver mimxrt1060Eth1Driver
i.MX RT1060 Ethernet MAC driver (ENET instance)
NXP i.MX RT1060 Ethernet MAC driver (ENET instance)
#define MIMXRT1060_ETH1_IRQ_GROUP_PRIORITY
#define MIMXRT1060_ETH1_TX_BUFFER_COUNT
#define MIMXRT1060_ETH1_RX_BUFFER_COUNT
#define MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING
#define MIMXRT1060_ETH1_IRQ_SUB_PRIORITY
#define MIMXRT1060_ETH1_RAM_SECTION
#define MIMXRT1060_ETH1_TX_BUFFER_SIZE
#define MIMXRT1060_ETH1_RX_BUFFER_SIZE
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemset(p, value, length)
Definition: os_port.h:135
#define osMemcpy(dest, src, length)
Definition: os_port.h:141
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define sleep(delay)
Definition: os_port.h:301
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368
uint8_t value[]
Definition: tcp.h:369