mk7x_eth_driver.c
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1 /**
2  * @file mk7x_eth_driver.c
3  * @brief NXP Kinetis K70 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //MK70F12 device?
35 #if defined(MK70F12)
36  #include "mk70f12.h"
37 //MK70F15 device?
38 #elif defined(MK70F15)
39  #include "mk70f15.h"
40 #endif
41 
42 //Dependencies
43 #include "core/net.h"
45 #include "debug.h"
46 
47 //Underlying network interface
48 static NetInterface *nicDriverInterface;
49 
50 //IAR EWARM compiler?
51 #if defined(__ICCARM__)
52 
53 //TX buffer
54 #pragma data_alignment = 16
56 //RX buffer
57 #pragma data_alignment = 16
59 //TX buffer descriptors
60 #pragma data_alignment = 16
61 static uint32_t txBufferDesc[MK7X_ETH_TX_BUFFER_COUNT][8];
62 //RX buffer descriptors
63 #pragma data_alignment = 16
64 static uint32_t rxBufferDesc[MK7X_ETH_RX_BUFFER_COUNT][8];
65 
66 //ARM or GCC compiler?
67 #else
68 
69 //TX buffer
71  __attribute__((aligned(16)));
72 //RX buffer
74  __attribute__((aligned(16)));
75 //TX buffer descriptors
76 static uint32_t txBufferDesc[MK7X_ETH_TX_BUFFER_COUNT][8]
77  __attribute__((aligned(16)));
78 //RX buffer descriptors
79 static uint32_t rxBufferDesc[MK7X_ETH_RX_BUFFER_COUNT][8]
80  __attribute__((aligned(16)));
81 
82 #endif
83 
84 //TX buffer index
85 static uint_t txBufferIndex;
86 //RX buffer index
87 static uint_t rxBufferIndex;
88 
89 
90 /**
91  * @brief Kinetis K7x Ethernet MAC driver
92  **/
93 
95 {
97  ETH_MTU,
108  TRUE,
109  TRUE,
110  TRUE,
111  FALSE
112 };
113 
114 
115 /**
116  * @brief Kinetis K7x Ethernet MAC initialization
117  * @param[in] interface Underlying network interface
118  * @return Error code
119  **/
120 
122 {
123  error_t error;
124  uint32_t value;
125 
126  //Debug message
127  TRACE_INFO("Initializing Kinetis K7x Ethernet MAC...\r\n");
128 
129  //Save underlying network interface
130  nicDriverInterface = interface;
131 
132  //Disable MPU
133  MPU->CESR &= ~MPU_CESR_VLD_MASK;
134 
135  //Enable external reference clock
136  OSC0->CR |= OSC_CR_ERCLKEN_MASK;
137  //Enable ENET peripheral clock
138  SIM->SCGC2 |= SIM_SCGC2_ENET_MASK;
139 
140  //GPIO configuration
141  mk7xEthInitGpio(interface);
142 
143  //Reset ENET module
144  ENET->ECR = ENET_ECR_RESET_MASK;
145  //Wait for the reset to complete
146  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
147  {
148  }
149 
150  //Receive control register
151  ENET->RCR = ENET_RCR_MAX_FL(MK7X_ETH_RX_BUFFER_SIZE) |
152  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
153 
154  //Transmit control register
155  ENET->TCR = 0;
156  //Configure MDC clock frequency
157  ENET->MSCR = ENET_MSCR_MII_SPEED(59);
158 
159  //Valid Ethernet PHY or switch driver?
160  if(interface->phyDriver != NULL)
161  {
162  //Ethernet PHY initialization
163  error = interface->phyDriver->init(interface);
164  }
165  else if(interface->switchDriver != NULL)
166  {
167  //Ethernet switch initialization
168  error = interface->switchDriver->init(interface);
169  }
170  else
171  {
172  //The interface is not properly configured
173  error = ERROR_FAILURE;
174  }
175 
176  //Any error to report?
177  if(error)
178  {
179  return error;
180  }
181 
182  //Set the MAC address of the station (upper 16 bits)
183  value = interface->macAddr.b[5];
184  value |= (interface->macAddr.b[4] << 8);
185  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
186 
187  //Set the MAC address of the station (lower 32 bits)
188  value = interface->macAddr.b[3];
189  value |= (interface->macAddr.b[2] << 8);
190  value |= (interface->macAddr.b[1] << 16);
191  value |= (interface->macAddr.b[0] << 24);
192  ENET->PALR = ENET_PALR_PADDR1(value);
193 
194  //Hash table for unicast address filtering
195  ENET->IALR = 0;
196  ENET->IAUR = 0;
197  //Hash table for multicast address filtering
198  ENET->GALR = 0;
199  ENET->GAUR = 0;
200 
201  //Disable transmit accelerator functions
202  ENET->TACC = 0;
203  //Disable receive accelerator functions
204  ENET->RACC = 0;
205 
206  //Use enhanced buffer descriptors
207  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
208 
209  //Reset statistics counters
210  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
211  ENET->MIBC = 0;
212 
213  //Initialize buffer descriptors
214  mk7xEthInitBufferDesc(interface);
215 
216  //Clear any pending interrupts
217  ENET->EIR = 0xFFFFFFFF;
218  //Enable desired interrupts
219  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
220 
221  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
222  NVIC_SetPriorityGrouping(MK7X_ETH_IRQ_PRIORITY_GROUPING);
223 
224  //Configure ENET transmit interrupt priority
225  NVIC_SetPriority(ENET_Transmit_IRQn, NVIC_EncodePriority(MK7X_ETH_IRQ_PRIORITY_GROUPING,
227 
228  //Configure ENET receive interrupt priority
229  NVIC_SetPriority(ENET_Receive_IRQn, NVIC_EncodePriority(MK7X_ETH_IRQ_PRIORITY_GROUPING,
231 
232  //Configure ENET error interrupt priority
233  NVIC_SetPriority(ENET_Error_IRQn, NVIC_EncodePriority(MK7X_ETH_IRQ_PRIORITY_GROUPING,
235 
236  //Enable Ethernet MAC
237  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
238  //Instruct the DMA to poll the receive descriptor list
239  ENET->RDAR = ENET_RDAR_RDAR_MASK;
240 
241  //Accept any packets from the upper layer
242  osSetEvent(&interface->nicTxEvent);
243 
244  //Successful initialization
245  return NO_ERROR;
246 }
247 
248 
249 //TWR-K70F120M evaluation board?
250 #if defined(USE_TWR_K70F120M)
251 
252 /**
253  * @brief GPIO configuration
254  * @param[in] interface Underlying network interface
255  **/
256 
257 void mk7xEthInitGpio(NetInterface *interface)
258 {
259  //Enable PORTA and PORTB peripheral clocks
260  SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK;
261 
262  //Configure RMII0_RXER (PTA5)
263  PORTA->PCR[5] = PORT_PCR_MUX(4) | PORT_PCR_PE_MASK;
264  //Configure RMII0_RXD1 (PTA12)
265  PORTA->PCR[12] = PORT_PCR_MUX(4);
266  //Configure RMII0_RXD0 (PTA13)
267  PORTA->PCR[13] = PORT_PCR_MUX(4);
268  //Configure RMII0_CRS_DV (PTA14)
269  PORTA->PCR[14] = PORT_PCR_MUX(4);
270  //Configure RMII0_TXEN (PTA15)
271  PORTA->PCR[15] = PORT_PCR_MUX(4);
272  //Configure RMII0_TXD0 (PTA16)
273  PORTA->PCR[16] = PORT_PCR_MUX(4);
274  //Configure RMII0_TXD1 (PTA17)
275  PORTA->PCR[17] = PORT_PCR_MUX(4);
276 
277  //Configure RMII0_MDIO (PTB0)
278  PORTB->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
279  //Configure RMII0_MDC (PTB1)
280  PORTB->PCR[1] = PORT_PCR_MUX(4);
281 }
282 
283 #endif
284 
285 
286 /**
287  * @brief Initialize buffer descriptors
288  * @param[in] interface Underlying network interface
289  **/
290 
292 {
293  uint_t i;
294  uint32_t address;
295 
296  //Clear TX and RX buffer descriptors
297  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
298  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
299 
300  //Initialize TX buffer descriptors
301  for(i = 0; i < MK7X_ETH_TX_BUFFER_COUNT; i++)
302  {
303  //Calculate the address of the current TX buffer
304  address = (uint32_t) txBuffer[i];
305  //Transmit buffer address
306  txBufferDesc[i][1] = address;
307  //Generate interrupts
308  txBufferDesc[i][2] = ENET_TBD2_INT;
309  }
310 
311  //Mark the last descriptor entry with the wrap flag
312  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
313  //Initialize TX buffer index
314  txBufferIndex = 0;
315 
316  //Initialize RX buffer descriptors
317  for(i = 0; i < MK7X_ETH_RX_BUFFER_COUNT; i++)
318  {
319  //Calculate the address of the current RX buffer
320  address = (uint32_t) rxBuffer[i];
321  //The descriptor is initially owned by the DMA
322  rxBufferDesc[i][0] = ENET_RBD0_E;
323  //Receive buffer address
324  rxBufferDesc[i][1] = address;
325  //Generate interrupts
326  rxBufferDesc[i][2] = ENET_RBD2_INT;
327  }
328 
329  //Mark the last descriptor entry with the wrap flag
330  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
331  //Initialize RX buffer index
332  rxBufferIndex = 0;
333 
334  //Start location of the TX descriptor list
335  ENET->TDSR = (uint32_t) txBufferDesc;
336  //Start location of the RX descriptor list
337  ENET->RDSR = (uint32_t) rxBufferDesc;
338  //Maximum receive buffer size
339  ENET->MRBR = MK7X_ETH_RX_BUFFER_SIZE;
340 }
341 
342 
343 /**
344  * @brief Kinetis K7x Ethernet MAC timer handler
345  *
346  * This routine is periodically called by the TCP/IP stack to handle periodic
347  * operations such as polling the link state
348  *
349  * @param[in] interface Underlying network interface
350  **/
351 
352 void mk7xEthTick(NetInterface *interface)
353 {
354  //Valid Ethernet PHY or switch driver?
355  if(interface->phyDriver != NULL)
356  {
357  //Handle periodic operations
358  interface->phyDriver->tick(interface);
359  }
360  else if(interface->switchDriver != NULL)
361  {
362  //Handle periodic operations
363  interface->switchDriver->tick(interface);
364  }
365  else
366  {
367  //Just for sanity
368  }
369 }
370 
371 
372 /**
373  * @brief Enable interrupts
374  * @param[in] interface Underlying network interface
375  **/
376 
378 {
379  //Enable Ethernet MAC interrupts
380  NVIC_EnableIRQ(ENET_Transmit_IRQn);
381  NVIC_EnableIRQ(ENET_Receive_IRQn);
382  NVIC_EnableIRQ(ENET_Error_IRQn);
383 
384 
385  //Valid Ethernet PHY or switch driver?
386  if(interface->phyDriver != NULL)
387  {
388  //Enable Ethernet PHY interrupts
389  interface->phyDriver->enableIrq(interface);
390  }
391  else if(interface->switchDriver != NULL)
392  {
393  //Enable Ethernet switch interrupts
394  interface->switchDriver->enableIrq(interface);
395  }
396  else
397  {
398  //Just for sanity
399  }
400 }
401 
402 
403 /**
404  * @brief Disable interrupts
405  * @param[in] interface Underlying network interface
406  **/
407 
409 {
410  //Disable Ethernet MAC interrupts
411  NVIC_DisableIRQ(ENET_Transmit_IRQn);
412  NVIC_DisableIRQ(ENET_Receive_IRQn);
413  NVIC_DisableIRQ(ENET_Error_IRQn);
414 
415 
416  //Valid Ethernet PHY or switch driver?
417  if(interface->phyDriver != NULL)
418  {
419  //Disable Ethernet PHY interrupts
420  interface->phyDriver->disableIrq(interface);
421  }
422  else if(interface->switchDriver != NULL)
423  {
424  //Disable Ethernet switch interrupts
425  interface->switchDriver->disableIrq(interface);
426  }
427  else
428  {
429  //Just for sanity
430  }
431 }
432 
433 
434 /**
435  * @brief Ethernet MAC transmit interrupt
436  **/
437 
439 {
440  bool_t flag;
441 
442  //Interrupt service routine prologue
443  osEnterIsr();
444 
445  //This flag will be set if a higher priority task must be woken
446  flag = FALSE;
447 
448  //Packet transmitted?
449  if((ENET->EIR & ENET_EIR_TXF_MASK) != 0)
450  {
451  //Clear TXF interrupt flag
452  ENET->EIR = ENET_EIR_TXF_MASK;
453 
454  //Check whether the TX buffer is available for writing
455  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
456  {
457  //Notify the TCP/IP stack that the transmitter is ready to send
458  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
459  }
460 
461  //Instruct the DMA to poll the transmit descriptor list
462  ENET->TDAR = ENET_TDAR_TDAR_MASK;
463  }
464 
465  //Interrupt service routine epilogue
466  osExitIsr(flag);
467 }
468 
469 
470 /**
471  * @brief Ethernet MAC receive interrupt
472  **/
473 
475 {
476  bool_t flag;
477 
478  //Interrupt service routine prologue
479  osEnterIsr();
480 
481  //This flag will be set if a higher priority task must be woken
482  flag = FALSE;
483 
484  //Packet received?
485  if((ENET->EIR & ENET_EIR_RXF_MASK) != 0)
486  {
487  //Disable RXF interrupt
488  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
489 
490  //Set event flag
491  nicDriverInterface->nicEvent = TRUE;
492  //Notify the TCP/IP stack of the event
493  flag = osSetEventFromIsr(&netEvent);
494  }
495 
496  //Interrupt service routine epilogue
497  osExitIsr(flag);
498 }
499 
500 
501 /**
502  * @brief Ethernet MAC error interrupt
503  **/
504 
506 {
507  bool_t flag;
508 
509  //Interrupt service routine prologue
510  osEnterIsr();
511 
512  //This flag will be set if a higher priority task must be woken
513  flag = FALSE;
514 
515  //System bus error?
516  if((ENET->EIR & ENET_EIR_EBERR_MASK) != 0)
517  {
518  //Disable EBERR interrupt
519  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
520 
521  //Set event flag
522  nicDriverInterface->nicEvent = TRUE;
523  //Notify the TCP/IP stack of the event
524  flag |= osSetEventFromIsr(&netEvent);
525  }
526 
527  //Interrupt service routine epilogue
528  osExitIsr(flag);
529 }
530 
531 
532 /**
533  * @brief Kinetis K7x Ethernet MAC event handler
534  * @param[in] interface Underlying network interface
535  **/
536 
538 {
539  error_t error;
540  uint32_t status;
541 
542  //Read interrupt event register
543  status = ENET->EIR;
544 
545  //Packet received?
546  if((status & ENET_EIR_RXF_MASK) != 0)
547  {
548  //Clear RXF interrupt flag
549  ENET->EIR = ENET_EIR_RXF_MASK;
550 
551  //Process all pending packets
552  do
553  {
554  //Read incoming packet
555  error = mk7xEthReceivePacket(interface);
556 
557  //No more data in the receive buffer?
558  } while(error != ERROR_BUFFER_EMPTY);
559  }
560 
561  //System bus error?
562  if((status & ENET_EIR_EBERR_MASK) != 0)
563  {
564  //Clear EBERR interrupt flag
565  ENET->EIR = ENET_EIR_EBERR_MASK;
566 
567  //Disable Ethernet MAC
568  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
569  //Reset buffer descriptors
570  mk7xEthInitBufferDesc(interface);
571  //Resume normal operation
572  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
573  //Instruct the DMA to poll the receive descriptor list
574  ENET->RDAR = ENET_RDAR_RDAR_MASK;
575  }
576 
577  //Re-enable Ethernet MAC interrupts
578  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
579 }
580 
581 
582 /**
583  * @brief Send a packet
584  * @param[in] interface Underlying network interface
585  * @param[in] buffer Multi-part buffer containing the data to send
586  * @param[in] offset Offset to the first data byte
587  * @param[in] ancillary Additional options passed to the stack along with
588  * the packet
589  * @return Error code
590  **/
591 
593  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
594 {
595  size_t length;
596 
597  //Retrieve the length of the packet
598  length = netBufferGetLength(buffer) - offset;
599 
600  //Check the frame length
602  {
603  //The transmitter can accept another packet
604  osSetEvent(&interface->nicTxEvent);
605  //Report an error
606  return ERROR_INVALID_LENGTH;
607  }
608 
609  //Make sure the current buffer is available for writing
610  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
611  {
612  return ERROR_FAILURE;
613  }
614 
615  //Copy user data to the transmit buffer
616  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
617 
618  //Clear BDU flag
619  txBufferDesc[txBufferIndex][4] = 0;
620 
621  //Check current index
622  if(txBufferIndex < (MK7X_ETH_TX_BUFFER_COUNT - 1))
623  {
624  //Give the ownership of the descriptor to the DMA engine
625  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
627 
628  //Point to the next buffer
629  txBufferIndex++;
630  }
631  else
632  {
633  //Give the ownership of the descriptor to the DMA engine
634  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
636 
637  //Wrap around
638  txBufferIndex = 0;
639  }
640 
641  //Instruct the DMA to poll the transmit descriptor list
642  ENET->TDAR = ENET_TDAR_TDAR_MASK;
643 
644  //Check whether the next buffer is available for writing
645  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
646  {
647  //The transmitter can accept another packet
648  osSetEvent(&interface->nicTxEvent);
649  }
650 
651  //Successful processing
652  return NO_ERROR;
653 }
654 
655 
656 /**
657  * @brief Receive a packet
658  * @param[in] interface Underlying network interface
659  * @return Error code
660  **/
661 
663 {
664  error_t error;
665  size_t n;
666  NetRxAncillary ancillary;
667 
668  //Make sure the current buffer is available for reading
669  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
670  {
671  //The frame should not span multiple buffers
672  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
673  {
674  //Check whether an error occurred
675  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
677  {
678  //Retrieve the length of the frame
679  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
680  //Limit the number of data to read
682 
683  //Additional options can be passed to the stack along with the packet
684  ancillary = NET_DEFAULT_RX_ANCILLARY;
685 
686  //Pass the packet to the upper layer
687  nicProcessPacket(interface, rxBuffer[rxBufferIndex], n, &ancillary);
688 
689  //Valid packet received
690  error = NO_ERROR;
691  }
692  else
693  {
694  //The received packet contains an error
695  error = ERROR_INVALID_PACKET;
696  }
697  }
698  else
699  {
700  //The packet is not valid
701  error = ERROR_INVALID_PACKET;
702  }
703 
704  //Clear BDU flag
705  rxBufferDesc[rxBufferIndex][4] = 0;
706 
707  //Check current index
708  if(rxBufferIndex < (MK7X_ETH_RX_BUFFER_COUNT - 1))
709  {
710  //Give the ownership of the descriptor back to the DMA engine
711  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
712  //Point to the next buffer
713  rxBufferIndex++;
714  }
715  else
716  {
717  //Give the ownership of the descriptor back to the DMA engine
718  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
719  //Wrap around
720  rxBufferIndex = 0;
721  }
722 
723  //Instruct the DMA to poll the receive descriptor list
724  ENET->RDAR = ENET_RDAR_RDAR_MASK;
725  }
726  else
727  {
728  //No more data in the receive buffer
729  error = ERROR_BUFFER_EMPTY;
730  }
731 
732  //Return status code
733  return error;
734 }
735 
736 
737 /**
738  * @brief Configure MAC address filtering
739  * @param[in] interface Underlying network interface
740  * @return Error code
741  **/
742 
744 {
745  uint_t i;
746  uint_t k;
747  uint32_t crc;
748  uint32_t value;
749  uint32_t unicastHashTable[2];
750  uint32_t multicastHashTable[2];
751  MacFilterEntry *entry;
752 
753  //Debug message
754  TRACE_DEBUG("Updating MAC filter...\r\n");
755 
756  //Set the MAC address of the station (upper 16 bits)
757  value = interface->macAddr.b[5];
758  value |= (interface->macAddr.b[4] << 8);
759  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
760 
761  //Set the MAC address of the station (lower 32 bits)
762  value = interface->macAddr.b[3];
763  value |= (interface->macAddr.b[2] << 8);
764  value |= (interface->macAddr.b[1] << 16);
765  value |= (interface->macAddr.b[0] << 24);
766  ENET->PALR = ENET_PALR_PADDR1(value);
767 
768  //Clear hash table (unicast address filtering)
769  unicastHashTable[0] = 0;
770  unicastHashTable[1] = 0;
771 
772  //Clear hash table (multicast address filtering)
773  multicastHashTable[0] = 0;
774  multicastHashTable[1] = 0;
775 
776  //The MAC address filter contains the list of MAC addresses to accept
777  //when receiving an Ethernet frame
778  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
779  {
780  //Point to the current entry
781  entry = &interface->macAddrFilter[i];
782 
783  //Valid entry?
784  if(entry->refCount > 0)
785  {
786  //Compute CRC over the current MAC address
787  crc = mk7xEthCalcCrc(&entry->addr, sizeof(MacAddr));
788 
789  //The upper 6 bits in the CRC register are used to index the
790  //contents of the hash table
791  k = (crc >> 26) & 0x3F;
792 
793  //Multicast address?
794  if(macIsMulticastAddr(&entry->addr))
795  {
796  //Update the multicast hash table
797  multicastHashTable[k / 32] |= (1 << (k % 32));
798  }
799  else
800  {
801  //Update the unicast hash table
802  unicastHashTable[k / 32] |= (1 << (k % 32));
803  }
804  }
805  }
806 
807  //Write the hash table (unicast address filtering)
808  ENET->IALR = unicastHashTable[0];
809  ENET->IAUR = unicastHashTable[1];
810 
811  //Write the hash table (multicast address filtering)
812  ENET->GALR = multicastHashTable[0];
813  ENET->GAUR = multicastHashTable[1];
814 
815  //Debug message
816  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
817  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
818  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
819  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
820 
821  //Successful processing
822  return NO_ERROR;
823 }
824 
825 
826 /**
827  * @brief Adjust MAC configuration parameters for proper operation
828  * @param[in] interface Underlying network interface
829  * @return Error code
830  **/
831 
833 {
834  //Disable Ethernet MAC while modifying configuration registers
835  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
836 
837  //10BASE-T or 100BASE-TX operation mode?
838  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
839  {
840  //100 Mbps operation
841  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
842  }
843  else
844  {
845  //10 Mbps operation
846  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
847  }
848 
849  //Half-duplex or full-duplex mode?
850  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
851  {
852  //Full-duplex mode
853  ENET->TCR |= ENET_TCR_FDEN_MASK;
854  //Receive path operates independently of transmit
855  ENET->RCR &= ~ENET_RCR_DRT_MASK;
856  }
857  else
858  {
859  //Half-duplex mode
860  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
861  //Disable reception of frames while transmitting
862  ENET->RCR |= ENET_RCR_DRT_MASK;
863  }
864 
865  //Reset buffer descriptors
866  mk7xEthInitBufferDesc(interface);
867 
868  //Re-enable Ethernet MAC
869  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
870  //Instruct the DMA to poll the receive descriptor list
871  ENET->RDAR = ENET_RDAR_RDAR_MASK;
872 
873  //Successful processing
874  return NO_ERROR;
875 }
876 
877 
878 /**
879  * @brief Write PHY register
880  * @param[in] opcode Access type (2 bits)
881  * @param[in] phyAddr PHY address (5 bits)
882  * @param[in] regAddr Register address (5 bits)
883  * @param[in] data Register value
884  **/
885 
886 void mk7xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
887  uint8_t regAddr, uint16_t data)
888 {
889  uint32_t temp;
890 
891  //Valid opcode?
892  if(opcode == SMI_OPCODE_WRITE)
893  {
894  //Set up a write operation
895  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
896  //PHY address
897  temp |= ENET_MMFR_PA(phyAddr);
898  //Register address
899  temp |= ENET_MMFR_RA(regAddr);
900  //Register value
901  temp |= ENET_MMFR_DATA(data);
902 
903  //Clear MII interrupt flag
904  ENET->EIR = ENET_EIR_MII_MASK;
905  //Start a write operation
906  ENET->MMFR = temp;
907 
908  //Wait for the write to complete
909  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
910  {
911  }
912  }
913  else
914  {
915  //The MAC peripheral only supports standard Clause 22 opcodes
916  }
917 }
918 
919 
920 /**
921  * @brief Read PHY register
922  * @param[in] opcode Access type (2 bits)
923  * @param[in] phyAddr PHY address (5 bits)
924  * @param[in] regAddr Register address (5 bits)
925  * @return Register value
926  **/
927 
928 uint16_t mk7xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
929  uint8_t regAddr)
930 {
931  uint16_t data;
932  uint32_t temp;
933 
934  //Valid opcode?
935  if(opcode == SMI_OPCODE_READ)
936  {
937  //Set up a read operation
938  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
939  //PHY address
940  temp |= ENET_MMFR_PA(phyAddr);
941  //Register address
942  temp |= ENET_MMFR_RA(regAddr);
943 
944  //Clear MII interrupt flag
945  ENET->EIR = ENET_EIR_MII_MASK;
946  //Start a read operation
947  ENET->MMFR = temp;
948 
949  //Wait for the read to complete
950  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
951  {
952  }
953 
954  //Get register value
955  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
956  }
957  else
958  {
959  //The MAC peripheral only supports standard Clause 22 opcodes
960  data = 0;
961  }
962 
963  //Return the value of the PHY register
964  return data;
965 }
966 
967 
968 /**
969  * @brief CRC calculation
970  * @param[in] data Pointer to the data over which to calculate the CRC
971  * @param[in] length Number of bytes to process
972  * @return Resulting CRC value
973  **/
974 
975 uint32_t mk7xEthCalcCrc(const void *data, size_t length)
976 {
977  uint_t i;
978  uint_t j;
979  uint32_t crc;
980  const uint8_t *p;
981 
982  //Point to the data over which to calculate the CRC
983  p = (uint8_t *) data;
984  //CRC preset value
985  crc = 0xFFFFFFFF;
986 
987  //Loop through data
988  for(i = 0; i < length; i++)
989  {
990  //Update CRC value
991  crc ^= p[i];
992  //The message is processed bit by bit
993  for(j = 0; j < 8; j++)
994  {
995  if((crc & 0x01) != 0)
996  {
997  crc = (crc >> 1) ^ 0xEDB88320;
998  }
999  else
1000  {
1001  crc = crc >> 1;
1002  }
1003  }
1004  }
1005 
1006  //Return CRC value
1007  return crc;
1008 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
uint8_t opcode
Definition: dns_common.h:172
void ENET_Receive_IRQHandler(void)
Ethernet MAC receive interrupt.
int bool_t
Definition: compiler_port.h:49
uint32_t mk7xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define netEvent
Definition: net_legacy.h:267
#define MK7X_ETH_IRQ_GROUP_PRIORITY
uint8_t data[]
Definition: ethernet.h:209
#define ENET_TBD0_L
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define MK7X_ETH_TX_BUFFER_COUNT
#define ENET_RBD0_DATA_LENGTH
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MK7X_ETH_TX_BUFFER_SIZE
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
__start_packed struct @5 MacAddr
MAC address.
error_t mk7xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define ENET_TBD0_DATA_LENGTH
#define MK7X_ETH_IRQ_SUB_PRIORITY
#define ENET_TBD0_W
void mk7xEthInitGpio(NetInterface *interface)
#define MK7X_ETH_IRQ_PRIORITY_GROUPING
#define ENET_TBD0_TC
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
void ENET_Transmit_IRQHandler(void)
Ethernet MAC transmit interrupt.
void mk7xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define osExitIsr(flag)
error_t mk7xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define SMI_OPCODE_WRITE
Definition: nic.h:65
error_t mk7xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ENET_RBD0_L
error_t mk7xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define FALSE
Definition: os_port.h:46
const NicDriver mk7xEthDriver
Kinetis K7x Ethernet MAC driver.
#define MPU_CESR_VLD_MASK
error_t
Error codes.
Definition: error.h:42
uint8_t value[]
Definition: tcp.h:332
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define txBuffer
void ENET_Error_IRQHandler(void)
Ethernet MAC error interrupt.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
#define MK7X_ETH_RX_BUFFER_COUNT
MacAddr addr
MAC address.
Definition: ethernet.h:248
void mk7xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define ENET_RBD0_W
#define ENET_RBD0_TR
#define NetTxAncillary
Definition: net_misc.h:36
error_t mk7xEthInit(NetInterface *interface)
Kinetis K7x Ethernet MAC initialization.
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void mk7xEthEventHandler(NetInterface *interface)
Kinetis K7x Ethernet MAC event handler.
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
#define ENET_RBD0_LG
#define TRACE_DEBUG(...)
Definition: debug.h:107
uint16_t mk7xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint16_t regAddr
#define ENET_RBD0_CR
#define ENET_RBD0_OV
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define osEnterIsr()
#define MPU
#define ENET_TBD0_R
#define ENET_TBD2_INT
NXP Kinetis K70 Ethernet MAC driver.
#define ENET_RBD0_E
void mk7xEthTick(NetInterface *interface)
Kinetis K7x Ethernet MAC timer handler.
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MK7X_ETH_RX_BUFFER_SIZE
void mk7xEthEnableIrq(NetInterface *interface)
Enable interrupts.
unsigned int uint_t
Definition: compiler_port.h:45
#define osMemset(p, value, length)
Definition: os_port.h:128
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
#define ENET_RBD0_NO
#define ENET_RBD2_INT
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
void mk7xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
Ethernet interface.
Definition: nic.h:82