mkv5x_eth_driver.c
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1 /**
2  * @file mkv5x_eth_driver.c
3  * @brief Freescale Kinetis KV5x Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //MKV58F12 device?
33 #if defined(MKV58F22)
34  #include "mkv58f22.h"
35 #endif
36 
37 //Dependencies
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
51 //RX buffer
52 #pragma data_alignment = 16
54 //TX buffer descriptors
55 #pragma data_alignment = 16
56 static uint32_t txBufferDesc[MKV5X_ETH_TX_BUFFER_COUNT][8];
57 //RX buffer descriptors
58 #pragma data_alignment = 16
59 static uint32_t rxBufferDesc[MKV5X_ETH_RX_BUFFER_COUNT][8];
60 
61 //ARM or GCC compiler?
62 #else
63 
64 //TX buffer
66  __attribute__((aligned(16)));
67 //RX buffer
69  __attribute__((aligned(16)));
70 //TX buffer descriptors
71 static uint32_t txBufferDesc[MKV5X_ETH_TX_BUFFER_COUNT][8]
72  __attribute__((aligned(16)));
73 //RX buffer descriptors
74 static uint32_t rxBufferDesc[MKV5X_ETH_RX_BUFFER_COUNT][8]
75  __attribute__((aligned(16)));
76 
77 #endif
78 
79 //TX buffer index
80 static uint_t txBufferIndex;
81 //RX buffer index
82 static uint_t rxBufferIndex;
83 
84 
85 /**
86  * @brief Kinetis KV5x Ethernet MAC driver
87  **/
88 
90 {
92  ETH_MTU,
103  TRUE,
104  TRUE,
105  TRUE,
106  FALSE
107 };
108 
109 
110 /**
111  * @brief Kinetis KV5x Ethernet MAC initialization
112  * @param[in] interface Underlying network interface
113  * @return Error code
114  **/
115 
117 {
118  error_t error;
119  uint32_t value;
120 
121  //Debug message
122  TRACE_INFO("Initializing Kinetis KV5x Ethernet MAC...\r\n");
123 
124  //Save underlying network interface
125  nicDriverInterface = interface;
126 
127  //Disable MPU
128  MPU->CESR &= ~MPU_CESR_VLD_MASK;
129 
130  //Enable ENET peripheral clock
131  SIM->SCGC2 |= SIM_SCGC2_ENET_MASK;
132 
133  //GPIO configuration
134  mkv5xEthInitGpio(interface);
135 
136  //Reset ENET module
137  ENET->ECR = ENET_ECR_RESET_MASK;
138  //Wait for the reset to complete
139  while(ENET->ECR & ENET_ECR_RESET_MASK);
140 
141  //Receive control register
142  ENET->RCR = ENET_RCR_MAX_FL(1518) | ENET_RCR_MII_MODE_MASK;
143  //Transmit control register
144  ENET->TCR = 0;
145  //Configure MDC clock frequency
146  ENET->MSCR = ENET_MSCR_MII_SPEED(49);
147 
148  //PHY transceiver initialization
149  error = interface->phyDriver->init(interface);
150  //Failed to initialize PHY transceiver?
151  if(error)
152  return error;
153 
154  //Set the MAC address (upper 16 bits)
155  value = interface->macAddr.b[5];
156  value |= (interface->macAddr.b[4] << 8);
157  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
158 
159  //Set the MAC address (lower 32 bits)
160  value = interface->macAddr.b[3];
161  value |= (interface->macAddr.b[2] << 8);
162  value |= (interface->macAddr.b[1] << 16);
163  value |= (interface->macAddr.b[0] << 24);
164  ENET->PALR = ENET_PALR_PADDR1(value);
165 
166  //Hash table for unicast address filtering
167  ENET->IALR = 0;
168  ENET->IAUR = 0;
169  //Hash table for multicast address filtering
170  ENET->GALR = 0;
171  ENET->GAUR = 0;
172 
173  //Disable transmit accelerator functions
174  ENET->TACC = 0;
175  //Disable receive accelerator functions
176  ENET->RACC = 0;
177 
178  //Use enhanced buffer descriptors
179  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
180  //Clear MIC counters
181  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
182 
183  //Initialize buffer descriptors
184  mkv5xEthInitBufferDesc(interface);
185 
186  //Clear any pending interrupts
187  ENET->EIR = 0xFFFFFFFF;
188  //Enable desired interrupts
189  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
190 
191  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
192  NVIC_SetPriorityGrouping(MKV5X_ETH_IRQ_PRIORITY_GROUPING);
193 
194  //Configure ENET transmit interrupt priority
195  NVIC_SetPriority(ENET_Transmit_IRQn, NVIC_EncodePriority(MKV5X_ETH_IRQ_PRIORITY_GROUPING,
197 
198  //Configure ENET receive interrupt priority
199  NVIC_SetPriority(ENET_Receive_IRQn, NVIC_EncodePriority(MKV5X_ETH_IRQ_PRIORITY_GROUPING,
201 
202  //Configure ENET error interrupt priority
203  NVIC_SetPriority(ENET_Error_IRQn, NVIC_EncodePriority(MKV5X_ETH_IRQ_PRIORITY_GROUPING,
205 
206  //Enable Ethernet MAC
207  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
208  //Instruct the DMA to poll the receive descriptor list
209  ENET->RDAR = ENET_RDAR_RDAR_MASK;
210 
211  //Accept any packets from the upper layer
212  osSetEvent(&interface->nicTxEvent);
213 
214  //Successful initialization
215  return NO_ERROR;
216 }
217 
218 
219 //TWR-KV58F220M evaluation board?
220 #if defined(USE_TWR_KV58F220M)
221 
222 /**
223  * @brief GPIO configuration
224  * @param[in] interface Underlying network interface
225  **/
226 
227 void mkv5xEthInitGpio(NetInterface *interface)
228 {
229  //Enable PORTA peripheral clock
230  SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
231 
232  //Configure MII0_RXER (PTA5)
233  PORTA->PCR[5] = PORT_PCR_MUX(4) | PORT_PCR_PE_MASK;
234  //Configure MII0_MDIO (PTA7)
235  PORTA->PCR[7] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
236  //Configure MII0_MDC (PTA8)
237  PORTA->PCR[8] = PORT_PCR_MUX(5);
238  //Configure MII0_RXD3 (PTA9)
239  PORTA->PCR[9] = PORT_PCR_MUX(5);
240  //Configure MII0_RXD2 (PTA10)
241  PORTA->PCR[10] = PORT_PCR_MUX(5);
242  //Configure MII0_RXCLK (PTA11)
243  PORTA->PCR[11] = PORT_PCR_MUX(5);
244  //Configure MII0_RXD1 (PTA12)
245  PORTA->PCR[12] = PORT_PCR_MUX(5);
246  //Configure MII0_RXD0 (PTA13)
247  PORTA->PCR[13] = PORT_PCR_MUX(5);
248  //Configure MII0_RXDV (PTA14)
249  PORTA->PCR[14] = PORT_PCR_MUX(5);
250  //Configure MII0_TXEN (PTA15)
251  PORTA->PCR[15] = PORT_PCR_MUX(5);
252  //Configure MII0_TXD0 (PTA16)
253  PORTA->PCR[16] = PORT_PCR_MUX(5);
254  //Configure MII0_TXD1 (PTA17)
255  PORTA->PCR[17] = PORT_PCR_MUX(5);
256  //Configure MII0_TXD2 (PTA24)
257  PORTA->PCR[24] = PORT_PCR_MUX(5);
258  //Configure MII0_TXCLK (PTA25)
259  PORTA->PCR[25] = PORT_PCR_MUX(5);
260  //Configure MII0_TXD3 (PTA26)
261  PORTA->PCR[26] = PORT_PCR_MUX(5);
262  //Configure MII0_CRS (PTA27)
263  PORTA->PCR[27] = PORT_PCR_MUX(5);
264  //Configure MII0_COL (PTA29)
265  PORTA->PCR[29] = PORT_PCR_MUX(5);
266 }
267 
268 #endif
269 
270 
271 /**
272  * @brief Initialize buffer descriptors
273  * @param[in] interface Underlying network interface
274  **/
275 
277 {
278  uint_t i;
279  uint32_t address;
280 
281  //Clear TX and RX buffer descriptors
282  memset(txBufferDesc, 0, sizeof(txBufferDesc));
283  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
284 
285  //Initialize TX buffer descriptors
286  for(i = 0; i < MKV5X_ETH_TX_BUFFER_COUNT; i++)
287  {
288  //Calculate the address of the current TX buffer
289  address = (uint32_t) txBuffer[i];
290  //Transmit buffer address
291  txBufferDesc[i][1] = address;
292  //Generate interrupts
293  txBufferDesc[i][2] = ENET_TBD2_INT;
294  }
295 
296  //Mark the last descriptor entry with the wrap flag
297  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
298  //Initialize TX buffer index
299  txBufferIndex = 0;
300 
301  //Initialize RX buffer descriptors
302  for(i = 0; i < MKV5X_ETH_RX_BUFFER_COUNT; i++)
303  {
304  //Calculate the address of the current RX buffer
305  address = (uint32_t) rxBuffer[i];
306  //The descriptor is initially owned by the DMA
307  rxBufferDesc[i][0] = ENET_RBD0_E;
308  //Receive buffer address
309  rxBufferDesc[i][1] = address;
310  //Generate interrupts
311  rxBufferDesc[i][2] = ENET_RBD2_INT;
312  }
313 
314  //Mark the last descriptor entry with the wrap flag
315  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
316  //Initialize RX buffer index
317  rxBufferIndex = 0;
318 
319  //Start location of the TX descriptor list
320  ENET->TDSR = (uint32_t) txBufferDesc;
321  //Start location of the RX descriptor list
322  ENET->RDSR = (uint32_t) rxBufferDesc;
323  //Maximum receive buffer size
324  ENET->MRBR = MKV5X_ETH_RX_BUFFER_SIZE;
325 }
326 
327 
328 /**
329  * @brief Kinetis KV5x Ethernet MAC timer handler
330  *
331  * This routine is periodically called by the TCP/IP stack to
332  * handle periodic operations such as polling the link state
333  *
334  * @param[in] interface Underlying network interface
335  **/
336 
337 void mkv5xEthTick(NetInterface *interface)
338 {
339  //Handle periodic operations
340  interface->phyDriver->tick(interface);
341 }
342 
343 
344 /**
345  * @brief Enable interrupts
346  * @param[in] interface Underlying network interface
347  **/
348 
350 {
351  //Enable Ethernet MAC interrupts
352  NVIC_EnableIRQ(ENET_Transmit_IRQn);
353  NVIC_EnableIRQ(ENET_Receive_IRQn);
354  NVIC_EnableIRQ(ENET_Error_IRQn);
355 
356  //Enable Ethernet PHY interrupts
357  interface->phyDriver->enableIrq(interface);
358 }
359 
360 
361 /**
362  * @brief Disable interrupts
363  * @param[in] interface Underlying network interface
364  **/
365 
367 {
368  //Disable Ethernet MAC interrupts
369  NVIC_DisableIRQ(ENET_Transmit_IRQn);
370  NVIC_DisableIRQ(ENET_Receive_IRQn);
371  NVIC_DisableIRQ(ENET_Error_IRQn);
372 
373  //Disable Ethernet PHY interrupts
374  interface->phyDriver->disableIrq(interface);
375 }
376 
377 
378 /**
379  * @brief Ethernet MAC transmit interrupt
380  **/
381 
383 {
384  bool_t flag;
385 
386  //Enter interrupt service routine
387  osEnterIsr();
388 
389  //This flag will be set if a higher priority task must be woken
390  flag = FALSE;
391 
392  //A packet has been transmitted?
393  if(ENET->EIR & ENET_EIR_TXF_MASK)
394  {
395  //Clear TXF interrupt flag
396  ENET->EIR = ENET_EIR_TXF_MASK;
397 
398  //Check whether the TX buffer is available for writing
399  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
400  {
401  //Notify the TCP/IP stack that the transmitter is ready to send
402  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
403  }
404 
405  //Instruct the DMA to poll the transmit descriptor list
406  ENET->TDAR = ENET_TDAR_TDAR_MASK;
407  }
408 
409  //Leave interrupt service routine
410  osExitIsr(flag);
411 }
412 
413 
414 /**
415  * @brief Ethernet MAC receive interrupt
416  **/
417 
419 {
420  bool_t flag;
421 
422  //Enter interrupt service routine
423  osEnterIsr();
424 
425  //This flag will be set if a higher priority task must be woken
426  flag = FALSE;
427 
428  //A packet has been received?
429  if(ENET->EIR & ENET_EIR_RXF_MASK)
430  {
431  //Disable RXF interrupt
432  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
433 
434  //Set event flag
435  nicDriverInterface->nicEvent = TRUE;
436  //Notify the TCP/IP stack of the event
437  flag = osSetEventFromIsr(&netEvent);
438  }
439 
440  //Leave interrupt service routine
441  osExitIsr(flag);
442 }
443 
444 
445 /**
446  * @brief Ethernet MAC error interrupt
447  **/
448 
450 {
451  bool_t flag;
452 
453  //Enter interrupt service routine
454  osEnterIsr();
455 
456  //This flag will be set if a higher priority task must be woken
457  flag = FALSE;
458 
459  //System bus error?
460  if(ENET->EIR & ENET_EIR_EBERR_MASK)
461  {
462  //Disable EBERR interrupt
463  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
464 
465  //Set event flag
466  nicDriverInterface->nicEvent = TRUE;
467  //Notify the TCP/IP stack of the event
468  flag |= osSetEventFromIsr(&netEvent);
469  }
470 
471  //Leave interrupt service routine
472  osExitIsr(flag);
473 }
474 
475 
476 /**
477  * @brief Kinetis KV5x Ethernet MAC event handler
478  * @param[in] interface Underlying network interface
479  **/
480 
482 {
483  error_t error;
484  uint32_t status;
485 
486  //Read interrupt event register
487  status = ENET->EIR;
488 
489  //Packet received?
490  if(status & ENET_EIR_RXF_MASK)
491  {
492  //Clear RXF interrupt flag
493  ENET->EIR = ENET_EIR_RXF_MASK;
494 
495  //Process all pending packets
496  do
497  {
498  //Read incoming packet
499  error = mkv5xEthReceivePacket(interface);
500 
501  //No more data in the receive buffer?
502  } while(error != ERROR_BUFFER_EMPTY);
503  }
504 
505  //System bus error?
506  if(status & ENET_EIR_EBERR_MASK)
507  {
508  //Clear EBERR interrupt flag
509  ENET->EIR = ENET_EIR_EBERR_MASK;
510 
511  //Disable Ethernet MAC
512  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
513  //Reset buffer descriptors
514  mkv5xEthInitBufferDesc(interface);
515  //Resume normal operation
516  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
517  //Instruct the DMA to poll the receive descriptor list
518  ENET->RDAR = ENET_RDAR_RDAR_MASK;
519  }
520 
521  //Re-enable Ethernet MAC interrupts
522  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
523 }
524 
525 
526 /**
527  * @brief Send a packet
528  * @param[in] interface Underlying network interface
529  * @param[in] buffer Multi-part buffer containing the data to send
530  * @param[in] offset Offset to the first data byte
531  * @return Error code
532  **/
533 
535  const NetBuffer *buffer, size_t offset)
536 {
537  static uint8_t temp[MKV5X_ETH_TX_BUFFER_SIZE];
538  size_t length;
539 
540  //Retrieve the length of the packet
541  length = netBufferGetLength(buffer) - offset;
542 
543  //Check the frame length
545  {
546  //The transmitter can accept another packet
547  osSetEvent(&interface->nicTxEvent);
548  //Report an error
549  return ERROR_INVALID_LENGTH;
550  }
551 
552  //Make sure the current buffer is available for writing
553  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
554  return ERROR_FAILURE;
555 
556  //Copy user data to the transmit buffer
557  netBufferRead(temp, buffer, offset, length);
558  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
559 
560  //Clear BDU flag
561  txBufferDesc[txBufferIndex][4] = 0;
562 
563  //Check current index
564  if(txBufferIndex < (MKV5X_ETH_TX_BUFFER_COUNT - 1))
565  {
566  //Give the ownership of the descriptor to the DMA engine
567  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
569 
570  //Point to the next buffer
571  txBufferIndex++;
572  }
573  else
574  {
575  //Give the ownership of the descriptor to the DMA engine
576  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
578 
579  //Wrap around
580  txBufferIndex = 0;
581  }
582 
583  //Data synchronization barrier
584  __DSB();
585 
586  //Instruct the DMA to poll the transmit descriptor list
587  ENET->TDAR = ENET_TDAR_TDAR_MASK;
588 
589  //Check whether the next buffer is available for writing
590  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
591  {
592  //The transmitter can accept another packet
593  osSetEvent(&interface->nicTxEvent);
594  }
595 
596  //Successful processing
597  return NO_ERROR;
598 }
599 
600 
601 /**
602  * @brief Receive a packet
603  * @param[in] interface Underlying network interface
604  * @return Error code
605  **/
606 
608 {
609  static uint8_t temp[MKV5X_ETH_RX_BUFFER_SIZE];
610  error_t error;
611  size_t n;
612 
613  //Make sure the current buffer is available for reading
614  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
615  {
616  //The frame should not span multiple buffers
617  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
618  {
619  //Check whether an error occurred
620  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
622  {
623  //Retrieve the length of the frame
624  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
625  //Limit the number of data to read
627 
628  //Copy data from the receive buffer
629  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
630 
631  //Pass the packet to the upper layer
632  nicProcessPacket(interface, temp, n);
633 
634  //Valid packet received
635  error = NO_ERROR;
636  }
637  else
638  {
639  //The received packet contains an error
640  error = ERROR_INVALID_PACKET;
641  }
642  }
643  else
644  {
645  //The packet is not valid
646  error = ERROR_INVALID_PACKET;
647  }
648 
649  //Clear BDU flag
650  rxBufferDesc[rxBufferIndex][4] = 0;
651 
652  //Check current index
653  if(rxBufferIndex < (MKV5X_ETH_RX_BUFFER_COUNT - 1))
654  {
655  //Give the ownership of the descriptor back to the DMA engine
656  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
657  //Point to the next buffer
658  rxBufferIndex++;
659  }
660  else
661  {
662  //Give the ownership of the descriptor back to the DMA engine
663  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
664  //Wrap around
665  rxBufferIndex = 0;
666  }
667 
668  //Instruct the DMA to poll the receive descriptor list
669  ENET->RDAR = ENET_RDAR_RDAR_MASK;
670  }
671  else
672  {
673  //No more data in the receive buffer
674  error = ERROR_BUFFER_EMPTY;
675  }
676 
677  //Return status code
678  return error;
679 }
680 
681 
682 /**
683  * @brief Configure MAC address filtering
684  * @param[in] interface Underlying network interface
685  * @return Error code
686  **/
687 
689 {
690  uint_t i;
691  uint_t k;
692  uint32_t crc;
693  uint32_t unicastHashTable[2];
694  uint32_t multicastHashTable[2];
695  MacFilterEntry *entry;
696 
697  //Debug message
698  TRACE_DEBUG("Updating Kinetis KV5x hash table...\r\n");
699 
700  //Clear hash table (unicast address filtering)
701  unicastHashTable[0] = 0;
702  unicastHashTable[1] = 0;
703 
704  //Clear hash table (multicast address filtering)
705  multicastHashTable[0] = 0;
706  multicastHashTable[1] = 0;
707 
708  //The MAC address filter contains the list of MAC addresses to accept
709  //when receiving an Ethernet frame
710  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
711  {
712  //Point to the current entry
713  entry = &interface->macAddrFilter[i];
714 
715  //Valid entry?
716  if(entry->refCount > 0)
717  {
718  //Compute CRC over the current MAC address
719  crc = mkv5xEthCalcCrc(&entry->addr, sizeof(MacAddr));
720 
721  //The upper 6 bits in the CRC register are used to index the
722  //contents of the hash table
723  k = (crc >> 26) & 0x3F;
724 
725  //Multicast address?
726  if(macIsMulticastAddr(&entry->addr))
727  {
728  //Update the multicast hash table
729  multicastHashTable[k / 32] |= (1 << (k % 32));
730  }
731  else
732  {
733  //Update the unicast hash table
734  unicastHashTable[k / 32] |= (1 << (k % 32));
735  }
736  }
737  }
738 
739  //Write the hash table (unicast address filtering)
740  ENET->IALR = unicastHashTable[0];
741  ENET->IAUR = unicastHashTable[1];
742 
743  //Write the hash table (multicast address filtering)
744  ENET->GALR = multicastHashTable[0];
745  ENET->GAUR = multicastHashTable[1];
746 
747  //Debug message
748  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
749  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
750  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
751  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
752 
753  //Successful processing
754  return NO_ERROR;
755 }
756 
757 
758 /**
759  * @brief Adjust MAC configuration parameters for proper operation
760  * @param[in] interface Underlying network interface
761  * @return Error code
762  **/
763 
765 {
766  //Disable Ethernet MAC while modifying configuration registers
767  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
768 
769  //10BASE-T or 100BASE-TX operation mode?
770  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
771  {
772  //100 Mbps operation
773  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
774  }
775  else
776  {
777  //10 Mbps operation
778  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
779  }
780 
781  //Half-duplex or full-duplex mode?
782  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
783  {
784  //Full-duplex mode
785  ENET->TCR |= ENET_TCR_FDEN_MASK;
786  //Receive path operates independently of transmit
787  ENET->RCR &= ~ENET_RCR_DRT_MASK;
788  }
789  else
790  {
791  //Half-duplex mode
792  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
793  //Disable reception of frames while transmitting
794  ENET->RCR |= ENET_RCR_DRT_MASK;
795  }
796 
797  //Reset buffer descriptors
798  mkv5xEthInitBufferDesc(interface);
799 
800  //Re-enable Ethernet MAC
801  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
802  //Instruct the DMA to poll the receive descriptor list
803  ENET->RDAR = ENET_RDAR_RDAR_MASK;
804 
805  //Successful processing
806  return NO_ERROR;
807 }
808 
809 
810 /**
811  * @brief Write PHY register
812  * @param[in] phyAddr PHY address
813  * @param[in] regAddr Register address
814  * @param[in] data Register value
815  **/
816 
817 void mkv5xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
818 {
819  uint32_t value;
820 
821  //Set up a write operation
822  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
823  //PHY address
824  value |= ENET_MMFR_PA(phyAddr);
825  //Register address
826  value |= ENET_MMFR_RA(regAddr);
827  //Register value
828  value |= ENET_MMFR_DATA(data);
829 
830  //Clear MII interrupt flag
831  ENET->EIR = ENET_EIR_MII_MASK;
832  //Start a write operation
833  ENET->MMFR = value;
834  //Wait for the write to complete
835  while(!(ENET->EIR & ENET_EIR_MII_MASK));
836 }
837 
838 
839 /**
840  * @brief Read PHY register
841  * @param[in] phyAddr PHY address
842  * @param[in] regAddr Register address
843  * @return Register value
844  **/
845 
846 uint16_t mkv5xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
847 {
848  uint32_t value;
849 
850  //Set up a read operation
851  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
852  //PHY address
853  value |= ENET_MMFR_PA(phyAddr);
854  //Register address
855  value |= ENET_MMFR_RA(regAddr);
856 
857  //Clear MII interrupt flag
858  ENET->EIR = ENET_EIR_MII_MASK;
859  //Start a read operation
860  ENET->MMFR = value;
861  //Wait for the read to complete
862  while(!(ENET->EIR & ENET_EIR_MII_MASK));
863 
864  //Return PHY register contents
865  return ENET->MMFR & ENET_MMFR_DATA_MASK;
866 }
867 
868 
869 /**
870  * @brief CRC calculation
871  * @param[in] data Pointer to the data over which to calculate the CRC
872  * @param[in] length Number of bytes to process
873  * @return Resulting CRC value
874  **/
875 
876 uint32_t mkv5xEthCalcCrc(const void *data, size_t length)
877 {
878  uint_t i;
879  uint_t j;
880 
881  //Point to the data over which to calculate the CRC
882  const uint8_t *p = (uint8_t *) data;
883  //CRC preset value
884  uint32_t crc = 0xFFFFFFFF;
885 
886  //Loop through data
887  for(i = 0; i < length; i++)
888  {
889  //Update CRC value
890  crc ^= p[i];
891  //The message is processed bit by bit
892  for(j = 0; j < 8; j++)
893  {
894  if(crc & 0x00000001)
895  crc = (crc >> 1) ^ 0xEDB88320;
896  else
897  crc = crc >> 1;
898  }
899  }
900 
901  //Return CRC value
902  return crc;
903 }
#define MKV5X_ETH_IRQ_GROUP_PRIORITY
MacAddr addr
MAC address.
Definition: ethernet.h:210
void mkv5xEthEventHandler(NetInterface *interface)
Kinetis KV5x Ethernet MAC event handler.
void ENET_Error_IRQHandler(void)
Ethernet MAC error interrupt.
error_t mkv5xEthInit(NetInterface *interface)
Kinetis KV5x Ethernet MAC initialization.
TCP/IP stack core.
#define MKV5X_ETH_IRQ_SUB_PRIORITY
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
uint16_t mkv5xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Generic error code.
Definition: error.h:43
#define ENET_RBD0_DATA_LENGTH
error_t mkv5xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:98
error_t mkv5xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define txBuffer
#define ENET_TBD0_TC
#define MKV5X_ETH_RX_BUFFER_COUNT
#define ENET_RBD0_TR
#define ENET_TBD2_INT
#define ENET_TBD0_L
void mkv5xEthTick(NetInterface *interface)
Kinetis KV5x Ethernet MAC timer handler.
uint32_t mkv5xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
void mkv5xEthEnableIrq(NetInterface *interface)
Enable interrupts.
Freescale Kinetis KV5x Ethernet MAC controller.
#define ENET_RBD0_W
const NicDriver mkv5xEthDriver
Kinetis KV5x Ethernet MAC driver.
#define MPU
#define ENET_TBD0_R
#define ENET_RBD0_CR
#define ENET_RBD0_NO
void mkv5xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define ENET_RBD0_E
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define MKV5X_ETH_TX_BUFFER_COUNT
#define ENET_RBD0_LG
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define MKV5X_ETH_IRQ_PRIORITY_GROUPING
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
#define ENET_TBD0_W
Success.
Definition: error.h:42
error_t mkv5xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MPU_CESR_VLD_MASK
error_t
Error codes.
Definition: error.h:40
void mkv5xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define ENET_RBD2_INT
unsigned int uint_t
Definition: compiler_port.h:43
__start_packed struct @112 MacAddr
MAC address.
void mkv5xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MKV5X_ETH_RX_BUFFER_SIZE
uint8_t data[]
Definition: dtls_misc.h:167
void ENET_Receive_IRQHandler(void)
Ethernet MAC receive interrupt.
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define MKV5X_ETH_TX_BUFFER_SIZE
#define osExitIsr(flag)
#define ENET_TBD0_DATA_LENGTH
#define osEnterIsr()
error_t mkv5xEthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
void mkv5xEthInitGpio(NetInterface *interface)
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
void ENET_Transmit_IRQHandler(void)
Ethernet MAC transmit interrupt.
#define ENET_RBD0_OV
#define ENET_RBD0_L
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98