mkv5x_eth_driver.c
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1 /**
2  * @file mkv5x_eth_driver.c
3  * @brief NXP Kinetis KV5x Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //MKV58F12 device?
35 #if defined(MKV58F22)
36  #include "mkv58f22.h"
37 #endif
38 
39 //Dependencies
40 #include "core/net.h"
42 #include "debug.h"
43 
44 //Underlying network interface
45 static NetInterface *nicDriverInterface;
46 
47 //IAR EWARM compiler?
48 #if defined(__ICCARM__)
49 
50 //TX buffer
51 #pragma data_alignment = 16
53 //RX buffer
54 #pragma data_alignment = 16
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 static uint32_t txBufferDesc[MKV5X_ETH_TX_BUFFER_COUNT][8];
59 //RX buffer descriptors
60 #pragma data_alignment = 16
61 static uint32_t rxBufferDesc[MKV5X_ETH_RX_BUFFER_COUNT][8];
62 
63 //ARM or GCC compiler?
64 #else
65 
66 //TX buffer
68  __attribute__((aligned(16)));
69 //RX buffer
71  __attribute__((aligned(16)));
72 //TX buffer descriptors
73 static uint32_t txBufferDesc[MKV5X_ETH_TX_BUFFER_COUNT][8]
74  __attribute__((aligned(16)));
75 //RX buffer descriptors
76 static uint32_t rxBufferDesc[MKV5X_ETH_RX_BUFFER_COUNT][8]
77  __attribute__((aligned(16)));
78 
79 #endif
80 
81 //TX buffer index
82 static uint_t txBufferIndex;
83 //RX buffer index
84 static uint_t rxBufferIndex;
85 
86 
87 /**
88  * @brief Kinetis KV5x Ethernet MAC driver
89  **/
90 
92 {
94  ETH_MTU,
105  TRUE,
106  TRUE,
107  TRUE,
108  FALSE
109 };
110 
111 
112 /**
113  * @brief Kinetis KV5x Ethernet MAC initialization
114  * @param[in] interface Underlying network interface
115  * @return Error code
116  **/
117 
119 {
120  error_t error;
121  uint32_t value;
122 
123  //Debug message
124  TRACE_INFO("Initializing Kinetis KV5x Ethernet MAC...\r\n");
125 
126  //Save underlying network interface
127  nicDriverInterface = interface;
128 
129  //Disable MPU
130  MPU->CESR &= ~MPU_CESR_VLD_MASK;
131 
132  //Enable ENET peripheral clock
133  SIM->SCGC2 |= SIM_SCGC2_ENET_MASK;
134 
135  //GPIO configuration
136  mkv5xEthInitGpio(interface);
137 
138  //Reset ENET module
139  ENET->ECR = ENET_ECR_RESET_MASK;
140  //Wait for the reset to complete
141  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
142  {
143  }
144 
145  //Receive control register
146  ENET->RCR = ENET_RCR_MAX_FL(MKV5X_ETH_RX_BUFFER_SIZE) |
147  ENET_RCR_MII_MODE_MASK;
148 
149  //Transmit control register
150  ENET->TCR = 0;
151  //Configure MDC clock frequency
152  ENET->MSCR = ENET_MSCR_MII_SPEED(49);
153 
154  //Valid Ethernet PHY or switch driver?
155  if(interface->phyDriver != NULL)
156  {
157  //Ethernet PHY initialization
158  error = interface->phyDriver->init(interface);
159  }
160  else if(interface->switchDriver != NULL)
161  {
162  //Ethernet switch initialization
163  error = interface->switchDriver->init(interface);
164  }
165  else
166  {
167  //The interface is not properly configured
168  error = ERROR_FAILURE;
169  }
170 
171  //Any error to report?
172  if(error)
173  {
174  return error;
175  }
176 
177  //Set the MAC address of the station (upper 16 bits)
178  value = interface->macAddr.b[5];
179  value |= (interface->macAddr.b[4] << 8);
180  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
181 
182  //Set the MAC address of the station (lower 32 bits)
183  value = interface->macAddr.b[3];
184  value |= (interface->macAddr.b[2] << 8);
185  value |= (interface->macAddr.b[1] << 16);
186  value |= (interface->macAddr.b[0] << 24);
187  ENET->PALR = ENET_PALR_PADDR1(value);
188 
189  //Hash table for unicast address filtering
190  ENET->IALR = 0;
191  ENET->IAUR = 0;
192  //Hash table for multicast address filtering
193  ENET->GALR = 0;
194  ENET->GAUR = 0;
195 
196  //Disable transmit accelerator functions
197  ENET->TACC = 0;
198  //Disable receive accelerator functions
199  ENET->RACC = 0;
200 
201  //Use enhanced buffer descriptors
202  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
203 
204  //Reset statistics counters
205  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
206  ENET->MIBC = 0;
207 
208  //Initialize buffer descriptors
209  mkv5xEthInitBufferDesc(interface);
210 
211  //Clear any pending interrupts
212  ENET->EIR = 0xFFFFFFFF;
213  //Enable desired interrupts
214  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
215 
216  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
217  NVIC_SetPriorityGrouping(MKV5X_ETH_IRQ_PRIORITY_GROUPING);
218 
219  //Configure ENET transmit interrupt priority
220  NVIC_SetPriority(ENET_Transmit_IRQn, NVIC_EncodePriority(MKV5X_ETH_IRQ_PRIORITY_GROUPING,
222 
223  //Configure ENET receive interrupt priority
224  NVIC_SetPriority(ENET_Receive_IRQn, NVIC_EncodePriority(MKV5X_ETH_IRQ_PRIORITY_GROUPING,
226 
227  //Configure ENET error interrupt priority
228  NVIC_SetPriority(ENET_Error_IRQn, NVIC_EncodePriority(MKV5X_ETH_IRQ_PRIORITY_GROUPING,
230 
231  //Enable Ethernet MAC
232  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
233  //Instruct the DMA to poll the receive descriptor list
234  ENET->RDAR = ENET_RDAR_RDAR_MASK;
235 
236  //Accept any packets from the upper layer
237  osSetEvent(&interface->nicTxEvent);
238 
239  //Successful initialization
240  return NO_ERROR;
241 }
242 
243 
244 //TWR-KV58F220M evaluation board?
245 #if defined(USE_TWR_KV58F220M)
246 
247 /**
248  * @brief GPIO configuration
249  * @param[in] interface Underlying network interface
250  **/
251 
252 void mkv5xEthInitGpio(NetInterface *interface)
253 {
254  //Enable PORTA peripheral clock
255  SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
256 
257  //Configure MII0_RXER (PTA5)
258  PORTA->PCR[5] = PORT_PCR_MUX(4) | PORT_PCR_PE_MASK;
259  //Configure MII0_MDIO (PTA7)
260  PORTA->PCR[7] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
261  //Configure MII0_MDC (PTA8)
262  PORTA->PCR[8] = PORT_PCR_MUX(5);
263  //Configure MII0_RXD3 (PTA9)
264  PORTA->PCR[9] = PORT_PCR_MUX(5);
265  //Configure MII0_RXD2 (PTA10)
266  PORTA->PCR[10] = PORT_PCR_MUX(5);
267  //Configure MII0_RXCLK (PTA11)
268  PORTA->PCR[11] = PORT_PCR_MUX(5);
269  //Configure MII0_RXD1 (PTA12)
270  PORTA->PCR[12] = PORT_PCR_MUX(5);
271  //Configure MII0_RXD0 (PTA13)
272  PORTA->PCR[13] = PORT_PCR_MUX(5);
273  //Configure MII0_RXDV (PTA14)
274  PORTA->PCR[14] = PORT_PCR_MUX(5);
275  //Configure MII0_TXEN (PTA15)
276  PORTA->PCR[15] = PORT_PCR_MUX(5);
277  //Configure MII0_TXD0 (PTA16)
278  PORTA->PCR[16] = PORT_PCR_MUX(5);
279  //Configure MII0_TXD1 (PTA17)
280  PORTA->PCR[17] = PORT_PCR_MUX(5);
281  //Configure MII0_TXD2 (PTA24)
282  PORTA->PCR[24] = PORT_PCR_MUX(5);
283  //Configure MII0_TXCLK (PTA25)
284  PORTA->PCR[25] = PORT_PCR_MUX(5);
285  //Configure MII0_TXD3 (PTA26)
286  PORTA->PCR[26] = PORT_PCR_MUX(5);
287  //Configure MII0_CRS (PTA27)
288  PORTA->PCR[27] = PORT_PCR_MUX(5);
289  //Configure MII0_COL (PTA29)
290  PORTA->PCR[29] = PORT_PCR_MUX(5);
291 }
292 
293 #endif
294 
295 
296 /**
297  * @brief Initialize buffer descriptors
298  * @param[in] interface Underlying network interface
299  **/
300 
302 {
303  uint_t i;
304  uint32_t address;
305 
306  //Clear TX and RX buffer descriptors
307  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
308  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
309 
310  //Initialize TX buffer descriptors
311  for(i = 0; i < MKV5X_ETH_TX_BUFFER_COUNT; i++)
312  {
313  //Calculate the address of the current TX buffer
314  address = (uint32_t) txBuffer[i];
315  //Transmit buffer address
316  txBufferDesc[i][1] = address;
317  //Generate interrupts
318  txBufferDesc[i][2] = ENET_TBD2_INT;
319  }
320 
321  //Mark the last descriptor entry with the wrap flag
322  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
323  //Initialize TX buffer index
324  txBufferIndex = 0;
325 
326  //Initialize RX buffer descriptors
327  for(i = 0; i < MKV5X_ETH_RX_BUFFER_COUNT; i++)
328  {
329  //Calculate the address of the current RX buffer
330  address = (uint32_t) rxBuffer[i];
331  //The descriptor is initially owned by the DMA
332  rxBufferDesc[i][0] = ENET_RBD0_E;
333  //Receive buffer address
334  rxBufferDesc[i][1] = address;
335  //Generate interrupts
336  rxBufferDesc[i][2] = ENET_RBD2_INT;
337  }
338 
339  //Mark the last descriptor entry with the wrap flag
340  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
341  //Initialize RX buffer index
342  rxBufferIndex = 0;
343 
344  //Start location of the TX descriptor list
345  ENET->TDSR = (uint32_t) txBufferDesc;
346  //Start location of the RX descriptor list
347  ENET->RDSR = (uint32_t) rxBufferDesc;
348  //Maximum receive buffer size
349  ENET->MRBR = MKV5X_ETH_RX_BUFFER_SIZE;
350 }
351 
352 
353 /**
354  * @brief Kinetis KV5x Ethernet MAC timer handler
355  *
356  * This routine is periodically called by the TCP/IP stack to handle periodic
357  * operations such as polling the link state
358  *
359  * @param[in] interface Underlying network interface
360  **/
361 
362 void mkv5xEthTick(NetInterface *interface)
363 {
364  //Valid Ethernet PHY or switch driver?
365  if(interface->phyDriver != NULL)
366  {
367  //Handle periodic operations
368  interface->phyDriver->tick(interface);
369  }
370  else if(interface->switchDriver != NULL)
371  {
372  //Handle periodic operations
373  interface->switchDriver->tick(interface);
374  }
375  else
376  {
377  //Just for sanity
378  }
379 }
380 
381 
382 /**
383  * @brief Enable interrupts
384  * @param[in] interface Underlying network interface
385  **/
386 
388 {
389  //Enable Ethernet MAC interrupts
390  NVIC_EnableIRQ(ENET_Transmit_IRQn);
391  NVIC_EnableIRQ(ENET_Receive_IRQn);
392  NVIC_EnableIRQ(ENET_Error_IRQn);
393 
394 
395  //Valid Ethernet PHY or switch driver?
396  if(interface->phyDriver != NULL)
397  {
398  //Enable Ethernet PHY interrupts
399  interface->phyDriver->enableIrq(interface);
400  }
401  else if(interface->switchDriver != NULL)
402  {
403  //Enable Ethernet switch interrupts
404  interface->switchDriver->enableIrq(interface);
405  }
406  else
407  {
408  //Just for sanity
409  }
410 }
411 
412 
413 /**
414  * @brief Disable interrupts
415  * @param[in] interface Underlying network interface
416  **/
417 
419 {
420  //Disable Ethernet MAC interrupts
421  NVIC_DisableIRQ(ENET_Transmit_IRQn);
422  NVIC_DisableIRQ(ENET_Receive_IRQn);
423  NVIC_DisableIRQ(ENET_Error_IRQn);
424 
425 
426  //Valid Ethernet PHY or switch driver?
427  if(interface->phyDriver != NULL)
428  {
429  //Disable Ethernet PHY interrupts
430  interface->phyDriver->disableIrq(interface);
431  }
432  else if(interface->switchDriver != NULL)
433  {
434  //Disable Ethernet switch interrupts
435  interface->switchDriver->disableIrq(interface);
436  }
437  else
438  {
439  //Just for sanity
440  }
441 }
442 
443 
444 /**
445  * @brief Ethernet MAC transmit interrupt
446  **/
447 
449 {
450  bool_t flag;
451 
452  //Interrupt service routine prologue
453  osEnterIsr();
454 
455  //This flag will be set if a higher priority task must be woken
456  flag = FALSE;
457 
458  //Packet transmitted?
459  if((ENET->EIR & ENET_EIR_TXF_MASK) != 0)
460  {
461  //Clear TXF interrupt flag
462  ENET->EIR = ENET_EIR_TXF_MASK;
463 
464  //Check whether the TX buffer is available for writing
465  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
466  {
467  //Notify the TCP/IP stack that the transmitter is ready to send
468  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
469  }
470 
471  //Instruct the DMA to poll the transmit descriptor list
472  ENET->TDAR = ENET_TDAR_TDAR_MASK;
473  }
474 
475  //Interrupt service routine epilogue
476  osExitIsr(flag);
477 }
478 
479 
480 /**
481  * @brief Ethernet MAC receive interrupt
482  **/
483 
485 {
486  bool_t flag;
487 
488  //Interrupt service routine prologue
489  osEnterIsr();
490 
491  //This flag will be set if a higher priority task must be woken
492  flag = FALSE;
493 
494  //Packet received?
495  if((ENET->EIR & ENET_EIR_RXF_MASK) != 0)
496  {
497  //Disable RXF interrupt
498  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
499 
500  //Set event flag
501  nicDriverInterface->nicEvent = TRUE;
502  //Notify the TCP/IP stack of the event
503  flag = osSetEventFromIsr(&netEvent);
504  }
505 
506  //Interrupt service routine epilogue
507  osExitIsr(flag);
508 }
509 
510 
511 /**
512  * @brief Ethernet MAC error interrupt
513  **/
514 
516 {
517  bool_t flag;
518 
519  //Interrupt service routine prologue
520  osEnterIsr();
521 
522  //This flag will be set if a higher priority task must be woken
523  flag = FALSE;
524 
525  //System bus error?
526  if((ENET->EIR & ENET_EIR_EBERR_MASK) != 0)
527  {
528  //Disable EBERR interrupt
529  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
530 
531  //Set event flag
532  nicDriverInterface->nicEvent = TRUE;
533  //Notify the TCP/IP stack of the event
534  flag |= osSetEventFromIsr(&netEvent);
535  }
536 
537  //Interrupt service routine epilogue
538  osExitIsr(flag);
539 }
540 
541 
542 /**
543  * @brief Kinetis KV5x Ethernet MAC event handler
544  * @param[in] interface Underlying network interface
545  **/
546 
548 {
549  error_t error;
550  uint32_t status;
551 
552  //Read interrupt event register
553  status = ENET->EIR;
554 
555  //Packet received?
556  if((status & ENET_EIR_RXF_MASK) != 0)
557  {
558  //Clear RXF interrupt flag
559  ENET->EIR = ENET_EIR_RXF_MASK;
560 
561  //Process all pending packets
562  do
563  {
564  //Read incoming packet
565  error = mkv5xEthReceivePacket(interface);
566 
567  //No more data in the receive buffer?
568  } while(error != ERROR_BUFFER_EMPTY);
569  }
570 
571  //System bus error?
572  if((status & ENET_EIR_EBERR_MASK) != 0)
573  {
574  //Clear EBERR interrupt flag
575  ENET->EIR = ENET_EIR_EBERR_MASK;
576 
577  //Disable Ethernet MAC
578  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
579  //Reset buffer descriptors
580  mkv5xEthInitBufferDesc(interface);
581  //Resume normal operation
582  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
583  //Instruct the DMA to poll the receive descriptor list
584  ENET->RDAR = ENET_RDAR_RDAR_MASK;
585  }
586 
587  //Re-enable Ethernet MAC interrupts
588  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
589 }
590 
591 
592 /**
593  * @brief Send a packet
594  * @param[in] interface Underlying network interface
595  * @param[in] buffer Multi-part buffer containing the data to send
596  * @param[in] offset Offset to the first data byte
597  * @param[in] ancillary Additional options passed to the stack along with
598  * the packet
599  * @return Error code
600  **/
601 
603  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
604 {
605  static uint8_t temp[MKV5X_ETH_TX_BUFFER_SIZE];
606  size_t length;
607 
608  //Retrieve the length of the packet
609  length = netBufferGetLength(buffer) - offset;
610 
611  //Check the frame length
613  {
614  //The transmitter can accept another packet
615  osSetEvent(&interface->nicTxEvent);
616  //Report an error
617  return ERROR_INVALID_LENGTH;
618  }
619 
620  //Make sure the current buffer is available for writing
621  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
622  {
623  return ERROR_FAILURE;
624  }
625 
626  //Copy user data to the transmit buffer
627  netBufferRead(temp, buffer, offset, length);
628  osMemcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
629 
630  //Clear BDU flag
631  txBufferDesc[txBufferIndex][4] = 0;
632 
633  //Check current index
634  if(txBufferIndex < (MKV5X_ETH_TX_BUFFER_COUNT - 1))
635  {
636  //Give the ownership of the descriptor to the DMA engine
637  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
639 
640  //Point to the next buffer
641  txBufferIndex++;
642  }
643  else
644  {
645  //Give the ownership of the descriptor to the DMA engine
646  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
648 
649  //Wrap around
650  txBufferIndex = 0;
651  }
652 
653  //Data synchronization barrier
654  __DSB();
655 
656  //Instruct the DMA to poll the transmit descriptor list
657  ENET->TDAR = ENET_TDAR_TDAR_MASK;
658 
659  //Check whether the next buffer is available for writing
660  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
661  {
662  //The transmitter can accept another packet
663  osSetEvent(&interface->nicTxEvent);
664  }
665 
666  //Successful processing
667  return NO_ERROR;
668 }
669 
670 
671 /**
672  * @brief Receive a packet
673  * @param[in] interface Underlying network interface
674  * @return Error code
675  **/
676 
678 {
679  static uint8_t temp[MKV5X_ETH_RX_BUFFER_SIZE];
680  error_t error;
681  size_t n;
682  NetRxAncillary ancillary;
683 
684  //Make sure the current buffer is available for reading
685  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
686  {
687  //The frame should not span multiple buffers
688  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
689  {
690  //Check whether an error occurred
691  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
693  {
694  //Retrieve the length of the frame
695  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
696  //Limit the number of data to read
698 
699  //Copy data from the receive buffer
700  osMemcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
701 
702  //Additional options can be passed to the stack along with the packet
703  ancillary = NET_DEFAULT_RX_ANCILLARY;
704 
705  //Pass the packet to the upper layer
706  nicProcessPacket(interface, temp, n, &ancillary);
707 
708  //Valid packet received
709  error = NO_ERROR;
710  }
711  else
712  {
713  //The received packet contains an error
714  error = ERROR_INVALID_PACKET;
715  }
716  }
717  else
718  {
719  //The packet is not valid
720  error = ERROR_INVALID_PACKET;
721  }
722 
723  //Clear BDU flag
724  rxBufferDesc[rxBufferIndex][4] = 0;
725 
726  //Check current index
727  if(rxBufferIndex < (MKV5X_ETH_RX_BUFFER_COUNT - 1))
728  {
729  //Give the ownership of the descriptor back to the DMA engine
730  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
731  //Point to the next buffer
732  rxBufferIndex++;
733  }
734  else
735  {
736  //Give the ownership of the descriptor back to the DMA engine
737  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
738  //Wrap around
739  rxBufferIndex = 0;
740  }
741 
742  //Instruct the DMA to poll the receive descriptor list
743  ENET->RDAR = ENET_RDAR_RDAR_MASK;
744  }
745  else
746  {
747  //No more data in the receive buffer
748  error = ERROR_BUFFER_EMPTY;
749  }
750 
751  //Return status code
752  return error;
753 }
754 
755 
756 /**
757  * @brief Configure MAC address filtering
758  * @param[in] interface Underlying network interface
759  * @return Error code
760  **/
761 
763 {
764  uint_t i;
765  uint_t k;
766  uint32_t crc;
767  uint32_t value;
768  uint32_t unicastHashTable[2];
769  uint32_t multicastHashTable[2];
770  MacFilterEntry *entry;
771 
772  //Debug message
773  TRACE_DEBUG("Updating MAC filter...\r\n");
774 
775  //Set the MAC address of the station (upper 16 bits)
776  value = interface->macAddr.b[5];
777  value |= (interface->macAddr.b[4] << 8);
778  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
779 
780  //Set the MAC address of the station (lower 32 bits)
781  value = interface->macAddr.b[3];
782  value |= (interface->macAddr.b[2] << 8);
783  value |= (interface->macAddr.b[1] << 16);
784  value |= (interface->macAddr.b[0] << 24);
785  ENET->PALR = ENET_PALR_PADDR1(value);
786 
787  //Clear hash table (unicast address filtering)
788  unicastHashTable[0] = 0;
789  unicastHashTable[1] = 0;
790 
791  //Clear hash table (multicast address filtering)
792  multicastHashTable[0] = 0;
793  multicastHashTable[1] = 0;
794 
795  //The MAC address filter contains the list of MAC addresses to accept
796  //when receiving an Ethernet frame
797  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
798  {
799  //Point to the current entry
800  entry = &interface->macAddrFilter[i];
801 
802  //Valid entry?
803  if(entry->refCount > 0)
804  {
805  //Compute CRC over the current MAC address
806  crc = mkv5xEthCalcCrc(&entry->addr, sizeof(MacAddr));
807 
808  //The upper 6 bits in the CRC register are used to index the
809  //contents of the hash table
810  k = (crc >> 26) & 0x3F;
811 
812  //Multicast address?
813  if(macIsMulticastAddr(&entry->addr))
814  {
815  //Update the multicast hash table
816  multicastHashTable[k / 32] |= (1 << (k % 32));
817  }
818  else
819  {
820  //Update the unicast hash table
821  unicastHashTable[k / 32] |= (1 << (k % 32));
822  }
823  }
824  }
825 
826  //Write the hash table (unicast address filtering)
827  ENET->IALR = unicastHashTable[0];
828  ENET->IAUR = unicastHashTable[1];
829 
830  //Write the hash table (multicast address filtering)
831  ENET->GALR = multicastHashTable[0];
832  ENET->GAUR = multicastHashTable[1];
833 
834  //Debug message
835  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
836  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
837  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
838  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
839 
840  //Successful processing
841  return NO_ERROR;
842 }
843 
844 
845 /**
846  * @brief Adjust MAC configuration parameters for proper operation
847  * @param[in] interface Underlying network interface
848  * @return Error code
849  **/
850 
852 {
853  //Disable Ethernet MAC while modifying configuration registers
854  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
855 
856  //10BASE-T or 100BASE-TX operation mode?
857  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
858  {
859  //100 Mbps operation
860  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
861  }
862  else
863  {
864  //10 Mbps operation
865  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
866  }
867 
868  //Half-duplex or full-duplex mode?
869  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
870  {
871  //Full-duplex mode
872  ENET->TCR |= ENET_TCR_FDEN_MASK;
873  //Receive path operates independently of transmit
874  ENET->RCR &= ~ENET_RCR_DRT_MASK;
875  }
876  else
877  {
878  //Half-duplex mode
879  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
880  //Disable reception of frames while transmitting
881  ENET->RCR |= ENET_RCR_DRT_MASK;
882  }
883 
884  //Reset buffer descriptors
885  mkv5xEthInitBufferDesc(interface);
886 
887  //Re-enable Ethernet MAC
888  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
889  //Instruct the DMA to poll the receive descriptor list
890  ENET->RDAR = ENET_RDAR_RDAR_MASK;
891 
892  //Successful processing
893  return NO_ERROR;
894 }
895 
896 
897 /**
898  * @brief Write PHY register
899  * @param[in] opcode Access type (2 bits)
900  * @param[in] phyAddr PHY address (5 bits)
901  * @param[in] regAddr Register address (5 bits)
902  * @param[in] data Register value
903  **/
904 
905 void mkv5xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
906  uint8_t regAddr, uint16_t data)
907 {
908  uint32_t temp;
909 
910  //Valid opcode?
911  if(opcode == SMI_OPCODE_WRITE)
912  {
913  //Set up a write operation
914  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
915  //PHY address
916  temp |= ENET_MMFR_PA(phyAddr);
917  //Register address
918  temp |= ENET_MMFR_RA(regAddr);
919  //Register value
920  temp |= ENET_MMFR_DATA(data);
921 
922  //Clear MII interrupt flag
923  ENET->EIR = ENET_EIR_MII_MASK;
924  //Start a write operation
925  ENET->MMFR = temp;
926 
927  //Wait for the write to complete
928  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
929  {
930  }
931  }
932  else
933  {
934  //The MAC peripheral only supports standard Clause 22 opcodes
935  }
936 }
937 
938 
939 /**
940  * @brief Read PHY register
941  * @param[in] opcode Access type (2 bits)
942  * @param[in] phyAddr PHY address (5 bits)
943  * @param[in] regAddr Register address (5 bits)
944  * @return Register value
945  **/
946 
947 uint16_t mkv5xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
948  uint8_t regAddr)
949 {
950  uint16_t data;
951  uint32_t temp;
952 
953  //Valid opcode?
954  if(opcode == SMI_OPCODE_READ)
955  {
956  //Set up a read operation
957  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
958  //PHY address
959  temp |= ENET_MMFR_PA(phyAddr);
960  //Register address
961  temp |= ENET_MMFR_RA(regAddr);
962 
963  //Clear MII interrupt flag
964  ENET->EIR = ENET_EIR_MII_MASK;
965  //Start a read operation
966  ENET->MMFR = temp;
967 
968  //Wait for the read to complete
969  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
970  {
971  }
972 
973  //Get register value
974  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
975  }
976  else
977  {
978  //The MAC peripheral only supports standard Clause 22 opcodes
979  data = 0;
980  }
981 
982  //Return the value of the PHY register
983  return data;
984 }
985 
986 
987 /**
988  * @brief CRC calculation
989  * @param[in] data Pointer to the data over which to calculate the CRC
990  * @param[in] length Number of bytes to process
991  * @return Resulting CRC value
992  **/
993 
994 uint32_t mkv5xEthCalcCrc(const void *data, size_t length)
995 {
996  uint_t i;
997  uint_t j;
998  uint32_t crc;
999  const uint8_t *p;
1000 
1001  //Point to the data over which to calculate the CRC
1002  p = (uint8_t *) data;
1003  //CRC preset value
1004  crc = 0xFFFFFFFF;
1005 
1006  //Loop through data
1007  for(i = 0; i < length; i++)
1008  {
1009  //Update CRC value
1010  crc ^= p[i];
1011  //The message is processed bit by bit
1012  for(j = 0; j < 8; j++)
1013  {
1014  if((crc & 0x01) != 0)
1015  {
1016  crc = (crc >> 1) ^ 0xEDB88320;
1017  }
1018  else
1019  {
1020  crc = crc >> 1;
1021  }
1022  }
1023  }
1024 
1025  //Return CRC value
1026  return crc;
1027 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
void mkv5xEthEnableIrq(NetInterface *interface)
Enable interrupts.
void mkv5xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t mkv5xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
void mkv5xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
#define ENET_TBD0_L
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void ENET_Receive_IRQHandler(void)
Ethernet MAC receive interrupt.
#define ENET_RBD0_DATA_LENGTH
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
__start_packed struct @5 MacAddr
MAC address.
const NicDriver mkv5xEthDriver
Kinetis KV5x Ethernet MAC driver.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define ENET_TBD0_DATA_LENGTH
#define MKV5X_ETH_TX_BUFFER_COUNT
#define ENET_TBD0_W
#define ENET_TBD0_TC
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:65
error_t mkv5xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ENET_RBD0_L
error_t mkv5xEthInit(NetInterface *interface)
Kinetis KV5x Ethernet MAC initialization.
#define FALSE
Definition: os_port.h:46
#define MKV5X_ETH_IRQ_GROUP_PRIORITY
#define osMemcpy(dest, src, length)
Definition: os_port.h:134
#define MPU_CESR_VLD_MASK
error_t
Error codes.
Definition: error.h:42
uint8_t value[]
Definition: tcp.h:332
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
#define MKV5X_ETH_IRQ_SUB_PRIORITY
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define MKV5X_ETH_RX_BUFFER_SIZE
#define ENET_RBD0_W
#define ENET_RBD0_TR
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void mkv5xEthInitGpio(NetInterface *interface)
#define MKV5X_ETH_TX_BUFFER_SIZE
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
void ENET_Transmit_IRQHandler(void)
Ethernet MAC transmit interrupt.
uint32_t mkv5xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_LG
#define TRACE_DEBUG(...)
Definition: debug.h:107
error_t mkv5xEthReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t regAddr
#define ENET_RBD0_CR
void mkv5xEthTick(NetInterface *interface)
Kinetis KV5x Ethernet MAC timer handler.
#define ENET_RBD0_OV
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
void ENET_Error_IRQHandler(void)
Ethernet MAC error interrupt.
NXP Kinetis KV5x Ethernet MAC driver.
#define osEnterIsr()
#define MPU
#define ENET_TBD0_R
#define ENET_TBD2_INT
void mkv5xEthEventHandler(NetInterface *interface)
Kinetis KV5x Ethernet MAC event handler.
#define ENET_RBD0_E
error_t mkv5xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MKV5X_ETH_RX_BUFFER_COUNT
unsigned int uint_t
Definition: compiler_port.h:45
#define osMemset(p, value, length)
Definition: os_port.h:128
TCP/IP stack core.
error_t mkv5xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
NIC driver.
Definition: nic.h:257
#define ENET_RBD0_NO
#define ENET_RBD2_INT
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
Ethernet interface.
Definition: nic.h:82
void mkv5xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MKV5X_ETH_IRQ_PRIORITY_GROUPING