mpc5748_eth1_driver.c
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1 /**
2  * @file mpc5748_eth1_driver.c
3  * @brief NXP MPC5748 Ethernet MAC driver (ENET0 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "device_registers.h"
36 #include "interrupt_manager.h"
37 #include "core/net.h"
38 #include "drivers/mac/mpc5748_eth1_driver.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //TX buffer
45 static uint8_t txBuffer[MPC5748_ETH1_TX_BUFFER_COUNT][MPC5748_ETH1_TX_BUFFER_SIZE]
46  __attribute__((aligned(64)));
47 //RX buffer
48 static uint8_t rxBuffer[MPC5748_ETH1_RX_BUFFER_COUNT][MPC5748_ETH1_RX_BUFFER_SIZE]
49  __attribute__((aligned(64)));
50 //TX buffer descriptors
51 static uint32_t txBufferDesc[MPC5748_ETH1_TX_BUFFER_COUNT][8]
52  __attribute__((aligned(64)));
53 //RX buffer descriptors
54 static uint32_t rxBufferDesc[MPC5748_ETH1_RX_BUFFER_COUNT][8]
55  __attribute__((aligned(64)));
56 
57 //TX buffer index
58 static uint_t txBufferIndex;
59 //RX buffer index
60 static uint_t rxBufferIndex;
61 
62 
63 /**
64  * @brief MPC5748 Ethernet MAC driver (ENET0 instance)
65  **/
66 
67 const NicDriver mpc5748Eth1Driver =
68 {
69  NIC_TYPE_ETHERNET,
70  ETH_MTU,
71  mpc5748Eth1Init,
72  mpc5748Eth1Tick,
73  mpc5748Eth1EnableIrq,
74  mpc5748Eth1DisableIrq,
75  mpc5748Eth1EventHandler,
76  mpc5748Eth1SendPacket,
77  mpc5748Eth1UpdateMacAddrFilter,
78  mpc5748Eth1UpdateMacConfig,
79  mpc5748Eth1WritePhyReg,
80  mpc5748Eth1ReadPhyReg,
81  TRUE,
82  TRUE,
83  TRUE,
84  FALSE
85 };
86 
87 
88 /**
89  * @brief MPC5748 Ethernet MAC initialization
90  * @param[in] interface Underlying network interface
91  * @return Error code
92  **/
93 
94 error_t mpc5748Eth1Init(NetInterface *interface)
95 {
96  error_t error;
97  uint32_t value;
98 
99  //Debug message
100  TRACE_INFO("Initializing MPC5748 Ethernet MAC (ENET0)...\r\n");
101 
102  //Save underlying network interface
103  nicDriverInterface = interface;
104 
105  //GPIO configuration
106  mpc5748Eth1InitGpio(interface);
107 
108  //Reset ENET module
109  ENET_0->ECR = ENET_ECR_RESET_MASK;
110  //Wait for the reset to complete
111  while((ENET_0->ECR & ENET_ECR_RESET_MASK) != 0)
112  {
113  }
114 
115 #if defined(USE_DEVKIT_MPC5748G)
116  //Configure MAC for RMII operation
117  ENET_0->RCR = ENET_RCR_MAX_FL(MPC5748_ETH1_RX_BUFFER_SIZE) |
118  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
119 #else
120  //Configure MAC for MII mode
121  ENET_0->RCR = ENET_RCR_MAX_FL(MPC5748_ETH1_RX_BUFFER_SIZE) |
122  ENET_RCR_MII_MODE_MASK;
123 #endif
124 
125  //Transmit control register
126  ENET_0->TCR = 0;
127  //Configure MDC clock frequency
128  ENET_0->MSCR = ENET_MSCR_MII_SPEED(19);
129 
130  //Valid Ethernet PHY or switch driver?
131  if(interface->phyDriver != NULL)
132  {
133  //Ethernet PHY initialization
134  error = interface->phyDriver->init(interface);
135  }
136  else if(interface->switchDriver != NULL)
137  {
138  //Ethernet switch initialization
139  error = interface->switchDriver->init(interface);
140  }
141  else
142  {
143  //The interface is not properly configured
144  error = ERROR_FAILURE;
145  }
146 
147  //Any error to report?
148  if(error)
149  {
150  return error;
151  }
152 
153  //Set the MAC address of the station (upper 16 bits)
154  value = interface->macAddr.b[5];
155  value |= (interface->macAddr.b[4] << 8);
156  ENET_0->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
157 
158  //Set the MAC address of the station (lower 32 bits)
159  value = interface->macAddr.b[3];
160  value |= (interface->macAddr.b[2] << 8);
161  value |= (interface->macAddr.b[1] << 16);
162  value |= (interface->macAddr.b[0] << 24);
163  ENET_0->PALR = ENET_PALR_PADDR1(value);
164 
165  //Hash table for unicast address filtering
166  ENET_0->IALR = 0;
167  ENET_0->IAUR = 0;
168  //Hash table for multicast address filtering
169  ENET_0->GALR = 0;
170  ENET_0->GAUR = 0;
171 
172  //Disable transmit accelerator functions
173  ENET_0->TACC = 0;
174  //Disable receive accelerator functions
175  ENET_0->RACC = 0;
176 
177  //Use enhanced buffer descriptors
178  ENET_0->ECR = ENET_ECR_EN1588_MASK;
179 
180  //Reset statistics counters
181  ENET_0->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
182  ENET_0->MIBC = 0;
183 
184  //Initialize buffer descriptors
185  mpc5748Eth1InitBufferDesc(interface);
186 
187  //Clear any pending interrupts
188  ENET_0->EIR = 0xFFFFFFFF;
189  //Enable desired interrupts
190  ENET_0->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
191 
192  //Configure ENET transmit interrupt priority
193  INT_SYS_SetPriority(ENET0_GROUP2_IRQn, MPC5748_ETH1_IRQ_PRIORITY);
194  //Configure ENET receive interrupt priority
195  INT_SYS_SetPriority(ENET0_GROUP1_IRQn, MPC5748_ETH1_IRQ_PRIORITY);
196  //Configure ENET error interrupt priority
197  INT_SYS_SetPriority(ENET0_GROUP0_IRQn, MPC5748_ETH1_IRQ_PRIORITY);
198 
199  //Enable Ethernet MAC
200  ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
201  //Instruct the DMA to poll the receive descriptor list
202  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
203 
204  //Accept any packets from the upper layer
205  osSetEvent(&interface->nicTxEvent);
206 
207  //Successful initialization
208  return NO_ERROR;
209 }
210 
211 
212 /**
213  * @brief GPIO configuration
214  * @param[in] interface Underlying network interface
215  **/
216 
217 __weak_func void mpc5748Eth1InitGpio(NetInterface *interface)
218 {
219 //DEVKIT-MPC5748G evaluation board?
220 #if defined(USE_DEVKIT_MPC5748G)
221  //Configure MII_RMII_0_MDIO (PF14)
222  SIUL2->MSCR[94] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
223  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_PUS_MASK |
224  SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_SSS(4);
225  SIUL2->IMCR[450] = SIUL2_IMCR_SSS(1);
226 
227  //Configure MII_RMII_0_MDC (PG0)
228  SIUL2->MSCR[96] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
229  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
230 
231  //Configure MII_RMII_0_TX_CLK (PG1)
232  SIUL2->MSCR[97] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
233  SIUL2->IMCR[449] = SIUL2_IMCR_SSS(1);
234 
235  //Configure MII_RMII_0_TX_EN (PH2)
236  SIUL2->MSCR[114] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
237  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
238 
239  //Configure MII_RMII_0_TXD0 (PH1)
240  SIUL2->MSCR[113] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
241  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
242 
243  //Configure MII_RMII_0_TXD1 (PH0)
244  SIUL2->MSCR[112] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
245  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
246 
247  //Configure MII_RMII_0_RX_DV (PF15)
248  SIUL2->MSCR[95] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
249  SIUL2->IMCR[457] = SIUL2_IMCR_SSS(1);
250 
251  //Configure MII_RMII_0_RX_ER (PA11)
252  SIUL2->MSCR[11] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
253  SIUL2->IMCR[455] = SIUL2_IMCR_SSS(1);
254 
255  //Configure MII_RMII_0_RXD0 (PA9)
256  SIUL2->MSCR[9] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
257  SIUL2->IMCR[451] = SIUL2_IMCR_SSS(1);
258 
259  //Configure MII_RMII_0_RXD1 (PA8)
260  SIUL2->MSCR[8] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
261  SIUL2->IMCR[452] = SIUL2_IMCR_SSS(1);
262 
263 //MPC5748G-LCEVB evaluation board?
264 #elif defined(USE_MPC5748G_LCEVB)
265  //Configure MII_RMII_0_MDIO (PF14)
266  SIUL2->MSCR[94] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
267  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_PUS_MASK |
268  SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_SSS(4);
269  SIUL2->IMCR[450] = SIUL2_IMCR_SSS(1);
270 
271  //Configure MII_RMII_0_MDC (PG0)
272  SIUL2->MSCR[96] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
273  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
274 
275  //Configure MII_RMII_0_TX_CLK (PG1)
276  SIUL2->MSCR[97] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
277  SIUL2->IMCR[449] = SIUL2_IMCR_SSS(1);
278 
279  //Configure MII_RMII_0_TX_EN (PH2)
280  SIUL2->MSCR[114] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
281  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
282 
283  //Configure MII_RMII_0_TXD0 (PH1)
284  SIUL2->MSCR[113] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
285  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
286 
287  //Configure MII_RMII_0_TXD1 (PH0)
288  SIUL2->MSCR[112] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
289  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
290 
291  //Configure MII_0_TXD2 (PG12)
292  SIUL2->MSCR[108] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
293  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
294 
295  //Configure MII_0_TXD3 (PG13)
296  SIUL2->MSCR[109] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
297  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
298 
299  //Configure MII_0_RX_CLK (PA3)
300  SIUL2->MSCR[3] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
301  SIUL2->IMCR[448] = SIUL2_IMCR_SSS(1);
302 
303  //Configure MII_RMII_0_RX_DV (PF15)
304  SIUL2->MSCR[95] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
305  SIUL2->IMCR[457] = SIUL2_IMCR_SSS(1);
306 
307  //Configure MII_RMII_0_RX_ER (PA11)
308  SIUL2->MSCR[11] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
309  SIUL2->IMCR[455] = SIUL2_IMCR_SSS(1);
310 
311  //Configure MII_0_COL (PA10)
312  SIUL2->MSCR[10] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
313  SIUL2->IMCR[456] = SIUL2_IMCR_SSS(1);
314 
315  //Configure MII_RMII_0_RXD0 (PA9)
316  SIUL2->MSCR[9] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
317  SIUL2->IMCR[451] = SIUL2_IMCR_SSS(1);
318 
319  //Configure MII_RMII_0_RXD1 (PA8)
320  SIUL2->MSCR[8] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
321  SIUL2->IMCR[452] = SIUL2_IMCR_SSS(1);
322 
323  //Configure MII_0_RXD2 (PA7)
324  SIUL2->MSCR[7] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
325  SIUL2->IMCR[453] = SIUL2_IMCR_SSS(1);
326 
327  //Configure MII_0_RXD3 (PE13)
328  SIUL2->MSCR[77] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
329  SIUL2->IMCR[454] = SIUL2_IMCR_SSS(1);
330 
331  //Configure PHY reset pin (PI11)
332  SIUL2->MSCR[139] = SIUL2_MSCR_OBE_MASK | SIUL2_MSCR_SMC_MASK;
333 
334  //Reset PHY transceiver
335  SIUL2->GPDO[139] = 0;
336  sleep(10);
337  SIUL2->GPDO[139] = 1;
338  sleep(10);
339 
340 //MPC5748G-GW-RDB evaluation board?
341 #elif defined(USE_MPC5748G_GW_RDB)
342  //Configure MII_RMII_0_MDIO (PF14)
343  SIUL2->MSCR[94] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
344  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_PUS_MASK |
345  SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_SSS(4);
346  SIUL2->IMCR[450] = SIUL2_IMCR_SSS(1);
347 
348  //Configure MII_RMII_0_MDC (PG0)
349  SIUL2->MSCR[96] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
350  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
351 
352  //Configure MII_RMII_0_TX_CLK (PG1)
353  SIUL2->MSCR[97] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
354  SIUL2->IMCR[449] = SIUL2_IMCR_SSS(1);
355 
356  //Configure MII_RMII_0_TX_EN (PH2)
357  SIUL2->MSCR[114] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
358  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
359 
360  //Configure MII_RMII_0_TXD0 (PH1)
361  SIUL2->MSCR[113] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
362  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
363 
364  //Configure MII_RMII_0_TXD1 (PH0)
365  SIUL2->MSCR[112] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
366  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
367 
368  //Configure MII_0_TXD2 (PG12)
369  SIUL2->MSCR[108] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
370  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
371 
372  //Configure MII_0_TXD3 (PG13)
373  SIUL2->MSCR[109] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
374  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
375 
376  //Configure MII_0_RX_CLK (PA3)
377  SIUL2->MSCR[3] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
378  SIUL2->IMCR[448] = SIUL2_IMCR_SSS(1);
379 
380  //Configure MII_RMII_0_RX_DV (PF15)
381  SIUL2->MSCR[95] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
382  SIUL2->IMCR[457] = SIUL2_IMCR_SSS(1);
383 
384  //Configure MII_RMII_0_RXD0 (PA9)
385  SIUL2->MSCR[9] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
386  SIUL2->IMCR[451] = SIUL2_IMCR_SSS(1);
387 
388  //Configure MII_RMII_0_RXD1 (PA8)
389  SIUL2->MSCR[8] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
390  SIUL2->IMCR[452] = SIUL2_IMCR_SSS(1);
391 
392  //Configure MII_0_RXD2 (PA7)
393  SIUL2->MSCR[7] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
394  SIUL2->IMCR[453] = SIUL2_IMCR_SSS(1);
395 
396  //Configure MII_0_RXD3 (PE13)
397  SIUL2->MSCR[77] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
398  SIUL2->IMCR[454] = SIUL2_IMCR_SSS(1);
399 
400  //Configure switch reset pin (PB15)
401  SIUL2->MSCR[31] = SIUL2_MSCR_OBE_MASK | SIUL2_MSCR_SMC_MASK;
402 
403  //Reset switch
404  SIUL2->GPDO[31] = 0;
405  sleep(10);
406  SIUL2->GPDO[31] = 1;
407  sleep(10);
408 
409 //SJA1105SMBEVM evaluation board?
410 #elif defined(USE_SJA1105SMBEVM)
411  //Configure MII_RMII_0_MDIO (PF14)
412  SIUL2->MSCR[94] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
413  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_PUS_MASK |
414  SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_SSS(4);
415  SIUL2->IMCR[450] = SIUL2_IMCR_SSS(1);
416 
417  //Configure MII_RMII_0_MDC (PG0)
418  SIUL2->MSCR[96] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
419  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
420 
421  //Configure MII_RMII_0_TX_CLK (PG1)
422  SIUL2->MSCR[97] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
423  SIUL2->IMCR[449] = SIUL2_IMCR_SSS(1);
424 
425  //Configure MII_RMII_0_TX_EN (PH2)
426  SIUL2->MSCR[114] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
427  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
428 
429  //Configure MII_RMII_0_TXD0 (PH1)
430  SIUL2->MSCR[113] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
431  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
432 
433  //Configure MII_RMII_0_TXD1 (PH0)
434  SIUL2->MSCR[112] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
435  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
436 
437  //Configure MII_0_TXD2 (PG12)
438  SIUL2->MSCR[108] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
439  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
440 
441  //Configure MII_0_TXD3 (PG13)
442  SIUL2->MSCR[109] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
443  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
444 
445  //Configure MII_0_RX_CLK (PA3)
446  SIUL2->MSCR[3] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
447  SIUL2->IMCR[448] = SIUL2_IMCR_SSS(1);
448 
449  //Configure MII_RMII_0_RX_DV (PF15)
450  SIUL2->MSCR[95] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
451  SIUL2->IMCR[457] = SIUL2_IMCR_SSS(1);
452 
453  //Configure MII_RMII_0_RXD0 (PA9)
454  SIUL2->MSCR[9] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
455  SIUL2->IMCR[451] = SIUL2_IMCR_SSS(1);
456 
457  //Configure MII_RMII_0_RXD1 (PA8)
458  SIUL2->MSCR[8] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
459  SIUL2->IMCR[452] = SIUL2_IMCR_SSS(1);
460 
461  //Configure MII_0_RXD2 (PA7)
462  SIUL2->MSCR[7] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
463  SIUL2->IMCR[453] = SIUL2_IMCR_SSS(1);
464 
465  //Configure MII_0_RXD3 (PE13)
466  SIUL2->MSCR[77] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
467  SIUL2->IMCR[454] = SIUL2_IMCR_SSS(1);
468 #endif
469 }
470 
471 
472 /**
473  * @brief Initialize buffer descriptors
474  * @param[in] interface Underlying network interface
475  **/
476 
477 void mpc5748Eth1InitBufferDesc(NetInterface *interface)
478 {
479  uint_t i;
480  uint32_t address;
481 
482  //Clear TX and RX buffer descriptors
483  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
484  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
485 
486  //Initialize TX buffer descriptors
487  for(i = 0; i < MPC5748_ETH1_TX_BUFFER_COUNT; i++)
488  {
489  //Calculate the address of the current TX buffer
490  address = (uint32_t) txBuffer[i];
491  //Transmit buffer address
492  txBufferDesc[i][1] = address;
493  //Generate interrupts
494  txBufferDesc[i][2] = ENET_TBD2_INT;
495  }
496 
497  //Mark the last descriptor entry with the wrap flag
498  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
499  //Initialize TX buffer index
500  txBufferIndex = 0;
501 
502  //Initialize RX buffer descriptors
503  for(i = 0; i < MPC5748_ETH1_RX_BUFFER_COUNT; i++)
504  {
505  //Calculate the address of the current RX buffer
506  address = (uint32_t) rxBuffer[i];
507  //The descriptor is initially owned by the DMA
508  rxBufferDesc[i][0] = ENET_RBD0_E;
509  //Receive buffer address
510  rxBufferDesc[i][1] = address;
511  //Generate interrupts
512  rxBufferDesc[i][2] = ENET_RBD2_INT;
513  }
514 
515  //Mark the last descriptor entry with the wrap flag
516  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
517  //Initialize RX buffer index
518  rxBufferIndex = 0;
519 
520  //Start location of the TX descriptor list
521  ENET_0->TDSR = (uint32_t) txBufferDesc;
522  //Start location of the RX descriptor list
523  ENET_0->RDSR = (uint32_t) rxBufferDesc;
524  //Maximum receive buffer size
525  ENET_0->MRBR = MPC5748_ETH1_RX_BUFFER_SIZE;
526 }
527 
528 
529 /**
530  * @brief MPC5748 Ethernet MAC timer handler
531  *
532  * This routine is periodically called by the TCP/IP stack to handle periodic
533  * operations such as polling the link state
534  *
535  * @param[in] interface Underlying network interface
536  **/
537 
538 void mpc5748Eth1Tick(NetInterface *interface)
539 {
540  //Valid Ethernet PHY or switch driver?
541  if(interface->phyDriver != NULL)
542  {
543  //Handle periodic operations
544  interface->phyDriver->tick(interface);
545  }
546  else if(interface->switchDriver != NULL)
547  {
548  //Handle periodic operations
549  interface->switchDriver->tick(interface);
550  }
551  else
552  {
553  //Just for sanity
554  }
555 }
556 
557 
558 /**
559  * @brief Enable interrupts
560  * @param[in] interface Underlying network interface
561  **/
562 
563 void mpc5748Eth1EnableIrq(NetInterface *interface)
564 {
565  //Enable Ethernet MAC interrupts
566  INT_SYS_EnableIRQ(ENET0_GROUP2_IRQn);
567  INT_SYS_EnableIRQ(ENET0_GROUP1_IRQn);
568  INT_SYS_EnableIRQ(ENET0_GROUP0_IRQn);
569 
570  //Valid Ethernet PHY or switch driver?
571  if(interface->phyDriver != NULL)
572  {
573  //Enable Ethernet PHY interrupts
574  interface->phyDriver->enableIrq(interface);
575  }
576  else if(interface->switchDriver != NULL)
577  {
578  //Enable Ethernet switch interrupts
579  interface->switchDriver->enableIrq(interface);
580  }
581  else
582  {
583  //Just for sanity
584  }
585 }
586 
587 
588 /**
589  * @brief Disable interrupts
590  * @param[in] interface Underlying network interface
591  **/
592 
593 void mpc5748Eth1DisableIrq(NetInterface *interface)
594 {
595  //Disable Ethernet MAC interrupts
596  INT_SYS_DisableIRQ(ENET0_GROUP2_IRQn);
597  INT_SYS_DisableIRQ(ENET0_GROUP1_IRQn);
598  INT_SYS_DisableIRQ(ENET0_GROUP0_IRQn);
599 
600  //Valid Ethernet PHY or switch driver?
601  if(interface->phyDriver != NULL)
602  {
603  //Disable Ethernet PHY interrupts
604  interface->phyDriver->disableIrq(interface);
605  }
606  else if(interface->switchDriver != NULL)
607  {
608  //Disable Ethernet switch interrupts
609  interface->switchDriver->disableIrq(interface);
610  }
611  else
612  {
613  //Just for sanity
614  }
615 }
616 
617 
618 /**
619  * @brief Ethernet MAC transmit interrupt
620  **/
621 
622 void ENET0_Tx_IRQHandler(void)
623 {
624  bool_t flag;
625 
626  //Interrupt service routine prologue
627  osEnterIsr();
628 
629  //This flag will be set if a higher priority task must be woken
630  flag = FALSE;
631 
632  //Packet transmitted?
633  if((ENET_0->EIR & ENET_EIR_TXF_MASK) != 0)
634  {
635  //Clear TXF interrupt flag
636  ENET_0->EIR = ENET_EIR_TXF_MASK;
637 
638  //Check whether the TX buffer is available for writing
639  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
640  {
641  //Notify the TCP/IP stack that the transmitter is ready to send
642  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
643  }
644 
645  //Instruct the DMA to poll the transmit descriptor list
646  ENET_0->TDAR = ENET_TDAR_TDAR_MASK;
647  }
648 
649  //Interrupt service routine epilogue
650  osExitIsr(flag);
651 }
652 
653 
654 /**
655  * @brief Ethernet MAC receive interrupt
656  **/
657 
658 void ENET0_Rx_IRQHandler(void)
659 {
660  bool_t flag;
661 
662  //Interrupt service routine prologue
663  osEnterIsr();
664 
665  //This flag will be set if a higher priority task must be woken
666  flag = FALSE;
667 
668  //Packet received?
669  if((ENET_0->EIR & ENET_EIR_RXF_MASK) != 0)
670  {
671  //Disable RXF interrupt
672  ENET_0->EIMR &= ~ENET_EIMR_RXF_MASK;
673 
674  //Set event flag
675  nicDriverInterface->nicEvent = TRUE;
676  //Notify the TCP/IP stack of the event
677  flag = osSetEventFromIsr(&netEvent);
678  }
679 
680  //Interrupt service routine epilogue
681  osExitIsr(flag);
682 }
683 
684 
685 /**
686  * @brief Ethernet MAC error interrupt
687  **/
688 
689 void ENET0_Err_IRQHandler(void)
690 {
691  bool_t flag;
692 
693  //Interrupt service routine prologue
694  osEnterIsr();
695 
696  //This flag will be set if a higher priority task must be woken
697  flag = FALSE;
698 
699  //System bus error?
700  if((ENET_0->EIR & ENET_EIR_EBERR_MASK) != 0)
701  {
702  //Disable EBERR interrupt
703  ENET_0->EIMR &= ~ENET_EIMR_EBERR_MASK;
704 
705  //Set event flag
706  nicDriverInterface->nicEvent = TRUE;
707  //Notify the TCP/IP stack of the event
708  flag |= osSetEventFromIsr(&netEvent);
709  }
710 
711  //Interrupt service routine epilogue
712  osExitIsr(flag);
713 }
714 
715 
716 /**
717  * @brief MPC5748 Ethernet MAC event handler
718  * @param[in] interface Underlying network interface
719  **/
720 
721 void mpc5748Eth1EventHandler(NetInterface *interface)
722 {
723  error_t error;
724  uint32_t status;
725 
726  //Read interrupt event register
727  status = ENET_0->EIR;
728 
729  //Packet received?
730  if((status & ENET_EIR_RXF_MASK) != 0)
731  {
732  //Clear RXF interrupt flag
733  ENET_0->EIR = ENET_EIR_RXF_MASK;
734 
735  //Process all pending packets
736  do
737  {
738  //Read incoming packet
739  error = mpc5748Eth1ReceivePacket(interface);
740 
741  //No more data in the receive buffer?
742  } while(error != ERROR_BUFFER_EMPTY);
743  }
744 
745  //System bus error?
746  if((status & ENET_EIR_EBERR_MASK) != 0)
747  {
748  //Clear EBERR interrupt flag
749  ENET_0->EIR = ENET_EIR_EBERR_MASK;
750 
751  //Disable Ethernet MAC
752  ENET_0->ECR &= ~ENET_ECR_ETHEREN_MASK;
753  //Reset buffer descriptors
754  mpc5748Eth1InitBufferDesc(interface);
755  //Resume normal operation
756  ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
757  //Instruct the DMA to poll the receive descriptor list
758  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
759  }
760 
761  //Re-enable Ethernet MAC interrupts
762  ENET_0->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
763 }
764 
765 
766 /**
767  * @brief Send a packet
768  * @param[in] interface Underlying network interface
769  * @param[in] buffer Multi-part buffer containing the data to send
770  * @param[in] offset Offset to the first data byte
771  * @param[in] ancillary Additional options passed to the stack along with
772  * the packet
773  * @return Error code
774  **/
775 
776 error_t mpc5748Eth1SendPacket(NetInterface *interface,
777  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
778 {
779  size_t length;
780 
781  //Retrieve the length of the packet
782  length = netBufferGetLength(buffer) - offset;
783 
784  //Check the frame length
785  if(length > MPC5748_ETH1_TX_BUFFER_SIZE)
786  {
787  //The transmitter can accept another packet
788  osSetEvent(&interface->nicTxEvent);
789  //Report an error
790  return ERROR_INVALID_LENGTH;
791  }
792 
793  //Make sure the current buffer is available for writing
794  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
795  {
796  return ERROR_FAILURE;
797  }
798 
799  //Copy user data to the transmit buffer
800  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
801 
802  //Clear BDU flag
803  txBufferDesc[txBufferIndex][4] = 0;
804 
805  //Check current index
806  if(txBufferIndex < (MPC5748_ETH1_TX_BUFFER_COUNT - 1))
807  {
808  //Give the ownership of the descriptor to the DMA engine
809  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
810  ENET_TBD0_TC | (length & ENET_TBD0_DATA_LENGTH);
811 
812  //Point to the next buffer
813  txBufferIndex++;
814  }
815  else
816  {
817  //Give the ownership of the descriptor to the DMA engine
818  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
819  ENET_TBD0_L | ENET_TBD0_TC | (length & ENET_TBD0_DATA_LENGTH);
820 
821  //Wrap around
822  txBufferIndex = 0;
823  }
824 
825  //Instruct the DMA to poll the transmit descriptor list
826  ENET_0->TDAR = ENET_TDAR_TDAR_MASK;
827 
828  //Check whether the next buffer is available for writing
829  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
830  {
831  //The transmitter can accept another packet
832  osSetEvent(&interface->nicTxEvent);
833  }
834 
835  //Successful processing
836  return NO_ERROR;
837 }
838 
839 
840 /**
841  * @brief Receive a packet
842  * @param[in] interface Underlying network interface
843  * @return Error code
844  **/
845 
846 error_t mpc5748Eth1ReceivePacket(NetInterface *interface)
847 {
848  error_t error;
849  size_t n;
850  NetRxAncillary ancillary;
851 
852  //Current buffer available for reading?
853  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
854  {
855  //The frame should not span multiple buffers
856  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
857  {
858  //Check whether an error occurred
859  if((rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG | ENET_RBD0_NO |
860  ENET_RBD0_CR | ENET_RBD0_OV | ENET_RBD0_TR)) == 0)
861  {
862  //Retrieve the length of the frame
863  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
864  //Limit the number of data to read
865  n = MIN(n, MPC5748_ETH1_RX_BUFFER_SIZE);
866 
867  //Additional options can be passed to the stack along with the packet
868  ancillary = NET_DEFAULT_RX_ANCILLARY;
869 
870  //Pass the packet to the upper layer
871  nicProcessPacket(interface, rxBuffer[rxBufferIndex], n, &ancillary);
872 
873  //Valid packet received
874  error = NO_ERROR;
875  }
876  else
877  {
878  //The received packet contains an error
879  error = ERROR_INVALID_PACKET;
880  }
881  }
882  else
883  {
884  //The packet is not valid
885  error = ERROR_INVALID_PACKET;
886  }
887 
888  //Clear BDU flag
889  rxBufferDesc[rxBufferIndex][4] = 0;
890 
891  //Check current index
892  if(rxBufferIndex < (MPC5748_ETH1_RX_BUFFER_COUNT - 1))
893  {
894  //Give the ownership of the descriptor back to the DMA engine
895  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
896  //Point to the next buffer
897  rxBufferIndex++;
898  }
899  else
900  {
901  //Give the ownership of the descriptor back to the DMA engine
902  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
903  //Wrap around
904  rxBufferIndex = 0;
905  }
906 
907  //Instruct the DMA to poll the receive descriptor list
908  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
909  }
910  else
911  {
912  //No more data in the receive buffer
913  error = ERROR_BUFFER_EMPTY;
914  }
915 
916  //Return status code
917  return error;
918 }
919 
920 
921 /**
922  * @brief Configure MAC address filtering
923  * @param[in] interface Underlying network interface
924  * @return Error code
925  **/
926 
927 error_t mpc5748Eth1UpdateMacAddrFilter(NetInterface *interface)
928 {
929  uint_t i;
930  uint_t k;
931  uint32_t crc;
932  uint32_t value;
933  uint32_t unicastHashTable[2];
934  uint32_t multicastHashTable[2];
935  MacFilterEntry *entry;
936 
937  //Debug message
938  TRACE_DEBUG("Updating MAC filter...\r\n");
939 
940  //Set the MAC address of the station (upper 16 bits)
941  value = interface->macAddr.b[5];
942  value |= (interface->macAddr.b[4] << 8);
943  ENET_0->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
944 
945  //Set the MAC address of the station (lower 32 bits)
946  value = interface->macAddr.b[3];
947  value |= (interface->macAddr.b[2] << 8);
948  value |= (interface->macAddr.b[1] << 16);
949  value |= (interface->macAddr.b[0] << 24);
950  ENET_0->PALR = ENET_PALR_PADDR1(value);
951 
952  //Clear hash table (unicast address filtering)
953  unicastHashTable[0] = 0;
954  unicastHashTable[1] = 0;
955 
956  //Clear hash table (multicast address filtering)
957  multicastHashTable[0] = 0;
958  multicastHashTable[1] = 0;
959 
960  //The MAC address filter contains the list of MAC addresses to accept
961  //when receiving an Ethernet frame
962  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
963  {
964  //Point to the current entry
965  entry = &interface->macAddrFilter[i];
966 
967  //Valid entry?
968  if(entry->refCount > 0)
969  {
970  //Compute CRC over the current MAC address
971  crc = mpc5748Eth1CalcCrc(&entry->addr, sizeof(MacAddr));
972 
973  //The upper 6 bits in the CRC register are used to index the
974  //contents of the hash table
975  k = (crc >> 26) & 0x3F;
976 
977  //Multicast address?
978  if(macIsMulticastAddr(&entry->addr))
979  {
980  //Update the multicast hash table
981  multicastHashTable[k / 32] |= (1 << (k % 32));
982  }
983  else
984  {
985  //Update the unicast hash table
986  unicastHashTable[k / 32] |= (1 << (k % 32));
987  }
988  }
989  }
990 
991  //Write the hash table (unicast address filtering)
992  ENET_0->IALR = unicastHashTable[0];
993  ENET_0->IAUR = unicastHashTable[1];
994 
995  //Write the hash table (multicast address filtering)
996  ENET_0->GALR = multicastHashTable[0];
997  ENET_0->GAUR = multicastHashTable[1];
998 
999  //Debug message
1000  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET_0->IALR);
1001  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET_0->IAUR);
1002  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET_0->GALR);
1003  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET_0->GAUR);
1004 
1005  //Successful processing
1006  return NO_ERROR;
1007 }
1008 
1009 
1010 /**
1011  * @brief Adjust MAC configuration parameters for proper operation
1012  * @param[in] interface Underlying network interface
1013  * @return Error code
1014  **/
1015 
1016 error_t mpc5748Eth1UpdateMacConfig(NetInterface *interface)
1017 {
1018  //Disable Ethernet MAC while modifying configuration registers
1019  ENET_0->ECR &= ~ENET_ECR_ETHEREN_MASK;
1020 
1021  //10BASE-T or 100BASE-TX operation mode?
1022  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
1023  {
1024  //100 Mbps operation
1025  ENET_0->RCR &= ~ENET_RCR_RMII_10T_MASK;
1026  }
1027  else
1028  {
1029  //10 Mbps operation
1030  ENET_0->RCR |= ENET_RCR_RMII_10T_MASK;
1031  }
1032 
1033  //Half-duplex or full-duplex mode?
1034  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
1035  {
1036  //Full-duplex mode
1037  ENET_0->TCR |= ENET_TCR_FDEN_MASK;
1038  //Receive path operates independently of transmit
1039  ENET_0->RCR &= ~ENET_RCR_DRT_MASK;
1040  }
1041  else
1042  {
1043  //Half-duplex mode
1044  ENET_0->TCR &= ~ENET_TCR_FDEN_MASK;
1045  //Disable reception of frames while transmitting
1046  ENET_0->RCR |= ENET_RCR_DRT_MASK;
1047  }
1048 
1049  //Reset buffer descriptors
1050  mpc5748Eth1InitBufferDesc(interface);
1051 
1052  //Re-enable Ethernet MAC
1053  ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
1054  //Instruct the DMA to poll the receive descriptor list
1055  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
1056 
1057  //Successful processing
1058  return NO_ERROR;
1059 }
1060 
1061 
1062 /**
1063  * @brief Write PHY register
1064  * @param[in] opcode Access type (2 bits)
1065  * @param[in] phyAddr PHY address (5 bits)
1066  * @param[in] regAddr Register address (5 bits)
1067  * @param[in] data Register value
1068  **/
1069 
1070 void mpc5748Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
1071  uint8_t regAddr, uint16_t data)
1072 {
1073  uint32_t temp;
1074 
1075  //Valid opcode?
1076  if(opcode == SMI_OPCODE_WRITE)
1077  {
1078  //Set up a write operation
1079  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
1080  //PHY address
1081  temp |= ENET_MMFR_PA(phyAddr);
1082  //Register address
1083  temp |= ENET_MMFR_RA(regAddr);
1084  //Register value
1085  temp |= ENET_MMFR_DATA(data);
1086 
1087  //Clear MII interrupt flag
1088  ENET_0->EIR = ENET_EIR_MII_MASK;
1089  //Start a write operation
1090  ENET_0->MMFR = temp;
1091 
1092  //Wait for the write to complete
1093  while((ENET_0->EIR & ENET_EIR_MII_MASK) == 0)
1094  {
1095  }
1096  }
1097  else
1098  {
1099  //The MAC peripheral only supports standard Clause 22 opcodes
1100  }
1101 }
1102 
1103 
1104 /**
1105  * @brief Read PHY register
1106  * @param[in] opcode Access type (2 bits)
1107  * @param[in] phyAddr PHY address (5 bits)
1108  * @param[in] regAddr Register address (5 bits)
1109  * @return Register value
1110  **/
1111 
1112 uint16_t mpc5748Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
1113  uint8_t regAddr)
1114 {
1115  uint16_t data;
1116  uint32_t temp;
1117 
1118  //Valid opcode?
1119  if(opcode == SMI_OPCODE_READ)
1120  {
1121  //Set up a read operation
1122  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
1123  //PHY address
1124  temp |= ENET_MMFR_PA(phyAddr);
1125  //Register address
1126  temp |= ENET_MMFR_RA(regAddr);
1127 
1128  //Clear MII interrupt flag
1129  ENET_0->EIR = ENET_EIR_MII_MASK;
1130  //Start a read operation
1131  ENET_0->MMFR = temp;
1132 
1133  //Wait for the read to complete
1134  while((ENET_0->EIR & ENET_EIR_MII_MASK) == 0)
1135  {
1136  }
1137 
1138  //Get register value
1139  data = ENET_0->MMFR & ENET_MMFR_DATA_MASK;
1140  }
1141  else
1142  {
1143  //The MAC peripheral only supports standard Clause 22 opcodes
1144  data = 0;
1145  }
1146 
1147  //Return the value of the PHY register
1148  return data;
1149 }
1150 
1151 
1152 /**
1153  * @brief CRC calculation
1154  * @param[in] data Pointer to the data over which to calculate the CRC
1155  * @param[in] length Number of bytes to process
1156  * @return Resulting CRC value
1157  **/
1158 
1159 uint32_t mpc5748Eth1CalcCrc(const void *data, size_t length)
1160 {
1161  uint_t i;
1162  uint_t j;
1163  uint32_t crc;
1164  const uint8_t *p;
1165 
1166  //Point to the data over which to calculate the CRC
1167  p = (uint8_t *) data;
1168  //CRC preset value
1169  crc = 0xFFFFFFFF;
1170 
1171  //Loop through data
1172  for(i = 0; i < length; i++)
1173  {
1174  //Update CRC value
1175  crc ^= p[i];
1176 
1177  //The message is processed bit by bit
1178  for(j = 0; j < 8; j++)
1179  {
1180  if((crc & 0x01) != 0)
1181  {
1182  crc = (crc >> 1) ^ 0xEDB88320;
1183  }
1184  else
1185  {
1186  crc = crc >> 1;
1187  }
1188  }
1189  }
1190 
1191  //Return CRC value
1192  return crc;
1193 }
osSetEventFromIsr
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
Definition: os_port_chibios.c:270
MPC5748_ETH1_TX_BUFFER_SIZE
#define MPC5748_ETH1_TX_BUFFER_SIZE
Definition: mpc5748_eth1_driver.h:43
opcode
uint8_t opcode
Definition: dns_common.h:188
bool_t
int bool_t
Definition: compiler_port.h:53
netEvent
#define netEvent
Definition: net_legacy.h:196
NIC_FULL_DUPLEX_MODE
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
ENET_TBD0_L
#define ENET_TBD0_L
Definition: mcimx6ul_eth1_driver.h:79
netBufferRead
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:690
ENET_RBD0_DATA_LENGTH
#define ENET_RBD0_DATA_LENGTH
Definition: mcimx6ul_eth1_driver.h:111
p
uint8_t p
Definition: ndp.h:300
NetBuffer
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
MAC_ADDR_FILTER_SIZE
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
TRUE
#define TRUE
Definition: os_port.h:50
mpc5748Eth1ReadPhyReg
uint16_t mpc5748Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Definition: mpc5748_eth1_driver.c:1112
data
uint8_t data[]
Definition: ethernet.h:222
sleep
#define sleep(delay)
Definition: os_port.h:307
MacFilterEntry::refCount
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
mpc5748Eth1UpdateMacConfig
error_t mpc5748Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Definition: mpc5748_eth1_driver.c:1016
mpc5748Eth1Tick
void mpc5748Eth1Tick(NetInterface *interface)
MPC5748 Ethernet MAC timer handler.
Definition: mpc5748_eth1_driver.c:538
ENET_TBD0_DATA_LENGTH
#define ENET_TBD0_DATA_LENGTH
Definition: mcimx6ul_eth1_driver.h:81
ENET_TBD0_W
#define ENET_TBD0_W
Definition: mcimx6ul_eth1_driver.h:77
mpc5748Eth1Driver
const NicDriver mpc5748Eth1Driver
MPC5748 Ethernet MAC driver (ENET0 instance)
Definition: mpc5748_eth1_driver.c:67
ENET_TBD0_TC
#define ENET_TBD0_TC
Definition: mcimx6ul_eth1_driver.h:80
nicProcessPacket
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:392
macIsMulticastAddr
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
mpc5748Eth1InitGpio
__weak_func void mpc5748Eth1InitGpio(NetInterface *interface)
GPIO configuration.
Definition: mpc5748_eth1_driver.c:217
osExitIsr
#define osExitIsr(flag)
Definition: os_port_chibios.h:72
SMI_OPCODE_WRITE
#define SMI_OPCODE_WRITE
Definition: nic.h:66
ENET0_Tx_IRQHandler
void ENET0_Tx_IRQHandler(void)
Ethernet MAC transmit interrupt.
Definition: mpc5748_eth1_driver.c:622
ENET_RBD0_L
#define ENET_RBD0_L
Definition: mcimx6ul_eth1_driver.h:102
mpc5748_eth1_driver.h
NXP MPC5748 Ethernet MAC driver (ENET0 instance)
FALSE
#define FALSE
Definition: os_port.h:46
mpc5748Eth1WritePhyReg
void mpc5748Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Definition: mpc5748_eth1_driver.c:1070
mpc5748Eth1EventHandler
void mpc5748Eth1EventHandler(NetInterface *interface)
MPC5748 Ethernet MAC event handler.
Definition: mpc5748_eth1_driver.c:721
error_t
error_t
Error codes.
Definition: error.h:43
ENET0_Rx_IRQHandler
void ENET0_Rx_IRQHandler(void)
Ethernet MAC receive interrupt.
Definition: mpc5748_eth1_driver.c:658
MPC5748_ETH1_TX_BUFFER_COUNT
#define MPC5748_ETH1_TX_BUFFER_COUNT
Definition: mpc5748_eth1_driver.h:36
NET_DEFAULT_RX_ANCILLARY
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:104
ERROR_FAILURE
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
txBuffer
#define txBuffer
Definition: aps3_eth_driver.c:45
NetRxAncillary
#define NetRxAncillary
Definition: net_misc.h:40
ERROR_INVALID_PACKET
@ ERROR_INVALID_PACKET
Definition: error.h:140
NetInterface
#define NetInterface
Definition: net.h:36
MacFilterEntry::addr
MacAddr addr
MAC address.
Definition: ethernet.h:263
mpc5748Eth1EnableIrq
void mpc5748Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
Definition: mpc5748_eth1_driver.c:563
ERROR_INVALID_LENGTH
@ ERROR_INVALID_LENGTH
Definition: error.h:111
ENET_RBD0_W
#define ENET_RBD0_W
Definition: mcimx6ul_eth1_driver.h:100
ERROR_BUFFER_EMPTY
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
ENET_RBD0_TR
#define ENET_RBD0_TR
Definition: mcimx6ul_eth1_driver.h:110
NetTxAncillary
#define NetTxAncillary
Definition: net_misc.h:36
SMI_OPCODE_READ
#define SMI_OPCODE_READ
Definition: nic.h:67
TRACE_INFO
#define TRACE_INFO(...)
Definition: debug.h:95
length
uint8_t length
Definition: tcp.h:368
MPC5748_ETH1_RX_BUFFER_COUNT
#define MPC5748_ETH1_RX_BUFFER_COUNT
Definition: mpc5748_eth1_driver.h:50
netBufferGetLength
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
MIN
#define MIN(a, b)
Definition: os_port.h:63
rxBuffer
#define rxBuffer
Definition: aps3_eth_driver.c:47
MacAddr
MacAddr
Definition: ethernet.h:195
ENET_RBD0_LG
#define ENET_RBD0_LG
Definition: mcimx6ul_eth1_driver.h:106
TRACE_DEBUG
#define TRACE_DEBUG(...)
Definition: debug.h:107
ENET0_Err_IRQHandler
void ENET0_Err_IRQHandler(void)
Ethernet MAC error interrupt.
Definition: mpc5748_eth1_driver.c:689
regAddr
uint16_t regAddr
Definition: modbus_common.h:276
ENET_RBD0_CR
#define ENET_RBD0_CR
Definition: mcimx6ul_eth1_driver.h:108
ENET_RBD0_OV
#define ENET_RBD0_OV
Definition: mcimx6ul_eth1_driver.h:109
ETH_MTU
#define ETH_MTU
Definition: ethernet.h:116
n
uint8_t n
Definition: dhcpv6_common.h:416
mpc5748Eth1Init
error_t mpc5748Eth1Init(NetInterface *interface)
MPC5748 Ethernet MAC initialization.
Definition: mpc5748_eth1_driver.c:94
MacFilterEntry
MAC filter table entry.
Definition: ethernet.h:262
mpc5748Eth1SendPacket
error_t mpc5748Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Definition: mpc5748_eth1_driver.c:776
address
Ipv6Addr address[]
Definition: ipv6.h:325
mpc5748Eth1InitBufferDesc
void mpc5748Eth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
Definition: mpc5748_eth1_driver.c:477
osEnterIsr
#define osEnterIsr()
Definition: os_port_chibios.h:70
ENET_TBD0_R
#define ENET_TBD0_R
Definition: mcimx6ul_eth1_driver.h:75
mpc5748Eth1UpdateMacAddrFilter
error_t mpc5748Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Definition: mpc5748_eth1_driver.c:927
value
uint8_t value[]
Definition: tcp.h:369
MPC5748_ETH1_IRQ_PRIORITY
#define MPC5748_ETH1_IRQ_PRIORITY
Definition: mpc5748_eth1_driver.h:64
ENET_TBD2_INT
#define ENET_TBD2_INT
Definition: mcimx6ul_eth1_driver.h:83
mpc5748Eth1DisableIrq
void mpc5748Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
Definition: mpc5748_eth1_driver.c:593
ENET_RBD0_E
#define ENET_RBD0_E
Definition: mcimx6ul_eth1_driver.h:98
osSetEvent
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
Definition: os_port_chibios.c:202
NIC_LINK_SPEED_100MBPS
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
mpc5748Eth1CalcCrc
uint32_t mpc5748Eth1CalcCrc(const void *data, size_t length)
CRC calculation.
Definition: mpc5748_eth1_driver.c:1159
uint_t
unsigned int uint_t
Definition: compiler_port.h:50
osMemset
#define osMemset(p, value, length)
Definition: os_port.h:135
net.h
TCP/IP stack core.
NicDriver
NIC driver.
Definition: nic.h:286
ENET_RBD0_NO
#define ENET_RBD0_NO
Definition: mcimx6ul_eth1_driver.h:107
ENET_RBD2_INT
#define ENET_RBD2_INT
Definition: mcimx6ul_eth1_driver.h:117
MPC5748_ETH1_RX_BUFFER_SIZE
#define MPC5748_ETH1_RX_BUFFER_SIZE
Definition: mpc5748_eth1_driver.h:57
NO_ERROR
@ NO_ERROR
Success.
Definition: error.h:44
mpc5748Eth1ReceivePacket
error_t mpc5748Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
Definition: mpc5748_eth1_driver.c:846
__attribute__
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Definition: avr32_eth_driver.c:380
debug.h
Debugging facilities.
NIC_TYPE_ETHERNET
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83