32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "device_registers.h"
36 #include "interrupt_manager.h"
58 static uint_t txBufferIndex;
60 static uint_t rxBufferIndex;
100 TRACE_INFO(
"Initializing MPC5748 Ethernet MAC (ENET0)...\r\n");
103 nicDriverInterface = interface;
109 ENET_0->ECR = ENET_ECR_RESET_MASK;
111 while((ENET_0->ECR & ENET_ECR_RESET_MASK) != 0)
117 ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
122 ENET_0->MSCR = ENET_MSCR_MII_SPEED(19);
125 if(interface->phyDriver != NULL)
128 error = interface->phyDriver->init(interface);
130 else if(interface->switchDriver != NULL)
133 error = interface->switchDriver->init(interface);
148 value = interface->macAddr.b[5];
149 value |= (interface->macAddr.b[4] << 8);
150 ENET_0->PAUR = ENET_PAUR_PADDR2(
value) | ENET_PAUR_TYPE(0x8808);
153 value = interface->macAddr.b[3];
154 value |= (interface->macAddr.b[2] << 8);
155 value |= (interface->macAddr.b[1] << 16);
156 value |= (interface->macAddr.b[0] << 24);
157 ENET_0->PALR = ENET_PALR_PADDR1(
value);
172 ENET_0->ECR = ENET_ECR_EN1588_MASK;
175 ENET_0->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
182 ENET_0->EIR = 0xFFFFFFFF;
184 ENET_0->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
194 ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
196 ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
214 #if defined(USE_DEVKIT_MPC5748G)
216 SIUL2->MSCR[94] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
217 SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_PUS_MASK |
218 SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_SSS(4);
219 SIUL2->IMCR[450] = SIUL2_IMCR_SSS(1);
222 SIUL2->MSCR[96] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
223 SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
226 SIUL2->MSCR[113] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
227 SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
230 SIUL2->MSCR[112] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
231 SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
234 SIUL2->MSCR[114] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
235 SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
238 SIUL2->MSCR[97] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
239 SIUL2->IMCR[449] = SIUL2_IMCR_SSS(1);
242 SIUL2->MSCR[9] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
243 SIUL2->IMCR[451] = SIUL2_IMCR_SSS(1);
246 SIUL2->MSCR[8] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
247 SIUL2->IMCR[452] = SIUL2_IMCR_SSS(1);
250 SIUL2->MSCR[11] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
251 SIUL2->IMCR[455] = SIUL2_IMCR_SSS(1);
254 SIUL2->MSCR[95] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
255 SIUL2->IMCR[457] = SIUL2_IMCR_SSS(1);
271 osMemset(txBufferDesc, 0,
sizeof(txBufferDesc));
272 osMemset(rxBufferDesc, 0,
sizeof(rxBufferDesc));
309 ENET_0->TDSR = (uint32_t) txBufferDesc;
311 ENET_0->RDSR = (uint32_t) rxBufferDesc;
329 if(interface->phyDriver != NULL)
332 interface->phyDriver->tick(interface);
334 else if(interface->switchDriver != NULL)
337 interface->switchDriver->tick(interface);
354 INT_SYS_EnableIRQ(ENET0_GROUP2_IRQn);
355 INT_SYS_EnableIRQ(ENET0_GROUP1_IRQn);
356 INT_SYS_EnableIRQ(ENET0_GROUP0_IRQn);
359 if(interface->phyDriver != NULL)
362 interface->phyDriver->enableIrq(interface);
364 else if(interface->switchDriver != NULL)
367 interface->switchDriver->enableIrq(interface);
384 INT_SYS_DisableIRQ(ENET0_GROUP2_IRQn);
385 INT_SYS_DisableIRQ(ENET0_GROUP1_IRQn);
386 INT_SYS_DisableIRQ(ENET0_GROUP0_IRQn);
389 if(interface->phyDriver != NULL)
392 interface->phyDriver->disableIrq(interface);
394 else if(interface->switchDriver != NULL)
397 interface->switchDriver->disableIrq(interface);
421 if((ENET_0->EIR & ENET_EIR_TXF_MASK) != 0)
424 ENET_0->EIR = ENET_EIR_TXF_MASK;
427 if((txBufferDesc[txBufferIndex][0] &
ENET_TBD0_R) == 0)
434 ENET_0->TDAR = ENET_TDAR_TDAR_MASK;
457 if((ENET_0->EIR & ENET_EIR_RXF_MASK) != 0)
460 ENET_0->EIMR &= ~ENET_EIMR_RXF_MASK;
463 nicDriverInterface->nicEvent =
TRUE;
488 if((ENET_0->EIR & ENET_EIR_EBERR_MASK) != 0)
491 ENET_0->EIMR &= ~ENET_EIMR_EBERR_MASK;
494 nicDriverInterface->nicEvent =
TRUE;
515 status = ENET_0->EIR;
518 if((status & ENET_EIR_RXF_MASK) != 0)
521 ENET_0->EIR = ENET_EIR_RXF_MASK;
534 if((status & ENET_EIR_EBERR_MASK) != 0)
537 ENET_0->EIR = ENET_EIR_EBERR_MASK;
540 ENET_0->ECR &= ~ENET_ECR_ETHEREN_MASK;
544 ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
546 ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
550 ENET_0->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
582 if((txBufferDesc[txBufferIndex][0] &
ENET_TBD0_R) != 0)
591 txBufferDesc[txBufferIndex][4] = 0;
614 ENET_0->TDAR = ENET_TDAR_TDAR_MASK;
617 if((txBufferDesc[txBufferIndex][0] &
ENET_TBD0_R) == 0)
641 if((rxBufferDesc[rxBufferIndex][0] &
ENET_RBD0_E) == 0)
644 if((rxBufferDesc[rxBufferIndex][0] &
ENET_RBD0_L) != 0)
677 rxBufferDesc[rxBufferIndex][4] = 0;
696 ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
721 uint32_t unicastHashTable[2];
722 uint32_t multicastHashTable[2];
729 value = interface->macAddr.b[5];
730 value |= (interface->macAddr.b[4] << 8);
731 ENET_0->PAUR = ENET_PAUR_PADDR2(
value) | ENET_PAUR_TYPE(0x8808);
734 value = interface->macAddr.b[3];
735 value |= (interface->macAddr.b[2] << 8);
736 value |= (interface->macAddr.b[1] << 16);
737 value |= (interface->macAddr.b[0] << 24);
738 ENET_0->PALR = ENET_PALR_PADDR1(
value);
741 unicastHashTable[0] = 0;
742 unicastHashTable[1] = 0;
745 multicastHashTable[0] = 0;
746 multicastHashTable[1] = 0;
753 entry = &interface->macAddrFilter[i];
763 k = (crc >> 26) & 0x3F;
769 multicastHashTable[k / 32] |= (1 << (k % 32));
774 unicastHashTable[k / 32] |= (1 << (k % 32));
780 ENET_0->IALR = unicastHashTable[0];
781 ENET_0->IAUR = unicastHashTable[1];
784 ENET_0->GALR = multicastHashTable[0];
785 ENET_0->GAUR = multicastHashTable[1];
788 TRACE_DEBUG(
" IALR = %08" PRIX32
"\r\n", ENET_0->IALR);
789 TRACE_DEBUG(
" IAUR = %08" PRIX32
"\r\n", ENET_0->IAUR);
790 TRACE_DEBUG(
" GALR = %08" PRIX32
"\r\n", ENET_0->GALR);
791 TRACE_DEBUG(
" GAUR = %08" PRIX32
"\r\n", ENET_0->GAUR);
807 ENET_0->ECR &= ~ENET_ECR_ETHEREN_MASK;
813 ENET_0->RCR &= ~ENET_RCR_RMII_10T_MASK;
818 ENET_0->RCR |= ENET_RCR_RMII_10T_MASK;
825 ENET_0->TCR |= ENET_TCR_FDEN_MASK;
827 ENET_0->RCR &= ~ENET_RCR_DRT_MASK;
832 ENET_0->TCR &= ~ENET_TCR_FDEN_MASK;
834 ENET_0->RCR |= ENET_RCR_DRT_MASK;
841 ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
843 ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
867 temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
869 temp |= ENET_MMFR_PA(phyAddr);
873 temp |= ENET_MMFR_DATA(
data);
876 ENET_0->EIR = ENET_EIR_MII_MASK;
881 while((ENET_0->EIR & ENET_EIR_MII_MASK) == 0)
910 temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
912 temp |= ENET_MMFR_PA(phyAddr);
917 ENET_0->EIR = ENET_EIR_MII_MASK;
922 while((ENET_0->EIR & ENET_EIR_MII_MASK) == 0)
927 data = ENET_0->MMFR & ENET_MMFR_DATA_MASK;
955 p = (uint8_t *)
data;
960 for(i = 0; i <
length; i++)
966 for(j = 0; j < 8; j++)
968 if((crc & 0x01) != 0)
970 crc = (crc >> 1) ^ 0xEDB88320;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define macIsMulticastAddr(macAddr)
#define MAC_ADDR_FILTER_SIZE
#define ENET_RBD0_DATA_LENGTH
#define ENET_TBD0_DATA_LENGTH
uint32_t mpc5748Eth1CalcCrc(const void *data, size_t length)
CRC calculation.
void ENET0_Err_IRQHandler(void)
Ethernet MAC error interrupt.
error_t mpc5748Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
__weak_func void mpc5748Eth1InitGpio(NetInterface *interface)
GPIO configuration.
void mpc5748Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver mpc5748Eth1Driver
MPC5748 Ethernet MAC driver (ENET0 instance)
void mpc5748Eth1Tick(NetInterface *interface)
MPC5748 Ethernet MAC timer handler.
error_t mpc5748Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void mpc5748Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void mpc5748Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
void ENET0_Rx_IRQHandler(void)
Ethernet MAC receive interrupt.
void ENET0_Tx_IRQHandler(void)
Ethernet MAC transmit interrupt.
error_t mpc5748Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t mpc5748Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t mpc5748Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void mpc5748Eth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t mpc5748Eth1Init(NetInterface *interface)
MPC5748 Ethernet MAC initialization.
void mpc5748Eth1EventHandler(NetInterface *interface)
MPC5748 Ethernet MAC event handler.
NXP MPC5748 Ethernet MAC driver (ENET0 instance)
#define MPC5748_ETH1_RX_BUFFER_SIZE
#define MPC5748_ETH1_TX_BUFFER_SIZE
#define MPC5748_ETH1_RX_BUFFER_COUNT
#define MPC5748_ETH1_IRQ_PRIORITY
#define MPC5748_ETH1_TX_BUFFER_COUNT
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemset(p, value, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.