mpc57xx_eth_driver.c
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1 /**
2  * @file mpc57xx_eth_driver.c
3  * @brief NXP MPC57xx Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "device_registers.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //TX buffer
45  __attribute__((aligned(64)));
46 //RX buffer
48  __attribute__((aligned(64)));
49 //TX buffer descriptors
50 static uint32_t txBufferDesc[MPC57XX_ETH_TX_BUFFER_COUNT][8]
51  __attribute__((aligned(64)));
52 //RX buffer descriptors
53 static uint32_t rxBufferDesc[MPC57XX_ETH_RX_BUFFER_COUNT][8]
54  __attribute__((aligned(64)));
55 
56 
57 //TX buffer index
58 static uint_t txBufferIndex;
59 //RX buffer index
60 static uint_t rxBufferIndex;
61 
62 
63 /**
64  * @brief MPC57xx Ethernet MAC driver
65  **/
66 
68 {
70  ETH_MTU,
81  TRUE,
82  TRUE,
83  TRUE,
84  FALSE
85 };
86 
87 
88 /**
89  * @brief MPC57xx Ethernet MAC initialization
90  * @param[in] interface Underlying network interface
91  * @return Error code
92  **/
93 
95 {
96  error_t error;
97  uint32_t value;
98 
99  //Debug message
100  TRACE_INFO("Initializing MPC57xx Ethernet MAC...\r\n");
101 
102  //Save underlying network interface
103  nicDriverInterface = interface;
104 
105  //GPIO configuration
106  mpc57xxEthInitGpio(interface);
107 
108  //Reset ENET module
109  ENET_0->ECR = ENET_ECR_RESET_MASK;
110  //Wait for the reset to complete
111  while((ENET_0->ECR & ENET_ECR_RESET_MASK) != 0)
112  {
113  }
114 
115  //Receive control register
116  ENET_0->RCR = ENET_RCR_MAX_FL(MPC57XX_ETH_RX_BUFFER_SIZE) |
117  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
118 
119  //Transmit control register
120  ENET_0->TCR = 0;
121  //Configure MDC clock frequency
122  ENET_0->MSCR = ENET_MSCR_MII_SPEED(19);
123 
124  //Valid Ethernet PHY or switch driver?
125  if(interface->phyDriver != NULL)
126  {
127  //Ethernet PHY initialization
128  error = interface->phyDriver->init(interface);
129  }
130  else if(interface->switchDriver != NULL)
131  {
132  //Ethernet switch initialization
133  error = interface->switchDriver->init(interface);
134  }
135  else
136  {
137  //The interface is not properly configured
138  error = ERROR_FAILURE;
139  }
140 
141  //Any error to report?
142  if(error)
143  {
144  return error;
145  }
146 
147  //Set the MAC address of the station (upper 16 bits)
148  value = interface->macAddr.b[5];
149  value |= (interface->macAddr.b[4] << 8);
150  ENET_0->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
151 
152  //Set the MAC address of the station (lower 32 bits)
153  value = interface->macAddr.b[3];
154  value |= (interface->macAddr.b[2] << 8);
155  value |= (interface->macAddr.b[1] << 16);
156  value |= (interface->macAddr.b[0] << 24);
157  ENET_0->PALR = ENET_PALR_PADDR1(value);
158 
159  //Hash table for unicast address filtering
160  ENET_0->IALR = 0;
161  ENET_0->IAUR = 0;
162  //Hash table for multicast address filtering
163  ENET_0->GALR = 0;
164  ENET_0->GAUR = 0;
165 
166  //Disable transmit accelerator functions
167  ENET_0->TACC = 0;
168  //Disable receive accelerator functions
169  ENET_0->RACC = 0;
170 
171  //Use enhanced buffer descriptors
172  ENET_0->ECR = ENET_ECR_EN1588_MASK;
173 
174  //Reset statistics counters
175  ENET_0->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
176  ENET_0->MIBC = 0;
177 
178  //Initialize buffer descriptors
179  mpc57xxEthInitBufferDesc(interface);
180 
181  //Clear any pending interrupts
182  ENET_0->EIR = 0xFFFFFFFF;
183  //Enable desired interrupts
184  ENET_0->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
185 
186  //Configure ENET transmit interrupt priority
187  INTC->PSR[ENET0_GROUP2_IRQn] = INTC_PSR_PRIN(MPC57XX_ETH_IRQ_PRIORITY);
188  //Configure ENET receive interrupt priority
189  INTC->PSR[ENET0_GROUP1_IRQn] = INTC_PSR_PRIN(MPC57XX_ETH_IRQ_PRIORITY);
190  //Configure ENET error interrupt priority
191  INTC->PSR[ENET0_GROUP0_IRQn] = INTC_PSR_PRIN(MPC57XX_ETH_IRQ_PRIORITY);
192 
193  //Enable Ethernet MAC
194  ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
195  //Instruct the DMA to poll the receive descriptor list
196  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
197 
198  //Accept any packets from the upper layer
199  osSetEvent(&interface->nicTxEvent);
200 
201  //Successful initialization
202  return NO_ERROR;
203 }
204 
205 
206 //DEVKIT-MPC5748G evaluation board?
207 #if defined(USE_DEVKIT_MPC5748G)
208 
209 /**
210  * @brief GPIO configuration
211  * @param[in] interface Underlying network interface
212  **/
213 
214 void mpc57xxEthInitGpio(NetInterface *interface)
215 {
216  //Configure MII_RMII_0_MDIO (PF14)
217  SIUL2->MSCR[94] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
218  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_PUS_MASK |
219  SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_SSS(4);
220  SIUL2->IMCR[450] = SIUL2_IMCR_SSS(1);
221 
222  //Configure MII_RMII_0_MDC (PG0)
223  SIUL2->MSCR[96] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
224  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
225 
226  //Configure MII_RMII_0_TXD0 (PH1)
227  SIUL2->MSCR[113] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
228  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
229 
230  //Configure MII_RMII_0_TXD1 (PH0)
231  SIUL2->MSCR[112] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
232  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(3);
233 
234  //Configure MII_RMII_0_TX_EN (PH2)
235  SIUL2->MSCR[114] = SIUL2_MSCR_SRC(3) | SIUL2_MSCR_OBE_MASK |
236  SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_SSS(4);
237 
238  //Configure MII_RMII_0_TX_CLK (PG1)
239  SIUL2->MSCR[97] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
240  SIUL2->IMCR[449] = SIUL2_IMCR_SSS(1);
241 
242  //Configure MII_RMII_0_RXD0 (PA9)
243  SIUL2->MSCR[9] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
244  SIUL2->IMCR[451] = SIUL2_IMCR_SSS(1);
245 
246  //Configure MII_RMII_0_RXD1 (PA8)
247  SIUL2->MSCR[8] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
248  SIUL2->IMCR[452] = SIUL2_IMCR_SSS(1);
249 
250  //Configure MII_RMII_0_RX_ER (PA11)
251  SIUL2->MSCR[11] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
252  SIUL2->IMCR[455] = SIUL2_IMCR_SSS(1);
253 
254  //Configure MII_RMII_0_RX_DV (PF15)
255  SIUL2->MSCR[95] = SIUL2_MSCR_SMC_MASK | SIUL2_MSCR_IBE_MASK;
256  SIUL2->IMCR[457] = SIUL2_IMCR_SSS(1);
257 }
258 
259 #endif
260 
261 
262 /**
263  * @brief Initialize buffer descriptors
264  * @param[in] interface Underlying network interface
265  **/
266 
268 {
269  uint_t i;
270  uint32_t address;
271 
272  //Clear TX and RX buffer descriptors
273  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
274  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
275 
276  //Initialize TX buffer descriptors
277  for(i = 0; i < MPC57XX_ETH_TX_BUFFER_COUNT; i++)
278  {
279  //Calculate the address of the current TX buffer
280  address = (uint32_t) txBuffer[i];
281  //Transmit buffer address
282  txBufferDesc[i][1] = address;
283  //Generate interrupts
284  txBufferDesc[i][2] = ENET_TBD2_INT;
285  }
286 
287  //Mark the last descriptor entry with the wrap flag
288  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
289  //Initialize TX buffer index
290  txBufferIndex = 0;
291 
292  //Initialize RX buffer descriptors
293  for(i = 0; i < MPC57XX_ETH_RX_BUFFER_COUNT; i++)
294  {
295  //Calculate the address of the current RX buffer
296  address = (uint32_t) rxBuffer[i];
297  //The descriptor is initially owned by the DMA
298  rxBufferDesc[i][0] = ENET_RBD0_E;
299  //Receive buffer address
300  rxBufferDesc[i][1] = address;
301  //Generate interrupts
302  rxBufferDesc[i][2] = ENET_RBD2_INT;
303  }
304 
305  //Mark the last descriptor entry with the wrap flag
306  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
307  //Initialize RX buffer index
308  rxBufferIndex = 0;
309 
310  //Start location of the TX descriptor list
311  ENET_0->TDSR = (uint32_t) txBufferDesc;
312  //Start location of the RX descriptor list
313  ENET_0->RDSR = (uint32_t) rxBufferDesc;
314  //Maximum receive buffer size
315  ENET_0->MRBR = MPC57XX_ETH_RX_BUFFER_SIZE;
316 }
317 
318 
319 /**
320  * @brief MPC57xx Ethernet MAC timer handler
321  *
322  * This routine is periodically called by the TCP/IP stack to handle periodic
323  * operations such as polling the link state
324  *
325  * @param[in] interface Underlying network interface
326  **/
327 
328 void mpc57xxEthTick(NetInterface *interface)
329 {
330  //Valid Ethernet PHY or switch driver?
331  if(interface->phyDriver != NULL)
332  {
333  //Handle periodic operations
334  interface->phyDriver->tick(interface);
335  }
336  else if(interface->switchDriver != NULL)
337  {
338  //Handle periodic operations
339  interface->switchDriver->tick(interface);
340  }
341  else
342  {
343  //Just for sanity
344  }
345 }
346 
347 
348 /**
349  * @brief Enable interrupts
350  * @param[in] interface Underlying network interface
351  **/
352 
354 {
355  //Enable Ethernet MAC interrupts
356  INTC->PSR[ENET0_GROUP2_IRQn] |= INTC_PSR_PRC_SELN0_MASK;
357  INTC->PSR[ENET0_GROUP1_IRQn] |= INTC_PSR_PRC_SELN0_MASK;
358  INTC->PSR[ENET0_GROUP0_IRQn] |= INTC_PSR_PRC_SELN0_MASK;
359 
360 
361  //Valid Ethernet PHY or switch driver?
362  if(interface->phyDriver != NULL)
363  {
364  //Enable Ethernet PHY interrupts
365  interface->phyDriver->enableIrq(interface);
366  }
367  else if(interface->switchDriver != NULL)
368  {
369  //Enable Ethernet switch interrupts
370  interface->switchDriver->enableIrq(interface);
371  }
372  else
373  {
374  //Just for sanity
375  }
376 }
377 
378 
379 /**
380  * @brief Disable interrupts
381  * @param[in] interface Underlying network interface
382  **/
383 
385 {
386  //Disable Ethernet MAC interrupts
387  INTC->PSR[ENET0_GROUP2_IRQn] &= ~INTC_PSR_PRC_SELN0_MASK;
388  INTC->PSR[ENET0_GROUP1_IRQn] &= ~INTC_PSR_PRC_SELN0_MASK;
389  INTC->PSR[ENET0_GROUP0_IRQn] &= ~INTC_PSR_PRC_SELN0_MASK;
390 
391 
392  //Valid Ethernet PHY or switch driver?
393  if(interface->phyDriver != NULL)
394  {
395  //Disable Ethernet PHY interrupts
396  interface->phyDriver->disableIrq(interface);
397  }
398  else if(interface->switchDriver != NULL)
399  {
400  //Disable Ethernet switch interrupts
401  interface->switchDriver->disableIrq(interface);
402  }
403  else
404  {
405  //Just for sanity
406  }
407 }
408 
409 
410 /**
411  * @brief Ethernet MAC transmit interrupt
412  **/
413 
415 {
416  bool_t flag;
417 
418  //Interrupt service routine prologue
419  osEnterIsr();
420 
421  //This flag will be set if a higher priority task must be woken
422  flag = FALSE;
423 
424  //Packet transmitted?
425  if((ENET_0->EIR & ENET_EIR_TXF_MASK) != 0)
426  {
427  //Clear TXF interrupt flag
428  ENET_0->EIR = ENET_EIR_TXF_MASK;
429 
430  //Check whether the TX buffer is available for writing
431  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
432  {
433  //Notify the TCP/IP stack that the transmitter is ready to send
434  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
435  }
436 
437  //Instruct the DMA to poll the transmit descriptor list
438  ENET_0->TDAR = ENET_TDAR_TDAR_MASK;
439  }
440 
441  //Interrupt service routine epilogue
442  osExitIsr(flag);
443 }
444 
445 
446 /**
447  * @brief Ethernet MAC receive interrupt
448  **/
449 
451 {
452  bool_t flag;
453 
454  //Interrupt service routine prologue
455  osEnterIsr();
456 
457  //This flag will be set if a higher priority task must be woken
458  flag = FALSE;
459 
460  //Packet received?
461  if((ENET_0->EIR & ENET_EIR_RXF_MASK) != 0)
462  {
463  //Disable RXF interrupt
464  ENET_0->EIMR &= ~ENET_EIMR_RXF_MASK;
465 
466  //Set event flag
467  nicDriverInterface->nicEvent = TRUE;
468  //Notify the TCP/IP stack of the event
469  flag = osSetEventFromIsr(&netEvent);
470  }
471 
472  //Interrupt service routine epilogue
473  osExitIsr(flag);
474 }
475 
476 
477 /**
478  * @brief Ethernet MAC error interrupt
479  **/
480 
482 {
483  bool_t flag;
484 
485  //Interrupt service routine prologue
486  osEnterIsr();
487 
488  //This flag will be set if a higher priority task must be woken
489  flag = FALSE;
490 
491  //System bus error?
492  if((ENET_0->EIR & ENET_EIR_EBERR_MASK) != 0)
493  {
494  //Disable EBERR interrupt
495  ENET_0->EIMR &= ~ENET_EIMR_EBERR_MASK;
496 
497  //Set event flag
498  nicDriverInterface->nicEvent = TRUE;
499  //Notify the TCP/IP stack of the event
500  flag |= osSetEventFromIsr(&netEvent);
501  }
502 
503  //Interrupt service routine epilogue
504  osExitIsr(flag);
505 }
506 
507 
508 /**
509  * @brief MPC57xx Ethernet MAC event handler
510  * @param[in] interface Underlying network interface
511  **/
512 
514 {
515  error_t error;
516  uint32_t status;
517 
518  //Read interrupt event register
519  status = ENET_0->EIR;
520 
521  //Packet received?
522  if((status & ENET_EIR_RXF_MASK) != 0)
523  {
524  //Clear RXF interrupt flag
525  ENET_0->EIR = ENET_EIR_RXF_MASK;
526 
527  //Process all pending packets
528  do
529  {
530  //Read incoming packet
531  error = mpc57xxEthReceivePacket(interface);
532 
533  //No more data in the receive buffer?
534  } while(error != ERROR_BUFFER_EMPTY);
535  }
536 
537  //System bus error?
538  if((status & ENET_EIR_EBERR_MASK) != 0)
539  {
540  //Clear EBERR interrupt flag
541  ENET_0->EIR = ENET_EIR_EBERR_MASK;
542 
543  //Disable Ethernet MAC
544  ENET_0->ECR &= ~ENET_ECR_ETHEREN_MASK;
545  //Reset buffer descriptors
546  mpc57xxEthInitBufferDesc(interface);
547  //Resume normal operation
548  ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
549  //Instruct the DMA to poll the receive descriptor list
550  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
551  }
552 
553  //Re-enable Ethernet MAC interrupts
554  ENET_0->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
555 }
556 
557 
558 /**
559  * @brief Send a packet
560  * @param[in] interface Underlying network interface
561  * @param[in] buffer Multi-part buffer containing the data to send
562  * @param[in] offset Offset to the first data byte
563  * @param[in] ancillary Additional options passed to the stack along with
564  * the packet
565  * @return Error code
566  **/
567 
569  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
570 {
571  size_t length;
572 
573  //Retrieve the length of the packet
574  length = netBufferGetLength(buffer) - offset;
575 
576  //Check the frame length
578  {
579  //The transmitter can accept another packet
580  osSetEvent(&interface->nicTxEvent);
581  //Report an error
582  return ERROR_INVALID_LENGTH;
583  }
584 
585  //Make sure the current buffer is available for writing
586  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
587  {
588  return ERROR_FAILURE;
589  }
590 
591  //Copy user data to the transmit buffer
592  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
593 
594  //Clear BDU flag
595  txBufferDesc[txBufferIndex][4] = 0;
596 
597  //Check current index
598  if(txBufferIndex < (MPC57XX_ETH_TX_BUFFER_COUNT - 1))
599  {
600  //Give the ownership of the descriptor to the DMA engine
601  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
603 
604  //Point to the next buffer
605  txBufferIndex++;
606  }
607  else
608  {
609  //Give the ownership of the descriptor to the DMA engine
610  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
612 
613  //Wrap around
614  txBufferIndex = 0;
615  }
616 
617  //Instruct the DMA to poll the transmit descriptor list
618  ENET_0->TDAR = ENET_TDAR_TDAR_MASK;
619 
620  //Check whether the next buffer is available for writing
621  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
622  {
623  //The transmitter can accept another packet
624  osSetEvent(&interface->nicTxEvent);
625  }
626 
627  //Successful processing
628  return NO_ERROR;
629 }
630 
631 
632 /**
633  * @brief Receive a packet
634  * @param[in] interface Underlying network interface
635  * @return Error code
636  **/
637 
639 {
640  error_t error;
641  size_t n;
642  NetRxAncillary ancillary;
643 
644  //Make sure the current buffer is available for reading
645  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
646  {
647  //The frame should not span multiple buffers
648  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
649  {
650  //Check whether an error occurred
651  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
653  {
654  //Retrieve the length of the frame
655  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
656  //Limit the number of data to read
658 
659  //Additional options can be passed to the stack along with the packet
660  ancillary = NET_DEFAULT_RX_ANCILLARY;
661 
662  //Pass the packet to the upper layer
663  nicProcessPacket(interface, rxBuffer[rxBufferIndex], n, &ancillary);
664 
665  //Valid packet received
666  error = NO_ERROR;
667  }
668  else
669  {
670  //The received packet contains an error
671  error = ERROR_INVALID_PACKET;
672  }
673  }
674  else
675  {
676  //The packet is not valid
677  error = ERROR_INVALID_PACKET;
678  }
679 
680  //Clear BDU flag
681  rxBufferDesc[rxBufferIndex][4] = 0;
682 
683  //Check current index
684  if(rxBufferIndex < (MPC57XX_ETH_RX_BUFFER_COUNT - 1))
685  {
686  //Give the ownership of the descriptor back to the DMA engine
687  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
688  //Point to the next buffer
689  rxBufferIndex++;
690  }
691  else
692  {
693  //Give the ownership of the descriptor back to the DMA engine
694  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
695  //Wrap around
696  rxBufferIndex = 0;
697  }
698 
699  //Instruct the DMA to poll the receive descriptor list
700  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
701  }
702  else
703  {
704  //No more data in the receive buffer
705  error = ERROR_BUFFER_EMPTY;
706  }
707 
708  //Return status code
709  return error;
710 }
711 
712 
713 /**
714  * @brief Configure MAC address filtering
715  * @param[in] interface Underlying network interface
716  * @return Error code
717  **/
718 
720 {
721  uint_t i;
722  uint_t k;
723  uint32_t crc;
724  uint32_t value;
725  uint32_t unicastHashTable[2];
726  uint32_t multicastHashTable[2];
727  MacFilterEntry *entry;
728 
729  //Debug message
730  TRACE_DEBUG("Updating MAC filter...\r\n");
731 
732  //Set the MAC address of the station (upper 16 bits)
733  value = interface->macAddr.b[5];
734  value |= (interface->macAddr.b[4] << 8);
735  ENET_0->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
736 
737  //Set the MAC address of the station (lower 32 bits)
738  value = interface->macAddr.b[3];
739  value |= (interface->macAddr.b[2] << 8);
740  value |= (interface->macAddr.b[1] << 16);
741  value |= (interface->macAddr.b[0] << 24);
742  ENET_0->PALR = ENET_PALR_PADDR1(value);
743 
744  //Clear hash table (unicast address filtering)
745  unicastHashTable[0] = 0;
746  unicastHashTable[1] = 0;
747 
748  //Clear hash table (multicast address filtering)
749  multicastHashTable[0] = 0;
750  multicastHashTable[1] = 0;
751 
752  //The MAC address filter contains the list of MAC addresses to accept
753  //when receiving an Ethernet frame
754  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
755  {
756  //Point to the current entry
757  entry = &interface->macAddrFilter[i];
758 
759  //Valid entry?
760  if(entry->refCount > 0)
761  {
762  //Compute CRC over the current MAC address
763  crc = mpc57xxEthCalcCrc(&entry->addr, sizeof(MacAddr));
764 
765  //The upper 6 bits in the CRC register are used to index the
766  //contents of the hash table
767  k = (crc >> 26) & 0x3F;
768 
769  //Multicast address?
770  if(macIsMulticastAddr(&entry->addr))
771  {
772  //Update the multicast hash table
773  multicastHashTable[k / 32] |= (1 << (k % 32));
774  }
775  else
776  {
777  //Update the unicast hash table
778  unicastHashTable[k / 32] |= (1 << (k % 32));
779  }
780  }
781  }
782 
783  //Write the hash table (unicast address filtering)
784  ENET_0->IALR = unicastHashTable[0];
785  ENET_0->IAUR = unicastHashTable[1];
786 
787  //Write the hash table (multicast address filtering)
788  ENET_0->GALR = multicastHashTable[0];
789  ENET_0->GAUR = multicastHashTable[1];
790 
791  //Debug message
792  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET_0->IALR);
793  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET_0->IAUR);
794  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET_0->GALR);
795  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET_0->GAUR);
796 
797  //Successful processing
798  return NO_ERROR;
799 }
800 
801 
802 /**
803  * @brief Adjust MAC configuration parameters for proper operation
804  * @param[in] interface Underlying network interface
805  * @return Error code
806  **/
807 
809 {
810  //Disable Ethernet MAC while modifying configuration registers
811  ENET_0->ECR &= ~ENET_ECR_ETHEREN_MASK;
812 
813  //10BASE-T or 100BASE-TX operation mode?
814  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
815  {
816  //100 Mbps operation
817  ENET_0->RCR &= ~ENET_RCR_RMII_10T_MASK;
818  }
819  else
820  {
821  //10 Mbps operation
822  ENET_0->RCR |= ENET_RCR_RMII_10T_MASK;
823  }
824 
825  //Half-duplex or full-duplex mode?
826  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
827  {
828  //Full-duplex mode
829  ENET_0->TCR |= ENET_TCR_FDEN_MASK;
830  //Receive path operates independently of transmit
831  ENET_0->RCR &= ~ENET_RCR_DRT_MASK;
832  }
833  else
834  {
835  //Half-duplex mode
836  ENET_0->TCR &= ~ENET_TCR_FDEN_MASK;
837  //Disable reception of frames while transmitting
838  ENET_0->RCR |= ENET_RCR_DRT_MASK;
839  }
840 
841  //Reset buffer descriptors
842  mpc57xxEthInitBufferDesc(interface);
843 
844  //Re-enable Ethernet MAC
845  ENET_0->ECR |= ENET_ECR_ETHEREN_MASK;
846  //Instruct the DMA to poll the receive descriptor list
847  ENET_0->RDAR = ENET_RDAR_RDAR_MASK;
848 
849  //Successful processing
850  return NO_ERROR;
851 }
852 
853 
854 /**
855  * @brief Write PHY register
856  * @param[in] opcode Access type (2 bits)
857  * @param[in] phyAddr PHY address (5 bits)
858  * @param[in] regAddr Register address (5 bits)
859  * @param[in] data Register value
860  **/
861 
862 void mpc57xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
863  uint8_t regAddr, uint16_t data)
864 {
865  uint32_t temp;
866 
867  //Valid opcode?
868  if(opcode == SMI_OPCODE_WRITE)
869  {
870  //Set up a write operation
871  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
872  //PHY address
873  temp |= ENET_MMFR_PA(phyAddr);
874  //Register address
875  temp |= ENET_MMFR_RA(regAddr);
876  //Register value
877  temp |= ENET_MMFR_DATA(data);
878 
879  //Clear MII interrupt flag
880  ENET_0->EIR = ENET_EIR_MII_MASK;
881  //Start a write operation
882  ENET_0->MMFR = temp;
883 
884  //Wait for the write to complete
885  while((ENET_0->EIR & ENET_EIR_MII_MASK) == 0)
886  {
887  }
888  }
889  else
890  {
891  //The MAC peripheral only supports standard Clause 22 opcodes
892  }
893 }
894 
895 
896 /**
897  * @brief Read PHY register
898  * @param[in] opcode Access type (2 bits)
899  * @param[in] phyAddr PHY address (5 bits)
900  * @param[in] regAddr Register address (5 bits)
901  * @return Register value
902  **/
903 
904 uint16_t mpc57xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
905  uint8_t regAddr)
906 {
907  uint16_t data;
908  uint32_t temp;
909 
910  //Valid opcode?
911  if(opcode == SMI_OPCODE_READ)
912  {
913  //Set up a read operation
914  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
915  //PHY address
916  temp |= ENET_MMFR_PA(phyAddr);
917  //Register address
918  temp |= ENET_MMFR_RA(regAddr);
919 
920  //Clear MII interrupt flag
921  ENET_0->EIR = ENET_EIR_MII_MASK;
922  //Start a read operation
923  ENET_0->MMFR = temp;
924 
925  //Wait for the read to complete
926  while((ENET_0->EIR & ENET_EIR_MII_MASK) == 0)
927  {
928  }
929 
930  //Get register value
931  data = ENET_0->MMFR & ENET_MMFR_DATA_MASK;
932  }
933  else
934  {
935  //The MAC peripheral only supports standard Clause 22 opcodes
936  data = 0;
937  }
938 
939  //Return the value of the PHY register
940  return data;
941 }
942 
943 
944 /**
945  * @brief CRC calculation
946  * @param[in] data Pointer to the data over which to calculate the CRC
947  * @param[in] length Number of bytes to process
948  * @return Resulting CRC value
949  **/
950 
951 uint32_t mpc57xxEthCalcCrc(const void *data, size_t length)
952 {
953  uint_t i;
954  uint_t j;
955  uint32_t crc;
956  const uint8_t *p;
957 
958  //Point to the data over which to calculate the CRC
959  p = (uint8_t *) data;
960  //CRC preset value
961  crc = 0xFFFFFFFF;
962 
963  //Loop through data
964  for(i = 0; i < length; i++)
965  {
966  //Update CRC value
967  crc ^= p[i];
968  //The message is processed bit by bit
969  for(j = 0; j < 8; j++)
970  {
971  if((crc & 0x01) != 0)
972  {
973  crc = (crc >> 1) ^ 0xEDB88320;
974  }
975  else
976  {
977  crc = crc >> 1;
978  }
979  }
980  }
981 
982  //Return CRC value
983  return crc;
984 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
#define ENET_TBD0_L
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void mpc57xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ENET_RBD0_DATA_LENGTH
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
void mpc57xxEthInitGpio(NetInterface *interface)
__start_packed struct @5 MacAddr
MAC address.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
void mpc57xxEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define ENET_TBD0_DATA_LENGTH
#define MPC57XX_ETH_TX_BUFFER_SIZE
#define ENET_TBD0_W
#define ENET_TBD0_TC
uint16_t mpc57xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:65
void ENET0_Rx_IRQHandler(void)
Ethernet MAC receive interrupt.
void ENET0_Err_IRQHandler(void)
Ethernet MAC error interrupt.
#define ENET_RBD0_L
void mpc57xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define FALSE
Definition: os_port.h:46
uint32_t mpc57xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t
Error codes.
Definition: error.h:42
void mpc57xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t value[]
Definition: tcp.h:332
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
NXP MPC57xx Ethernet MAC driver.
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define MPC57XX_ETH_RX_BUFFER_SIZE
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define ENET_RBD0_W
error_t mpc57xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define ENET_RBD0_TR
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
error_t mpc57xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define rxBuffer
#define ENET_RBD0_LG
void mpc57xxEthEventHandler(NetInterface *interface)
MPC57xx Ethernet MAC event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:107
error_t mpc57xxEthReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t regAddr
#define ENET_RBD0_CR
#define ENET_RBD0_OV
void mpc57xxEthTick(NetInterface *interface)
MPC57xx Ethernet MAC timer handler.
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define MPC57XX_ETH_TX_BUFFER_COUNT
#define osEnterIsr()
#define ENET_TBD0_R
#define ENET_TBD2_INT
#define ENET_RBD0_E
#define MPC57XX_ETH_IRQ_PRIORITY
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t mpc57xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
const NicDriver mpc57xxEthDriver
MPC57xx Ethernet MAC driver.
void ENET0_Tx_IRQHandler(void)
Ethernet MAC transmit interrupt.
unsigned int uint_t
Definition: compiler_port.h:45
#define osMemset(p, value, length)
Definition: os_port.h:128
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
error_t mpc57xxEthInit(NetInterface *interface)
MPC57xx Ethernet MAC initialization.
#define ENET_RBD0_NO
#define ENET_RBD2_INT
#define MPC57XX_ETH_RX_BUFFER_COUNT
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
Ethernet interface.
Definition: nic.h:82