32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "hl_hw_reg_access.h"
36 #include "hl_hw_emac.h"
37 #include "hl_hw_emac_ctrl.h"
38 #include "hl_hw_mdio.h"
40 #include "hl_sys_vim.h"
46 #define MDIO_INPUT_CLK 75000000
48 #define MDIO_OUTPUT_CLK 1000000
54 #if defined(__ICCARM__)
57 #pragma data_alignment = 4
58 #pragma location = RM57_ETH_RAM_SECTION
61 #pragma data_alignment = 4
62 #pragma location = RM57_ETH_RAM_SECTION
65 #pragma data_alignment = 4
66 #pragma location = RM57_ETH_RAM_CPPI_SECTION
69 #pragma data_alignment = 4
70 #pragma location = RM57_ETH_RAM_CPPI_SECTION
135 TRACE_INFO(
"Initializing RM57 Ethernet MAC...\r\n");
138 nicDriverInterface = interface;
162 MDIO_CONTROL_FAULTENB | (temp & MDIO_CONTROL_CLKDIV);
165 if(interface->phyDriver != NULL)
168 error = interface->phyDriver->init(interface);
170 else if(interface->switchDriver != NULL)
173 error = interface->switchDriver->init(interface);
207 (interface->macAddr.b[1] << 8) |
208 (interface->macAddr.b[2] << 16) |
209 (interface->macAddr.b[3] << 24);
213 (interface->macAddr.b[5] << 8);
220 (interface->macAddr.b[1] << 8) |
221 (interface->macAddr.b[2] << 16) |
222 (interface->macAddr.b[3] << 24);
225 temp = interface->macAddr.b[4] |
226 (interface->macAddr.b[5] << 8);
230 (
EMAC_CH0 << EMAC_MACADDRLO_CHANNEL_SHIFT) | temp;
260 (
EMAC_CH0 << EMAC_RXMBPENABLE_RXBROADCH_SHIFT);
264 (
EMAC_CH0 << EMAC_RXMBPENABLE_RXMULTCH_SHIFT);
315 #if defined(USE_LAUNCHXL2_RM57L)
317 gioPORTA->DIR &= ~(1 << 3);
318 gioPORTA->PSL |= (1 << 3);
319 gioPORTA->PULDIS &= ~(1 << 3);
322 gioPORTA->DIR |= (1 << 4);
323 gioPORTA->PDR &= ~(1 << 4);
326 gioPORTA->DCLR = (1 << 4);
328 gioPORTA->DSET = (1 << 4);
354 txBufferDesc[i].
word0 = (uint32_t) NULL;
358 txBufferDesc[i].
word2 = 0;
360 txBufferDesc[i].
word3 = 0;
363 txBufferDesc[i].
next = &txBufferDesc[nextIndex];
364 txBufferDesc[i].
prev = &txBufferDesc[prevIndex];
368 txCurBufferDesc = &txBufferDesc[0];
383 rxBufferDesc[i].
word0 = (uint32_t) &rxBufferDesc[nextIndex];
392 rxBufferDesc[i].
next = &rxBufferDesc[nextIndex];
393 rxBufferDesc[i].
prev = &rxBufferDesc[prevIndex];
397 rxCurBufferDesc = &rxBufferDesc[0];
400 rxCurBufferDesc->
prev->
word0 = (uint32_t) NULL;
416 if(interface->phyDriver != NULL)
419 interface->phyDriver->tick(interface);
421 else if(interface->switchDriver != NULL)
424 interface->switchDriver->tick(interface);
457 if(interface->phyDriver != NULL)
460 interface->phyDriver->enableIrq(interface);
462 else if(interface->switchDriver != NULL)
465 interface->switchDriver->enableIrq(interface);
486 if(interface->phyDriver != NULL)
489 interface->phyDriver->disableIrq(interface);
491 else if(interface->switchDriver != NULL)
494 interface->switchDriver->disableIrq(interface);
507 #if defined(__ICCARM__)
510 #pragma CODE_STATE(rm57EthTxIrqHandler, 32)
511 #pragma INTERRUPT(rm57EthTxIrqHandler, IRQ)
576 #if defined(__ICCARM__)
579 #pragma CODE_STATE(rm57EthRxIrqHandler, 32)
580 #pragma INTERRUPT(rm57EthRxIrqHandler, IRQ)
604 nicDriverInterface->nicEvent =
TRUE;
675 txCurBufferDesc->
word0 = (uint32_t) NULL;
689 txCurBufferDesc->
prev->
word0 = (uint32_t) txCurBufferDesc;
708 txCurBufferDesc = txCurBufferDesc->
next;
769 rxCurBufferDesc->
word0 = (uint32_t) NULL;
776 rxCurBufferDesc->
prev->
word0 = (uint32_t) rxCurBufferDesc;
795 rxCurBufferDesc = rxCurBufferDesc->
next;
831 uint32_t hashTable[2];
846 entry = &interface->macAddrFilter[i];
855 k = (
p[0] >> 2) ^ (
p[0] << 4);
856 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
857 k ^= (
p[2] >> 6) ^
p[2];
858 k ^= (
p[3] >> 2) ^ (
p[3] << 4);
859 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
860 k ^= (
p[5] >> 6) ^
p[5];
866 hashTable[k / 32] |= (1 << (k % 32));
899 config |= EMAC_MACCONTROL_RMIISPEED;
903 config &= ~EMAC_MACCONTROL_RMIISPEED;
909 config |= EMAC_MACCONTROL_FULLDUPLEX;
913 config &= ~EMAC_MACCONTROL_FULLDUPLEX;
941 temp = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE;
943 temp |= (phyAddr << MDIO_USERACCESS0_PHYADR_SHIFT) & MDIO_USERACCESS0_PHYADR;
945 temp |= (
regAddr << MDIO_USERACCESS0_REGADR_SHIFT) & MDIO_USERACCESS0_REGADR;
947 temp |=
data & MDIO_USERACCESS0_DATA;
981 temp = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_READ;
983 temp |= (phyAddr << MDIO_USERACCESS0_PHYADR_SHIFT) & MDIO_USERACCESS0_PHYADR;
985 temp |= (
regAddr << MDIO_USERACCESS0_REGADR_SHIFT) & MDIO_USERACCESS0_REGADR;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define EMAC_CTRL_C0RXSTAT_R
#define EMAC_TX_WORD3_EOQ
#define EMAC_MACEOIVECTOR_C0TX
#define EMAC_RX_WORD3_SOP
#define EMAC_TX_WORD2_BUFFER_LENGTH
#define EMAC_RX_WORD3_PACKET_LENGTH
#define EMAC_RXMBPENABLE_R
#define EMAC_RX_WORD3_OWNER
#define EMAC_TX_WORD3_OWNER
#define EMAC_RXINTMASKSET_R
#define MDIO_USERACCESS0_R
#define EMAC_RXBUFFEROFFSET_R
#define EMAC_TXINTMASKSET_R
#define EMAC_RXUNICASTSET_R
#define EMAC_CTRL_CnRXEN_R(n)
#define EMAC_TX_WORD3_EOP
#define EMAC_RX_WORD3_ERROR_MASK
#define EMAC_CTRL_CnTXEN_R(n)
#define EMAC_TXINTMASKCLEAR_R
#define EMAC_RX_WORD3_EOP
#define EMAC_MACSRCADDRHI_R
#define EMAC_TX_WORD3_PACKET_LENGTH
#define EMAC_MACEOIVECTOR_C0RX
#define EMAC_CTRL_C0TXSTAT_R
#define EMAC_RXINTMASKCLEAR_R
#define EMAC_RXUNICASTCLEAR_R
#define EMAC_MACEOIVECTOR_R
#define EMAC_CTRL_SOFTRESET_R
#define EMAC_RX_WORD3_EOQ
#define EMAC_TX_WORD3_SOP
#define EMAC_MACSRCADDRLO_R
#define EMAC_MACCONTROL_R
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void rm57EthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
void rm57EthTick(NetInterface *interface)
RM57 Ethernet MAC timer handler.
const NicDriver rm57EthDriver
RM57 Ethernet MAC driver.
void rm57EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
void rm57EthEnableIrq(NetInterface *interface)
Enable interrupts.
void rm57EthEventHandler(NetInterface *interface)
RM57 Ethernet MAC event handler.
error_t rm57EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t rm57EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t rm57EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void rm57EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t rm57EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
__weak_func void rm57EthInitGpio(NetInterface *interface)
GPIO configuration.
void rm57EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t rm57EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t rm57EthInit(NetInterface *interface)
RM57 Ethernet MAC initialization.
void rm57EthRxIrqHandler(void)
Ethernet MAC receive interrupt.
RM57 Ethernet MAC driver.
#define RM57_ETH_RAM_CPPI_SECTION
#define RM57_ETH_TX_BUFFER_COUNT
#define RM57_ETH_RAM_SECTION
#define RM57_ETH_RX_BUFFER_SIZE
#define RM57_ETH_RX_BUFFER_COUNT
#define RM57_ETH_RX_IRQ_CHANNEL
#define RM57_ETH_TX_BUFFER_SIZE
#define RM57_ETH_TX_IRQ_CHANNEL
struct _Rm57RxBufferDesc * next
struct _Rm57RxBufferDesc * prev
struct _Rm57TxBufferDesc * next
struct _Rm57TxBufferDesc * prev
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.