s32k148_eth_driver.c
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1 /**
2  * @file s32k148_eth_driver.c
3  * @brief NXP S32K148 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "s32k148.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //TX buffer
47 #pragma data_alignment = 16
49 //RX buffer
50 #pragma data_alignment = 16
52 //TX buffer descriptors
53 #pragma data_alignment = 16
54 static uint32_t txBufferDesc[S32K148_ETH_TX_BUFFER_COUNT][8];
55 //RX buffer descriptors
56 #pragma data_alignment = 16
57 static uint32_t rxBufferDesc[S32K148_ETH_RX_BUFFER_COUNT][8];
58 
59 //ARM or GCC compiler?
60 #else
61 
62 //TX buffer
64  __attribute__((aligned(16)));
65 //RX buffer
67  __attribute__((aligned(16)));
68 //TX buffer descriptors
69 static uint32_t txBufferDesc[S32K148_ETH_TX_BUFFER_COUNT][8]
70  __attribute__((aligned(16)));
71 //RX buffer descriptors
72 static uint32_t rxBufferDesc[S32K148_ETH_RX_BUFFER_COUNT][8]
73  __attribute__((aligned(16)));
74 
75 #endif
76 
77 //TX buffer index
78 static uint_t txBufferIndex;
79 //RX buffer index
80 static uint_t rxBufferIndex;
81 
82 
83 /**
84  * @brief S32K148 Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief S32K148 Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117  uint32_t value;
118 
119  //Debug message
120  TRACE_INFO("Initializing S32K148 Ethernet MAC...\r\n");
121 
122  //Save underlying network interface
123  nicDriverInterface = interface;
124 
125  //Disable MPU
126  MPU->CESR &= ~MPU_CESR_VLD_MASK;
127 
128  //Enable external reference clock
129  SIM->MISCTRL0 &= ~(SIM_MISCTRL0_RMII_CLK_SEL_MASK |
130  SIM_MISCTRL0_RMII_CLK_OBE_MASK);
131 
132  //Enable ENET peripheral clock
133  PCC->PCCn[PCC_ENET_INDEX] |= PCC_PCCn_CGC_MASK;
134 
135  //GPIO configuration
136  s32k148EthInitGpio(interface);
137 
138  //Reset ENET module
139  ENET->ECR = ENET_ECR_RESET_MASK;
140  //Wait for the reset to complete
141  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
142  {
143  }
144 
145  //Receive control register
146  ENET->RCR = ENET_RCR_MAX_FL(S32K148_ETH_RX_BUFFER_SIZE) |
147  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
148 
149  //Transmit control register
150  ENET->TCR = 0;
151  //Configure MDC clock frequency
152  ENET->MSCR = ENET_MSCR_MII_SPEED(23);
153 
154  //Valid Ethernet PHY or switch driver?
155  if(interface->phyDriver != NULL)
156  {
157  //Ethernet PHY initialization
158  error = interface->phyDriver->init(interface);
159  }
160  else if(interface->switchDriver != NULL)
161  {
162  //Ethernet switch initialization
163  error = interface->switchDriver->init(interface);
164  }
165  else
166  {
167  //The interface is not properly configured
168  error = ERROR_FAILURE;
169  }
170 
171  //Any error to report?
172  if(error)
173  {
174  return error;
175  }
176 
177  //Set the MAC address of the station (upper 16 bits)
178  value = interface->macAddr.b[5];
179  value |= (interface->macAddr.b[4] << 8);
180  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
181 
182  //Set the MAC address of the station (lower 32 bits)
183  value = interface->macAddr.b[3];
184  value |= (interface->macAddr.b[2] << 8);
185  value |= (interface->macAddr.b[1] << 16);
186  value |= (interface->macAddr.b[0] << 24);
187  ENET->PALR = ENET_PALR_PADDR1(value);
188 
189  //Hash table for unicast address filtering
190  ENET->IALR = 0;
191  ENET->IAUR = 0;
192  //Hash table for multicast address filtering
193  ENET->GALR = 0;
194  ENET->GAUR = 0;
195 
196  //Disable transmit accelerator functions
197  ENET->TACC = 0;
198  //Disable receive accelerator functions
199  ENET->RACC = 0;
200 
201  //Use enhanced buffer descriptors
202  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
203 
204  //Reset statistics counters
205  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
206  ENET->MIBC = 0;
207 
208  //Initialize buffer descriptors
209  s32k148EthInitBufferDesc(interface);
210 
211  //Clear any pending interrupts
212  ENET->EIR = 0xFFFFFFFF;
213  //Enable desired interrupts
214  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
215 
216  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
217  NVIC_SetPriorityGrouping(S32K148_ETH_IRQ_PRIORITY_GROUPING);
218 
219  //Configure ENET transmit interrupt priority
220  NVIC_SetPriority(ENET_TX_IRQn, NVIC_EncodePriority(S32K148_ETH_IRQ_PRIORITY_GROUPING,
222 
223  //Configure ENET receive interrupt priority
224  NVIC_SetPriority(ENET_RX_IRQn, NVIC_EncodePriority(S32K148_ETH_IRQ_PRIORITY_GROUPING,
226 
227  //Configure ENET error interrupt priority
228  NVIC_SetPriority(ENET_ERR_IRQn, NVIC_EncodePriority(S32K148_ETH_IRQ_PRIORITY_GROUPING,
230 
231  //Enable Ethernet MAC
232  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
233  //Instruct the DMA to poll the receive descriptor list
234  ENET->RDAR = ENET_RDAR_RDAR_MASK;
235 
236  //Accept any packets from the upper layer
237  osSetEvent(&interface->nicTxEvent);
238 
239  //Successful initialization
240  return NO_ERROR;
241 }
242 
243 
244 //S32K148-EVB evaluation board?
245 #if defined(USE_S32K148_EVB)
246 
247 /**
248  * @brief GPIO configuration
249  * @param[in] interface Underlying network interface
250  **/
251 
252 void s32k148EthInitGpio(NetInterface *interface)
253 {
254  //Enable PARTA, PORTB, PORTC and PORTD peripheral clocks
255  PCC->PCCn[PCC_PORTA_INDEX] = PCC_PCCn_CGC_MASK;
256  PCC->PCCn[PCC_PORTB_INDEX] = PCC_PCCn_CGC_MASK;
257  PCC->PCCn[PCC_PORTC_INDEX] = PCC_PCCn_CGC_MASK;
258  PCC->PCCn[PCC_PORTD_INDEX] = PCC_PCCn_CGC_MASK;
259 
260  //Configure RMII_RXD1 (PTC0)
261  PORTC->PCR[0] = PORT_PCR_MUX(4);
262  //Configure RMII_RXD0 (PTC1)
263  PORTC->PCR[1] = PORT_PCR_MUX(5);
264  //Configure RMII_TXD0 (PTC2)
265  PORTC->PCR[2] = PORT_PCR_MUX(5);
266  //Configure RMII_RXER (PTC16)
267  //PORTC->PCR[16] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK;
268  //Configure RMII_CRS_DV (PTC17)
269  PORTC->PCR[17] = PORT_PCR_MUX(5);
270  //Configure RMII_TXD1 (PTD7)
271  PORTD->PCR[7] = PORT_PCR_MUX(5);
272  //Configure RMII_REF_CLK (PTD11)
273  PORTD->PCR[11] = PORT_PCR_MUX(5);
274  //Configure RMII_TXEN (PTD12)
275  PORTD->PCR[12] = PORT_PCR_MUX(5);
276 
277  //Configure RMII_MDIO (PTB4)
278  PORTB->PCR[4] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
279  //Configure RMII_MDC (PTB5)
280  PORTB->PCR[5] = PORT_PCR_MUX(7);
281 
282  //Configure ENET_RESET (PTA17) as an output
283  PORTA->PCR[17] = PORT_PCR_MUX(1);
284  PTA->PDDR |= (1 << 17);
285 
286  //Reset PHY transceiver
287  PTA->PCOR |= (1 << 17);
288  sleep(10);
289  PTA->PSOR |= (1 << 17);
290  sleep(10);
291 }
292 
293 #endif
294 
295 
296 /**
297  * @brief Initialize buffer descriptors
298  * @param[in] interface Underlying network interface
299  **/
300 
302 {
303  uint_t i;
304  uint32_t address;
305 
306  //Clear TX and RX buffer descriptors
307  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
308  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
309 
310  //Initialize TX buffer descriptors
311  for(i = 0; i < S32K148_ETH_TX_BUFFER_COUNT; i++)
312  {
313  //Calculate the address of the current TX buffer
314  address = (uint32_t) txBuffer[i];
315  //Transmit buffer address
316  txBufferDesc[i][1] = address;
317  //Generate interrupts
318  txBufferDesc[i][2] = ENET_TBD2_INT;
319  }
320 
321  //Mark the last descriptor entry with the wrap flag
322  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
323  //Initialize TX buffer index
324  txBufferIndex = 0;
325 
326  //Initialize RX buffer descriptors
327  for(i = 0; i < S32K148_ETH_RX_BUFFER_COUNT; i++)
328  {
329  //Calculate the address of the current RX buffer
330  address = (uint32_t) rxBuffer[i];
331  //The descriptor is initially owned by the DMA
332  rxBufferDesc[i][0] = ENET_RBD0_E;
333  //Receive buffer address
334  rxBufferDesc[i][1] = address;
335  //Generate interrupts
336  rxBufferDesc[i][2] = ENET_RBD2_INT;
337  }
338 
339  //Mark the last descriptor entry with the wrap flag
340  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
341  //Initialize RX buffer index
342  rxBufferIndex = 0;
343 
344  //Start location of the TX descriptor list
345  ENET->TDSR = (uint32_t) txBufferDesc;
346  //Start location of the RX descriptor list
347  ENET->RDSR = (uint32_t) rxBufferDesc;
348  //Maximum receive buffer size
349  ENET->MRBR = S32K148_ETH_RX_BUFFER_SIZE;
350 }
351 
352 
353 /**
354  * @brief S32K148 Ethernet MAC timer handler
355  *
356  * This routine is periodically called by the TCP/IP stack to handle periodic
357  * operations such as polling the link state
358  *
359  * @param[in] interface Underlying network interface
360  **/
361 
362 void s32k148EthTick(NetInterface *interface)
363 {
364  //Valid Ethernet PHY or switch driver?
365  if(interface->phyDriver != NULL)
366  {
367  //Handle periodic operations
368  interface->phyDriver->tick(interface);
369  }
370  else if(interface->switchDriver != NULL)
371  {
372  //Handle periodic operations
373  interface->switchDriver->tick(interface);
374  }
375  else
376  {
377  //Just for sanity
378  }
379 }
380 
381 
382 /**
383  * @brief Enable interrupts
384  * @param[in] interface Underlying network interface
385  **/
386 
388 {
389  //Enable Ethernet MAC interrupts
390  NVIC_EnableIRQ(ENET_TX_IRQn);
391  NVIC_EnableIRQ(ENET_RX_IRQn);
392  NVIC_EnableIRQ(ENET_ERR_IRQn);
393 
394 
395  //Valid Ethernet PHY or switch driver?
396  if(interface->phyDriver != NULL)
397  {
398  //Enable Ethernet PHY interrupts
399  interface->phyDriver->enableIrq(interface);
400  }
401  else if(interface->switchDriver != NULL)
402  {
403  //Enable Ethernet switch interrupts
404  interface->switchDriver->enableIrq(interface);
405  }
406  else
407  {
408  //Just for sanity
409  }
410 }
411 
412 
413 /**
414  * @brief Disable interrupts
415  * @param[in] interface Underlying network interface
416  **/
417 
419 {
420  //Disable Ethernet MAC interrupts
421  NVIC_DisableIRQ(ENET_TX_IRQn);
422  NVIC_DisableIRQ(ENET_RX_IRQn);
423  NVIC_DisableIRQ(ENET_ERR_IRQn);
424 
425 
426  //Valid Ethernet PHY or switch driver?
427  if(interface->phyDriver != NULL)
428  {
429  //Disable Ethernet PHY interrupts
430  interface->phyDriver->disableIrq(interface);
431  }
432  else if(interface->switchDriver != NULL)
433  {
434  //Disable Ethernet switch interrupts
435  interface->switchDriver->disableIrq(interface);
436  }
437  else
438  {
439  //Just for sanity
440  }
441 }
442 
443 
444 /**
445  * @brief Ethernet MAC transmit interrupt
446  **/
447 
449 {
450  bool_t flag;
451 
452  //Interrupt service routine prologue
453  osEnterIsr();
454 
455  //This flag will be set if a higher priority task must be woken
456  flag = FALSE;
457 
458  //Packet transmitted?
459  if((ENET->EIR & ENET_EIR_TXF_MASK) != 0)
460  {
461  //Clear TXF interrupt flag
462  ENET->EIR = ENET_EIR_TXF_MASK;
463 
464  //Check whether the TX buffer is available for writing
465  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
466  {
467  //Notify the TCP/IP stack that the transmitter is ready to send
468  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
469  }
470 
471  //Instruct the DMA to poll the transmit descriptor list
472  ENET->TDAR = ENET_TDAR_TDAR_MASK;
473  }
474 
475  //Interrupt service routine epilogue
476  osExitIsr(flag);
477 }
478 
479 
480 /**
481  * @brief Ethernet MAC receive interrupt
482  **/
483 
485 {
486  bool_t flag;
487 
488  //Interrupt service routine prologue
489  osEnterIsr();
490 
491  //This flag will be set if a higher priority task must be woken
492  flag = FALSE;
493 
494  //Packet received?
495  if((ENET->EIR & ENET_EIR_RXF_MASK) != 0)
496  {
497  //Disable RXF interrupt
498  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
499 
500  //Set event flag
501  nicDriverInterface->nicEvent = TRUE;
502  //Notify the TCP/IP stack of the event
503  flag = osSetEventFromIsr(&netEvent);
504  }
505 
506  //Interrupt service routine epilogue
507  osExitIsr(flag);
508 }
509 
510 
511 /**
512  * @brief Ethernet MAC error interrupt
513  **/
514 
516 {
517  bool_t flag;
518 
519  //Interrupt service routine prologue
520  osEnterIsr();
521 
522  //This flag will be set if a higher priority task must be woken
523  flag = FALSE;
524 
525  //System bus error?
526  if((ENET->EIR & ENET_EIR_EBERR_MASK) != 0)
527  {
528  //Disable EBERR interrupt
529  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
530 
531  //Set event flag
532  nicDriverInterface->nicEvent = TRUE;
533  //Notify the TCP/IP stack of the event
534  flag |= osSetEventFromIsr(&netEvent);
535  }
536 
537  //Interrupt service routine epilogue
538  osExitIsr(flag);
539 }
540 
541 
542 /**
543  * @brief S32K148 Ethernet MAC event handler
544  * @param[in] interface Underlying network interface
545  **/
546 
548 {
549  error_t error;
550  uint32_t status;
551 
552  //Read interrupt event register
553  status = ENET->EIR;
554 
555  //Packet received?
556  if((status & ENET_EIR_RXF_MASK) != 0)
557  {
558  //Clear RXF interrupt flag
559  ENET->EIR = ENET_EIR_RXF_MASK;
560 
561  //Process all pending packets
562  do
563  {
564  //Read incoming packet
565  error = s32k148EthReceivePacket(interface);
566 
567  //No more data in the receive buffer?
568  } while(error != ERROR_BUFFER_EMPTY);
569  }
570 
571  //System bus error?
572  if((status & ENET_EIR_EBERR_MASK) != 0)
573  {
574  //Clear EBERR interrupt flag
575  ENET->EIR = ENET_EIR_EBERR_MASK;
576 
577  //Disable Ethernet MAC
578  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
579  //Reset buffer descriptors
580  s32k148EthInitBufferDesc(interface);
581  //Resume normal operation
582  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
583  //Instruct the DMA to poll the receive descriptor list
584  ENET->RDAR = ENET_RDAR_RDAR_MASK;
585  }
586 
587  //Re-enable Ethernet MAC interrupts
588  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
589 }
590 
591 
592 /**
593  * @brief Send a packet
594  * @param[in] interface Underlying network interface
595  * @param[in] buffer Multi-part buffer containing the data to send
596  * @param[in] offset Offset to the first data byte
597  * @param[in] ancillary Additional options passed to the stack along with
598  * the packet
599  * @return Error code
600  **/
601 
603  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
604 {
605  size_t length;
606 
607  //Retrieve the length of the packet
608  length = netBufferGetLength(buffer) - offset;
609 
610  //Check the frame length
612  {
613  //The transmitter can accept another packet
614  osSetEvent(&interface->nicTxEvent);
615  //Report an error
616  return ERROR_INVALID_LENGTH;
617  }
618 
619  //Make sure the current buffer is available for writing
620  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
621  {
622  return ERROR_FAILURE;
623  }
624 
625  //Copy user data to the transmit buffer
626  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
627 
628  //Clear BDU flag
629  txBufferDesc[txBufferIndex][4] = 0;
630 
631  //Check current index
632  if(txBufferIndex < (S32K148_ETH_TX_BUFFER_COUNT - 1))
633  {
634  //Give the ownership of the descriptor to the DMA engine
635  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
637 
638  //Point to the next buffer
639  txBufferIndex++;
640  }
641  else
642  {
643  //Give the ownership of the descriptor to the DMA engine
644  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
646 
647  //Wrap around
648  txBufferIndex = 0;
649  }
650 
651  //Instruct the DMA to poll the transmit descriptor list
652  ENET->TDAR = ENET_TDAR_TDAR_MASK;
653 
654  //Check whether the next buffer is available for writing
655  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
656  {
657  //The transmitter can accept another packet
658  osSetEvent(&interface->nicTxEvent);
659  }
660 
661  //Successful processing
662  return NO_ERROR;
663 }
664 
665 
666 /**
667  * @brief Receive a packet
668  * @param[in] interface Underlying network interface
669  * @return Error code
670  **/
671 
673 {
674  error_t error;
675  size_t n;
676  NetRxAncillary ancillary;
677 
678  //Make sure the current buffer is available for reading
679  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
680  {
681  //The frame should not span multiple buffers
682  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
683  {
684  //Check whether an error occurred
685  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
687  {
688  //Retrieve the length of the frame
689  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
690  //Limit the number of data to read
692 
693  //Additional options can be passed to the stack along with the packet
694  ancillary = NET_DEFAULT_RX_ANCILLARY;
695 
696  //Pass the packet to the upper layer
697  nicProcessPacket(interface, rxBuffer[rxBufferIndex], n, &ancillary);
698 
699  //Valid packet received
700  error = NO_ERROR;
701  }
702  else
703  {
704  //The received packet contains an error
705  error = ERROR_INVALID_PACKET;
706  }
707  }
708  else
709  {
710  //The packet is not valid
711  error = ERROR_INVALID_PACKET;
712  }
713 
714  //Clear BDU flag
715  rxBufferDesc[rxBufferIndex][4] = 0;
716 
717  //Check current index
718  if(rxBufferIndex < (S32K148_ETH_RX_BUFFER_COUNT - 1))
719  {
720  //Give the ownership of the descriptor back to the DMA engine
721  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
722  //Point to the next buffer
723  rxBufferIndex++;
724  }
725  else
726  {
727  //Give the ownership of the descriptor back to the DMA engine
728  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
729  //Wrap around
730  rxBufferIndex = 0;
731  }
732 
733  //Instruct the DMA to poll the receive descriptor list
734  ENET->RDAR = ENET_RDAR_RDAR_MASK;
735  }
736  else
737  {
738  //No more data in the receive buffer
739  error = ERROR_BUFFER_EMPTY;
740  }
741 
742  //Return status code
743  return error;
744 }
745 
746 
747 /**
748  * @brief Configure MAC address filtering
749  * @param[in] interface Underlying network interface
750  * @return Error code
751  **/
752 
754 {
755  uint_t i;
756  uint_t k;
757  uint32_t crc;
758  uint32_t value;
759  uint32_t unicastHashTable[2];
760  uint32_t multicastHashTable[2];
761  MacFilterEntry *entry;
762 
763  //Debug message
764  TRACE_DEBUG("Updating MAC filter...\r\n");
765 
766  //Set the MAC address of the station (upper 16 bits)
767  value = interface->macAddr.b[5];
768  value |= (interface->macAddr.b[4] << 8);
769  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
770 
771  //Set the MAC address of the station (lower 32 bits)
772  value = interface->macAddr.b[3];
773  value |= (interface->macAddr.b[2] << 8);
774  value |= (interface->macAddr.b[1] << 16);
775  value |= (interface->macAddr.b[0] << 24);
776  ENET->PALR = ENET_PALR_PADDR1(value);
777 
778  //Clear hash table (unicast address filtering)
779  unicastHashTable[0] = 0;
780  unicastHashTable[1] = 0;
781 
782  //Clear hash table (multicast address filtering)
783  multicastHashTable[0] = 0;
784  multicastHashTable[1] = 0;
785 
786  //The MAC address filter contains the list of MAC addresses to accept
787  //when receiving an Ethernet frame
788  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
789  {
790  //Point to the current entry
791  entry = &interface->macAddrFilter[i];
792 
793  //Valid entry?
794  if(entry->refCount > 0)
795  {
796  //Compute CRC over the current MAC address
797  crc = s32k148EthCalcCrc(&entry->addr, sizeof(MacAddr));
798 
799  //The upper 6 bits in the CRC register are used to index the
800  //contents of the hash table
801  k = (crc >> 26) & 0x3F;
802 
803  //Multicast address?
804  if(macIsMulticastAddr(&entry->addr))
805  {
806  //Update the multicast hash table
807  multicastHashTable[k / 32] |= (1 << (k % 32));
808  }
809  else
810  {
811  //Update the unicast hash table
812  unicastHashTable[k / 32] |= (1 << (k % 32));
813  }
814  }
815  }
816 
817  //Write the hash table (unicast address filtering)
818  ENET->IALR = unicastHashTable[0];
819  ENET->IAUR = unicastHashTable[1];
820 
821  //Write the hash table (multicast address filtering)
822  ENET->GALR = multicastHashTable[0];
823  ENET->GAUR = multicastHashTable[1];
824 
825  //Debug message
826  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
827  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
828  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
829  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
830 
831  //Successful processing
832  return NO_ERROR;
833 }
834 
835 
836 /**
837  * @brief Adjust MAC configuration parameters for proper operation
838  * @param[in] interface Underlying network interface
839  * @return Error code
840  **/
841 
843 {
844  //Disable Ethernet MAC while modifying configuration registers
845  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
846 
847  //10BASE-T or 100BASE-TX operation mode?
848  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
849  {
850  //100 Mbps operation
851  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
852  }
853  else
854  {
855  //10 Mbps operation
856  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
857  }
858 
859  //Half-duplex or full-duplex mode?
860  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
861  {
862  //Full-duplex mode
863  ENET->TCR |= ENET_TCR_FDEN_MASK;
864  //Receive path operates independently of transmit
865  ENET->RCR &= ~ENET_RCR_DRT_MASK;
866  }
867  else
868  {
869  //Half-duplex mode
870  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
871  //Disable reception of frames while transmitting
872  ENET->RCR |= ENET_RCR_DRT_MASK;
873  }
874 
875  //Reset buffer descriptors
876  s32k148EthInitBufferDesc(interface);
877 
878  //Re-enable Ethernet MAC
879  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
880  //Instruct the DMA to poll the receive descriptor list
881  ENET->RDAR = ENET_RDAR_RDAR_MASK;
882 
883  //Successful processing
884  return NO_ERROR;
885 }
886 
887 
888 /**
889  * @brief Write PHY register
890  * @param[in] opcode Access type (2 bits)
891  * @param[in] phyAddr PHY address (5 bits)
892  * @param[in] regAddr Register address (5 bits)
893  * @param[in] data Register value
894  **/
895 
896 void s32k148EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
897  uint8_t regAddr, uint16_t data)
898 {
899  uint32_t temp;
900 
901  //Valid opcode?
902  if(opcode == SMI_OPCODE_WRITE)
903  {
904  //Set up a write operation
905  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
906  //PHY address
907  temp |= ENET_MMFR_PA(phyAddr);
908  //Register address
909  temp |= ENET_MMFR_RA(regAddr);
910  //Register value
911  temp |= ENET_MMFR_DATA(data);
912 
913  //Clear MII interrupt flag
914  ENET->EIR = ENET_EIR_MII_MASK;
915  //Start a write operation
916  ENET->MMFR = temp;
917 
918  //Wait for the write to complete
919  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
920  {
921  }
922  }
923  else
924  {
925  //The MAC peripheral only supports standard Clause 22 opcodes
926  }
927 }
928 
929 
930 /**
931  * @brief Read PHY register
932  * @param[in] opcode Access type (2 bits)
933  * @param[in] phyAddr PHY address (5 bits)
934  * @param[in] regAddr Register address (5 bits)
935  * @return Register value
936  **/
937 
938 uint16_t s32k148EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
939  uint8_t regAddr)
940 {
941  uint16_t data;
942  uint32_t temp;
943 
944  //Valid opcode?
945  if(opcode == SMI_OPCODE_READ)
946  {
947  //Set up a read operation
948  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
949  //PHY address
950  temp |= ENET_MMFR_PA(phyAddr);
951  //Register address
952  temp |= ENET_MMFR_RA(regAddr);
953 
954  //Clear MII interrupt flag
955  ENET->EIR = ENET_EIR_MII_MASK;
956  //Start a read operation
957  ENET->MMFR = temp;
958 
959  //Wait for the read to complete
960  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
961  {
962  }
963 
964  //Get register value
965  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
966  }
967  else
968  {
969  //The MAC peripheral only supports standard Clause 22 opcodes
970  data = 0;
971  }
972 
973  //Return the value of the PHY register
974  return data;
975 }
976 
977 
978 /**
979  * @brief CRC calculation
980  * @param[in] data Pointer to the data over which to calculate the CRC
981  * @param[in] length Number of bytes to process
982  * @return Resulting CRC value
983  **/
984 
985 uint32_t s32k148EthCalcCrc(const void *data, size_t length)
986 {
987  uint_t i;
988  uint_t j;
989  uint32_t crc;
990  const uint8_t *p;
991 
992  //Point to the data over which to calculate the CRC
993  p = (uint8_t *) data;
994  //CRC preset value
995  crc = 0xFFFFFFFF;
996 
997  //Loop through data
998  for(i = 0; i < length; i++)
999  {
1000  //Update CRC value
1001  crc ^= p[i];
1002  //The message is processed bit by bit
1003  for(j = 0; j < 8; j++)
1004  {
1005  if((crc & 0x01) != 0)
1006  {
1007  crc = (crc >> 1) ^ 0xEDB88320;
1008  }
1009  else
1010  {
1011  crc = crc >> 1;
1012  }
1013  }
1014  }
1015 
1016  //Return CRC value
1017  return crc;
1018 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
void s32k148EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
#define ENET_TBD0_L
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define ENET_RBD0_DATA_LENGTH
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define sleep(delay)
Definition: os_port.h:251
__start_packed struct @5 MacAddr
MAC address.
#define S32K148_ETH_TX_BUFFER_SIZE
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
void ENET_ERR_IRQHandler(void)
Ethernet MAC error interrupt.
error_t s32k148EthInit(NetInterface *interface)
S32K148 Ethernet MAC initialization.
#define ENET_TBD0_DATA_LENGTH
#define ENET_TBD0_W
#define ENET_TBD0_TC
void s32k148EthEventHandler(NetInterface *interface)
S32K148 Ethernet MAC event handler.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define S32K148_ETH_TX_BUFFER_COUNT
#define osExitIsr(flag)
NXP S32K148 Ethernet MAC driver.
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define ENET_RBD0_L
#define FALSE
Definition: os_port.h:46
void s32k148EthTick(NetInterface *interface)
S32K148 Ethernet MAC timer handler.
uint16_t s32k148EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MPU_CESR_VLD_MASK
error_t
Error codes.
Definition: error.h:42
#define S32K148_ETH_IRQ_SUB_PRIORITY
uint8_t value[]
Definition: tcp.h:332
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
error_t s32k148EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define ENET_RBD0_W
#define ENET_RBD0_TR
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
error_t s32k148EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
error_t s32k148EthReceivePacket(NetInterface *interface)
Receive a packet.
void s32k148EthInitGpio(NetInterface *interface)
#define S32K148_ETH_IRQ_GROUP_PRIORITY
const NicDriver s32k148EthDriver
S32K148 Ethernet MAC driver.
#define rxBuffer
void s32k148EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define ENET_RBD0_LG
uint32_t s32k148EthCalcCrc(const void *data, size_t length)
CRC calculation.
void ENET_RX_IRQHandler(void)
Ethernet MAC receive interrupt.
void s32k148EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define TRACE_DEBUG(...)
Definition: debug.h:107
uint16_t regAddr
#define ENET_RBD0_CR
#define ENET_RBD0_OV
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define osEnterIsr()
#define MPU
#define ENET_TBD0_R
#define ENET_TBD2_INT
#define S32K148_ETH_RX_BUFFER_SIZE
#define ENET_RBD0_E
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define S32K148_ETH_RX_BUFFER_COUNT
#define S32K148_ETH_IRQ_PRIORITY_GROUPING
void s32k148EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t s32k148EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
unsigned int uint_t
Definition: compiler_port.h:45
#define osMemset(p, value, length)
Definition: os_port.h:128
TCP/IP stack core.
void ENET_TX_IRQHandler(void)
Ethernet MAC transmit interrupt.
NIC driver.
Definition: nic.h:257
#define ENET_RBD0_NO
#define ENET_RBD2_INT
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
Ethernet interface.
Definition: nic.h:82