32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "fsl_device_registers.h"
44 #if defined(__ICCARM__)
47 #pragma data_alignment = 16
50 #pragma data_alignment = 16
53 #pragma data_alignment = 16
56 #pragma data_alignment = 16
78 static uint_t txBufferIndex;
80 static uint_t rxBufferIndex;
120 TRACE_INFO(
"Initializing S32K1 Ethernet MAC...\r\n");
123 nicDriverInterface = interface;
129 SIM->MISCTRL0 &= ~(SIM_MISCTRL0_RMII_CLK_SEL_MASK |
130 SIM_MISCTRL0_RMII_CLK_OBE_MASK);
133 PCC->PCCn[PCC_ENET_INDEX] |= PCC_PCCn_CGC_MASK;
139 ENET->ECR = ENET_ECR_RESET_MASK;
141 while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
147 ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
152 ENET->MSCR = ENET_MSCR_MII_SPEED(23);
155 if(interface->phyDriver != NULL)
158 error = interface->phyDriver->init(interface);
160 else if(interface->switchDriver != NULL)
163 error = interface->switchDriver->init(interface);
178 value = interface->macAddr.b[5];
179 value |= (interface->macAddr.b[4] << 8);
180 ENET->PAUR = ENET_PAUR_PADDR2(
value) | ENET_PAUR_TYPE(0x8808);
183 value = interface->macAddr.b[3];
184 value |= (interface->macAddr.b[2] << 8);
185 value |= (interface->macAddr.b[1] << 16);
186 value |= (interface->macAddr.b[0] << 24);
187 ENET->PALR = ENET_PALR_PADDR1(
value);
202 ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
205 ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
212 ENET->EIR = 0xFFFFFFFF;
214 ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
232 ENET->ECR |= ENET_ECR_ETHEREN_MASK;
234 ENET->RDAR = ENET_RDAR_RDAR_MASK;
252 #if defined(USE_S32K148_EVB_Q176)
254 PCC->PCCn[PCC_PORTA_INDEX] = PCC_PCCn_CGC_MASK;
255 PCC->PCCn[PCC_PORTB_INDEX] = PCC_PCCn_CGC_MASK;
256 PCC->PCCn[PCC_PORTC_INDEX] = PCC_PCCn_CGC_MASK;
257 PCC->PCCn[PCC_PORTD_INDEX] = PCC_PCCn_CGC_MASK;
260 PORTC->PCR[0] = PORT_PCR_MUX(4);
262 PORTC->PCR[1] = PORT_PCR_MUX(5);
264 PORTC->PCR[2] = PORT_PCR_MUX(5);
268 PORTC->PCR[17] = PORT_PCR_MUX(5);
270 PORTD->PCR[7] = PORT_PCR_MUX(5);
272 PORTD->PCR[11] = PORT_PCR_MUX(5);
274 PORTD->PCR[12] = PORT_PCR_MUX(5);
277 PORTB->PCR[4] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
279 PORTB->PCR[5] = PORT_PCR_MUX(7);
282 PORTA->PCR[17] = PORT_PCR_MUX(1);
283 PTA->PDDR |= (1 << 17);
286 PTA->PCOR |= (1 << 17);
288 PTA->PSOR |= (1 << 17);
305 osMemset(txBufferDesc, 0,
sizeof(txBufferDesc));
306 osMemset(rxBufferDesc, 0,
sizeof(rxBufferDesc));
343 ENET->TDSR = (uint32_t) txBufferDesc;
345 ENET->RDSR = (uint32_t) rxBufferDesc;
363 if(interface->phyDriver != NULL)
366 interface->phyDriver->tick(interface);
368 else if(interface->switchDriver != NULL)
371 interface->switchDriver->tick(interface);
388 NVIC_EnableIRQ(ENET_TX_IRQn);
389 NVIC_EnableIRQ(ENET_RX_IRQn);
390 NVIC_EnableIRQ(ENET_ERR_IRQn);
393 if(interface->phyDriver != NULL)
396 interface->phyDriver->enableIrq(interface);
398 else if(interface->switchDriver != NULL)
401 interface->switchDriver->enableIrq(interface);
418 NVIC_DisableIRQ(ENET_TX_IRQn);
419 NVIC_DisableIRQ(ENET_RX_IRQn);
420 NVIC_DisableIRQ(ENET_ERR_IRQn);
423 if(interface->phyDriver != NULL)
426 interface->phyDriver->disableIrq(interface);
428 else if(interface->switchDriver != NULL)
431 interface->switchDriver->disableIrq(interface);
455 if((ENET->EIR & ENET_EIR_TXF_MASK) != 0)
458 ENET->EIR = ENET_EIR_TXF_MASK;
461 if((txBufferDesc[txBufferIndex][0] &
ENET_TBD0_R) == 0)
468 ENET->TDAR = ENET_TDAR_TDAR_MASK;
491 if((ENET->EIR & ENET_EIR_RXF_MASK) != 0)
494 ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
497 nicDriverInterface->nicEvent =
TRUE;
522 if((ENET->EIR & ENET_EIR_EBERR_MASK) != 0)
525 ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
528 nicDriverInterface->nicEvent =
TRUE;
552 if((status & ENET_EIR_RXF_MASK) != 0)
555 ENET->EIR = ENET_EIR_RXF_MASK;
568 if((status & ENET_EIR_EBERR_MASK) != 0)
571 ENET->EIR = ENET_EIR_EBERR_MASK;
574 ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
578 ENET->ECR |= ENET_ECR_ETHEREN_MASK;
580 ENET->RDAR = ENET_RDAR_RDAR_MASK;
584 ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
616 if((txBufferDesc[txBufferIndex][0] &
ENET_TBD0_R) != 0)
625 txBufferDesc[txBufferIndex][4] = 0;
648 ENET->TDAR = ENET_TDAR_TDAR_MASK;
651 if((txBufferDesc[txBufferIndex][0] &
ENET_TBD0_R) == 0)
675 if((rxBufferDesc[rxBufferIndex][0] &
ENET_RBD0_E) == 0)
678 if((rxBufferDesc[rxBufferIndex][0] &
ENET_RBD0_L) != 0)
711 rxBufferDesc[rxBufferIndex][4] = 0;
730 ENET->RDAR = ENET_RDAR_RDAR_MASK;
755 uint32_t unicastHashTable[2];
756 uint32_t multicastHashTable[2];
763 value = interface->macAddr.b[5];
764 value |= (interface->macAddr.b[4] << 8);
765 ENET->PAUR = ENET_PAUR_PADDR2(
value) | ENET_PAUR_TYPE(0x8808);
768 value = interface->macAddr.b[3];
769 value |= (interface->macAddr.b[2] << 8);
770 value |= (interface->macAddr.b[1] << 16);
771 value |= (interface->macAddr.b[0] << 24);
772 ENET->PALR = ENET_PALR_PADDR1(
value);
775 unicastHashTable[0] = 0;
776 unicastHashTable[1] = 0;
779 multicastHashTable[0] = 0;
780 multicastHashTable[1] = 0;
787 entry = &interface->macAddrFilter[i];
797 k = (crc >> 26) & 0x3F;
803 multicastHashTable[k / 32] |= (1 << (k % 32));
808 unicastHashTable[k / 32] |= (1 << (k % 32));
814 ENET->IALR = unicastHashTable[0];
815 ENET->IAUR = unicastHashTable[1];
818 ENET->GALR = multicastHashTable[0];
819 ENET->GAUR = multicastHashTable[1];
822 TRACE_DEBUG(
" IALR = %08" PRIX32
"\r\n", ENET->IALR);
823 TRACE_DEBUG(
" IAUR = %08" PRIX32
"\r\n", ENET->IAUR);
824 TRACE_DEBUG(
" GALR = %08" PRIX32
"\r\n", ENET->GALR);
825 TRACE_DEBUG(
" GAUR = %08" PRIX32
"\r\n", ENET->GAUR);
841 ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
847 ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
852 ENET->RCR |= ENET_RCR_RMII_10T_MASK;
859 ENET->TCR |= ENET_TCR_FDEN_MASK;
861 ENET->RCR &= ~ENET_RCR_DRT_MASK;
866 ENET->TCR &= ~ENET_TCR_FDEN_MASK;
868 ENET->RCR |= ENET_RCR_DRT_MASK;
875 ENET->ECR |= ENET_ECR_ETHEREN_MASK;
877 ENET->RDAR = ENET_RDAR_RDAR_MASK;
901 temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
903 temp |= ENET_MMFR_PA(phyAddr);
907 temp |= ENET_MMFR_DATA(
data);
910 ENET->EIR = ENET_EIR_MII_MASK;
915 while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
944 temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
946 temp |= ENET_MMFR_PA(phyAddr);
951 ENET->EIR = ENET_EIR_MII_MASK;
956 while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
961 data = ENET->MMFR & ENET_MMFR_DATA_MASK;
989 p = (uint8_t *)
data;
994 for(i = 0; i <
length; i++)
1000 for(j = 0; j < 8; j++)
1002 if((crc & 0x01) != 0)
1004 crc = (crc >> 1) ^ 0xEDB88320;