nuc472_eth_driver.c
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1 /**
2  * @file nuc472_eth_driver.c
3  * @brief Nuvoton NUC472 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "nuc472_442.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit DMA descriptors
53 #pragma data_alignment = 4
55 //Receive DMA descriptors
56 #pragma data_alignment = 4
58 
59 //Keil MDK-ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
64  __attribute__((aligned(4)));
65 //Receive buffer
67  __attribute__((aligned(4)));
68 //Transmit DMA descriptors
70  __attribute__((aligned(4)));
71 //Receive DMA descriptors
73  __attribute__((aligned(4)));
74 
75 #endif
76 
77 //Current transmit descriptor
78 static uint_t txIndex;
79 //Current receive descriptor
80 static uint_t rxIndex;
81 
82 
83 /**
84  * @brief NUC472 Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief NUC472 Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117 
118  //Debug message
119  TRACE_INFO("Initializing NUC472 Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable EMAC clock
125  CLK_EnableModuleClock(EMAC_MODULE);
126  //Select MDC clock frequency
127  CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(100));
128 
129  //Perform a software reset
130  EMAC->CTL |= EMAC_CTL_RST_Msk;
131  //Wait for the reset to complete
132  while((EMAC->CTL & EMAC_CTL_RST_Msk) != 0)
133  {
134  }
135 
136  //GPIO configuration
137  nuc472EthInitGpio(interface);
138 
139  //Valid Ethernet PHY or switch driver?
140  if(interface->phyDriver != NULL)
141  {
142  //Ethernet PHY initialization
143  error = interface->phyDriver->init(interface);
144  }
145  else if(interface->switchDriver != NULL)
146  {
147  //Ethernet switch initialization
148  error = interface->switchDriver->init(interface);
149  }
150  else
151  {
152  //The interface is not properly configured
153  error = ERROR_FAILURE;
154  }
155 
156  //Any error to report?
157  if(error)
158  {
159  return error;
160  }
161 
162  //Set the upper 32 bits of the MAC address
163  EMAC->CAM0M = interface->macAddr.b[3] |
164  (interface->macAddr.b[2] << 8) |
165  (interface->macAddr.b[1] << 16) |
166  (interface->macAddr.b[0] << 24);
167 
168  //Set the lower 16 bits of the MAC address
169  EMAC->CAM0L = (interface->macAddr.b[5] << 16) |
170  (interface->macAddr.b[4] << 24);
171 
172  //Enable the corresponding CAM entry
173  EMAC->CAMEN = EMAC_CAMEN_CAMxEN_Msk << 0;
174  //Accept broadcast and multicast packets
175  EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | EMAC_CAMCTL_ABP_Msk;
176 
177  //Maximum frame length that can be accepted
178  EMAC->MRFL = NUC472_ETH_RX_BUFFER_SIZE;
179 
180  //Initialize DMA descriptor lists
181  nuc472EthInitDmaDesc(interface);
182 
183  //Enable the desired MAC interrupts
184  EMAC->INTEN = EMAC_INTEN_TXCPIEN_Msk | EMAC_INTEN_TXIEN_Msk |
185  EMAC_INTEN_RXGDIEN_Msk | EMAC_INTEN_RXIEN_Msk;
186 
187  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
188  NVIC_SetPriorityGrouping(NUC472_ETH_IRQ_PRIORITY_GROUPING);
189 
190  //Configure EMAC transmit interrupt priority
191  NVIC_SetPriority(EMAC_TX_IRQn, NVIC_EncodePriority(NUC472_ETH_IRQ_PRIORITY_GROUPING,
193 
194  //Configure EMAC receive interrupt priority
195  NVIC_SetPriority(EMAC_RX_IRQn, NVIC_EncodePriority(NUC472_ETH_IRQ_PRIORITY_GROUPING,
197 
198  //Enable transmission and reception
199  EMAC->CTL |= EMAC_CTL_TXON_Msk | EMAC_CTL_RXON_Msk;
200 
201  //Accept any packets from the upper layer
202  osSetEvent(&interface->nicTxEvent);
203 
204  //Successful initialization
205  return NO_ERROR;
206 }
207 
208 
209 /**
210  * @brief GPIO configuration
211  * @param[in] interface Underlying network interface
212  **/
213 
214 __weak_func void nuc472EthInitGpio(NetInterface *interface)
215 {
216 //NuTiny-SDK-NUC472 or NuMaker-PFM-NUC472 evaluation board?
217 #if defined(USE_NUTINY_SDK_NUC472) || defined(USE_NUMAKER_PFM_NUC472)
218  uint32_t temp;
219 
220  //Select RMII interface mode
221  EMAC->CTL |= EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
222 
223  //Configure EMAC_MII_MDC (PB.14) and EMAC_MII_MDIO (PB.15)
224  temp = SYS->GPB_MFPH;
225  temp = (temp & ~SYS_GPB_MFPH_PB14MFP_Msk) | SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC;
226  temp = (temp & ~SYS_GPB_MFPH_PB15MFP_Msk) | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
227  SYS->GPB_MFPH = temp;
228 
229  //Configure EMAC_REFCLK (PC.0), EMAC_MII_RXERR (PC.1), EMAC_MII_RXDV (PC.2),
230  //EMAC_MII_RXD1 (PC.3), EMAC_MII_RXD0 (PC.4), EMAC_MII_TXD0 (PC.6) and
231  //EMAC_MII_TXD1 (PC.7)
232  temp = SYS->GPC_MFPL;
233  temp = (temp & ~SYS_GPC_MFPL_PC0MFP_Msk) | SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK;
234  temp = (temp & ~SYS_GPC_MFPL_PC1MFP_Msk) | SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR;
235  temp = (temp & ~SYS_GPC_MFPL_PC2MFP_Msk) | SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV;
236  temp = (temp & ~SYS_GPC_MFPL_PC3MFP_Msk) | SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1;
237  temp = (temp & ~SYS_GPC_MFPL_PC4MFP_Msk) | SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0;
238  temp = (temp & ~SYS_GPC_MFPL_PC6MFP_Msk) | SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0;
239  temp = (temp & ~SYS_GPC_MFPL_PC7MFP_Msk) | SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
240  SYS->GPC_MFPL = temp;
241 
242  //Configure EMAC_MII_TXEN (PC.8)
243  temp = SYS->GPC_MFPH;
244  temp = (temp & ~SYS_GPC_MFPH_PC8MFP_Msk) | SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
245  SYS->GPC_MFPH = temp;
246 
247  //Enable high slew rate on RMII output pins
248  PC->SLEWCTL |= GPIO_SLEWCTL_HSREN6_Msk | GPIO_SLEWCTL_HSREN7_Msk |
249  GPIO_SLEWCTL_HSREN8_Msk;
250 #endif
251 }
252 
253 
254 /**
255  * @brief Initialize DMA descriptor lists
256  * @param[in] interface Underlying network interface
257  **/
258 
260 {
261  uint_t i;
262 
263  //Initialize TX DMA descriptor list
264  for(i = 0; i < NUC472_ETH_TX_BUFFER_COUNT; i++)
265  {
266  //The descriptor is initially owned by the CPU
267  txDmaDesc[i].txdes0 = 0;
268  //Transmit buffer address
269  txDmaDesc[i].txdes1 = (uint32_t) txBuffer[i];
270  //Transmit frame status
271  txDmaDesc[i].txdes2 = 0;
272  //Next descriptor address
273  txDmaDesc[i].txdes3 = (uint32_t) &txDmaDesc[i + 1];
274  }
275 
276  //The last descriptor is chained to the first entry
277  txDmaDesc[i - 1].txdes3 = (uint32_t) &txDmaDesc[0];
278  //Initialize TX descriptor index
279  txIndex = 0;
280 
281  //Initialize RX DMA descriptor list
282  for(i = 0; i < NUC472_ETH_RX_BUFFER_COUNT; i++)
283  {
284  //The descriptor is initially owned by the DMA
285  rxDmaDesc[i].rxdes0 = EMAC_RXDES0_OWNER;
286  //Receive buffer address
287  rxDmaDesc[i].rxdes1 = (uint32_t) rxBuffer[i];
288  //Reserved field
289  rxDmaDesc[i].rxdes2 = 0;
290  //Next descriptor address
291  rxDmaDesc[i].rxdes3 = (uint32_t) &rxDmaDesc[i + 1];
292  }
293 
294  //The last descriptor is chained to the first entry
295  rxDmaDesc[i - 1].rxdes3 = (uint32_t) &rxDmaDesc[0];
296  //Initialize RX descriptor index
297  rxIndex = 0;
298 
299  //Start address of the TX descriptor list
300  EMAC->TXDSA = (uint32_t) txDmaDesc;
301  //Start address of the RX descriptor list
302  EMAC->RXDSA = (uint32_t) rxDmaDesc;
303 }
304 
305 
306 /**
307  * @brief NUC472 Ethernet MAC timer handler
308  *
309  * This routine is periodically called by the TCP/IP stack to handle periodic
310  * operations such as polling the link state
311  *
312  * @param[in] interface Underlying network interface
313  **/
314 
315 void nuc472EthTick(NetInterface *interface)
316 {
317  //Valid Ethernet PHY or switch driver?
318  if(interface->phyDriver != NULL)
319  {
320  //Handle periodic operations
321  interface->phyDriver->tick(interface);
322  }
323  else if(interface->switchDriver != NULL)
324  {
325  //Handle periodic operations
326  interface->switchDriver->tick(interface);
327  }
328  else
329  {
330  //Just for sanity
331  }
332 }
333 
334 
335 /**
336  * @brief Enable interrupts
337  * @param[in] interface Underlying network interface
338  **/
339 
341 {
342  //Enable Ethernet MAC interrupts
343  NVIC_EnableIRQ(EMAC_TX_IRQn);
344  NVIC_EnableIRQ(EMAC_RX_IRQn);
345 
346  //Valid Ethernet PHY or switch driver?
347  if(interface->phyDriver != NULL)
348  {
349  //Enable Ethernet PHY interrupts
350  interface->phyDriver->enableIrq(interface);
351  }
352  else if(interface->switchDriver != NULL)
353  {
354  //Enable Ethernet switch interrupts
355  interface->switchDriver->enableIrq(interface);
356  }
357  else
358  {
359  //Just for sanity
360  }
361 }
362 
363 
364 /**
365  * @brief Disable interrupts
366  * @param[in] interface Underlying network interface
367  **/
368 
370 {
371  //Disable Ethernet MAC interrupts
372  NVIC_DisableIRQ(EMAC_TX_IRQn);
373  NVIC_DisableIRQ(EMAC_RX_IRQn);
374 
375  //Valid Ethernet PHY or switch driver?
376  if(interface->phyDriver != NULL)
377  {
378  //Disable Ethernet PHY interrupts
379  interface->phyDriver->disableIrq(interface);
380  }
381  else if(interface->switchDriver != NULL)
382  {
383  //Disable Ethernet switch interrupts
384  interface->switchDriver->disableIrq(interface);
385  }
386  else
387  {
388  //Just for sanity
389  }
390 }
391 
392 
393 /**
394  * @brief Ethernet MAC transmit interrupt
395  **/
396 
398 {
399  bool_t flag;
400 
401  //Interrupt service routine prologue
402  osEnterIsr();
403 
404  //This flag will be set if a higher priority task must be woken
405  flag = FALSE;
406 
407  //Packet transmitted?
408  if((EMAC->INTSTS & EMAC_INTSTS_TXCPIF_Msk) != 0)
409  {
410  //Clear TXCPIF interrupt flag
411  EMAC->INTSTS = EMAC_INTSTS_TXCPIF_Msk;
412 
413  //Check whether the TX buffer is available for writing
414  if((txDmaDesc[txIndex].txdes0 & EMAC_TXDES0_OWNER) == 0)
415  {
416  //Notify the TCP/IP stack that the transmitter is ready to send
417  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
418  }
419  }
420 
421  //Interrupt service routine epilogue
422  osExitIsr(flag);
423 }
424 
425 
426 /**
427  * @brief Ethernet MAC receive interrupt
428  **/
429 
431 {
432  bool_t flag;
433 
434  //Interrupt service routine prologue
435  osEnterIsr();
436 
437  //This flag will be set if a higher priority task must be woken
438  flag = FALSE;
439 
440  //Packet received?
441  if((EMAC->INTSTS & EMAC_INTSTS_RXGDIF_Msk) != 0)
442  {
443  //Clear RXGDIF interrupt flag
444  EMAC->INTSTS = EMAC_INTSTS_RXGDIF_Msk;
445 
446  //Set event flag
447  nicDriverInterface->nicEvent = TRUE;
448  //Notify the TCP/IP stack of the event
449  flag |= osSetEventFromIsr(&netEvent);
450  }
451 
452  //Interrupt service routine epilogue
453  osExitIsr(flag);
454 }
455 
456 
457 /**
458  * @brief NUC472 Ethernet MAC event handler
459  * @param[in] interface Underlying network interface
460  **/
461 
463 {
464  error_t error;
465 
466  //Process all pending packets
467  do
468  {
469  //Read incoming packet
470  error = nuc472EthReceivePacket(interface);
471 
472  //No more data in the receive buffer?
473  } while(error != ERROR_BUFFER_EMPTY);
474 }
475 
476 
477 /**
478  * @brief Send a packet
479  * @param[in] interface Underlying network interface
480  * @param[in] buffer Multi-part buffer containing the data to send
481  * @param[in] offset Offset to the first data byte
482  * @param[in] ancillary Additional options passed to the stack along with
483  * the packet
484  * @return Error code
485  **/
486 
488  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
489 {
490  size_t length;
491  uint_t txNextIndex;
492 
493  //Retrieve the length of the packet
494  length = netBufferGetLength(buffer) - offset;
495 
496  //Check the frame length
498  {
499  //The transmitter can accept another packet
500  osSetEvent(&interface->nicTxEvent);
501  //Report an error
502  return ERROR_INVALID_LENGTH;
503  }
504 
505  //Make sure the current buffer is available for writing
506  if((txDmaDesc[txIndex].txdes0 & EMAC_TXDES0_OWNER) != 0)
507  {
508  return ERROR_FAILURE;
509  }
510 
511  //Copy user data to the transmit buffer
512  netBufferRead((uint8_t *) txBuffer[txIndex], buffer, offset, length);
513 
514  //Calculate the index of the next descriptor
515  txNextIndex = txIndex + 1;
516 
517  //Wrap around if necessary
518  if(txNextIndex >= NUC472_ETH_TX_BUFFER_COUNT)
519  {
520  txNextIndex = 0;
521  }
522 
523  //Set the start address of the buffer
524  txDmaDesc[txIndex].txdes1 = (uint32_t) txBuffer[txIndex];
525  //Write the number of bytes to send
526  txDmaDesc[txIndex].txdes2 = length & EMAC_TXDES2_TBC;
527  //Set the address of the next descriptor
528  txDmaDesc[txIndex].txdes3 = (uint32_t) &txDmaDesc[txNextIndex];
529 
530  //Give the ownership of the descriptor to the DMA
531  txDmaDesc[txIndex].txdes0 = EMAC_TXDES0_OWNER | EMAC_TXDES0_INTEN |
533 
534  //Instruct the DMA to poll the transmit descriptor list
535  EMAC->TXST = 0;
536 
537  //Point to the next register
538  txIndex = txNextIndex;
539 
540  //Check whether the next buffer is available for writing
541  if((txDmaDesc[txIndex].txdes0 & EMAC_TXDES0_OWNER) == 0)
542  {
543  //The transmitter can accept another packet
544  osSetEvent(&interface->nicTxEvent);
545  }
546 
547  //Data successfully written
548  return NO_ERROR;
549 }
550 
551 
552 /**
553  * @brief Receive a packet
554  * @param[in] interface Underlying network interface
555  * @return Error code
556  **/
557 
559 {
560  error_t error;
561  size_t n;
562  uint_t rxNextIndex;
563  NetRxAncillary ancillary;
564 
565  //Current buffer available for reading?
566  if((rxDmaDesc[rxIndex].rxdes0 & EMAC_RXDES0_OWNER) == 0)
567  {
568  //Valid frame received?
569  if((rxDmaDesc[rxIndex].rxdes0 & EMAC_RXDES0_RXGDIF) != 0)
570  {
571  //Retrieve the length of the frame
572  n = rxDmaDesc[rxIndex].rxdes0 & EMAC_RXDES0_RBC;
573  //Limit the number of data to read
575 
576  //Additional options can be passed to the stack along with the packet
577  ancillary = NET_DEFAULT_RX_ANCILLARY;
578 
579  //Pass the packet to the upper layer
580  nicProcessPacket(interface, rxBuffer[rxIndex], n, &ancillary);
581 
582  //Valid packet received
583  error = NO_ERROR;
584  }
585  else
586  {
587  //The packet is not valid
588  error = ERROR_INVALID_PACKET;
589  }
590 
591  //Calculate the index of the next descriptor
592  rxNextIndex = rxIndex + 1;
593 
594  //Wrap around if necessary
595  if(rxNextIndex >= NUC472_ETH_RX_BUFFER_COUNT)
596  {
597  rxNextIndex = 0;
598  }
599 
600  //Set the start address of the buffer
601  rxDmaDesc[rxIndex].rxdes1 = (uint32_t) rxBuffer[rxIndex];
602  //Set the address of the next descriptor
603  rxDmaDesc[rxIndex].rxdes3 = (uint32_t) &rxDmaDesc[rxNextIndex];
604  //Give the ownership of the descriptor back to the DMA
605  rxDmaDesc[rxIndex].rxdes0 = EMAC_RXDES0_OWNER;
606 
607  //Point to the next register
608  rxIndex = rxNextIndex;
609  }
610  else
611  {
612  //No more data in the receive buffer
613  error = ERROR_BUFFER_EMPTY;
614  }
615 
616  //Instruct the DMA to poll the receive descriptor list
617  EMAC->RXST = 0;
618 
619  //Return status code
620  return error;
621 }
622 
623 
624 /**
625  * @brief Configure MAC address filtering
626  * @param[in] interface Underlying network interface
627  * @return Error code
628  **/
629 
631 {
632  uint_t i;
633  bool_t acceptMulticast;
634 
635  //Debug message
636  TRACE_DEBUG("Updating MAC filter...\r\n");
637 
638  //This flag will be set if multicast addresses should be accepted
639  acceptMulticast = FALSE;
640 
641  //The MAC address filter contains the list of MAC addresses to accept
642  //when receiving an Ethernet frame
643  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
644  {
645  //Valid entry?
646  if(interface->macAddrFilter[i].refCount > 0)
647  {
648  //Accept multicast addresses
649  acceptMulticast = TRUE;
650  //We are done
651  break;
652  }
653  }
654 
655  //Enable or disable the reception of multicast frames
656  if(acceptMulticast)
657  {
658  EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk;
659  }
660  else
661  {
662  EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk;
663  }
664 
665  //Successful processing
666  return NO_ERROR;
667 }
668 
669 
670 /**
671  * @brief Adjust MAC configuration parameters for proper operation
672  * @param[in] interface Underlying network interface
673  * @return Error code
674  **/
675 
677 {
678  uint32_t config;
679 
680  //Read MAC control register
681  config = EMAC->CTL;
682 
683  //10BASE-T or 100BASE-TX operation mode?
684  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
685  {
686  config |= EMAC_CTL_OPMODE_Msk;
687  }
688  else
689  {
690  config &= ~EMAC_CTL_OPMODE_Msk;
691  }
692 
693  //Half-duplex or full-duplex mode?
694  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
695  {
696  config |= EMAC_CTL_FUDUP_Msk;
697  }
698  else
699  {
700  config &= ~EMAC_CTL_FUDUP_Msk;
701  }
702 
703  //Update MAC control register
704  EMAC->CTL = config;
705 
706  //Successful processing
707  return NO_ERROR;
708 }
709 
710 
711 /**
712  * @brief Write PHY register
713  * @param[in] opcode Access type (2 bits)
714  * @param[in] phyAddr PHY address (5 bits)
715  * @param[in] regAddr Register address (5 bits)
716  * @param[in] data Register value
717  **/
718 
719 void nuc472EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
720  uint8_t regAddr, uint16_t data)
721 {
722  uint32_t temp;
723 
724  //Valid opcode?
725  if(opcode == SMI_OPCODE_WRITE)
726  {
727  //Set up a write operation
728  temp = EMAC_MIIMCTL_MDCON_Msk | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk;
729  //PHY address
730  temp |= (phyAddr << EMAC_MIIMCTL_PHYADDR_Pos) & EMAC_MIIMCTL_PHYADDR_Msk;
731  //Register address
732  temp |= (regAddr << EMAC_MIIMCTL_PHYREG_Pos) & EMAC_MIIMCTL_PHYREG_Msk;
733 
734  //Data to be written in the PHY register
735  EMAC->MIIMDAT = data & EMAC_MIIMDAT_DATA_Msk;
736 
737  //Start a write operation
738  EMAC->MIIMCTL = temp;
739  //Wait for the write to complete
740  while((EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) != 0)
741  {
742  }
743  }
744  else
745  {
746  //The MAC peripheral only supports standard Clause 22 opcodes
747  }
748 }
749 
750 
751 /**
752  * @brief Read PHY register
753  * @param[in] opcode Access type (2 bits)
754  * @param[in] phyAddr PHY address (5 bits)
755  * @param[in] regAddr Register address (5 bits)
756  * @return Register value
757  **/
758 
759 uint16_t nuc472EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
760  uint8_t regAddr)
761 {
762  uint16_t data;
763  uint32_t temp;
764 
765  //Valid opcode?
766  if(opcode == SMI_OPCODE_READ)
767  {
768  //Set up a read operation
769  temp = EMAC_MIIMCTL_MDCON_Msk | EMAC_MIIMCTL_BUSY_Msk;
770  //PHY address
771  temp |= (phyAddr << EMAC_MIIMCTL_PHYADDR_Pos) & EMAC_MIIMCTL_PHYADDR_Msk;
772  //Register address
773  temp |= (regAddr << EMAC_MIIMCTL_PHYREG_Pos) & EMAC_MIIMCTL_PHYREG_Msk;
774 
775  //Start a read operation
776  EMAC->MIIMCTL = temp;
777  //Wait for the read to complete
778  while((EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) != 0)
779  {
780  }
781 
782  //Get register value
783  data = EMAC->MIIMDAT & EMAC_MIIMDAT_DATA_Msk;
784  }
785  else
786  {
787  //The MAC peripheral only supports standard Clause 22 opcodes
788  data = 0;
789  }
790 
791  //Return the value of the PHY register
792  return data;
793 }
#define txDmaDesc
#define rxBuffer
#define txBuffer
#define rxDmaDesc
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
#define EMAC_RXDES0_OWNER
#define EMAC_TXDES2_TBC
#define EMAC_TXDES0_CRCAPP
#define EMAC_RXDES0_RXGDIF
#define EMAC_TXDES0_OWNER
#define EMAC_TXDES0_PADEN
#define EMAC_TXDES0_INTEN
#define EMAC_RXDES0_RBC
uint16_t regAddr
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
void nuc472EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t nuc472EthInit(NetInterface *interface)
NUC472 Ethernet MAC initialization.
error_t nuc472EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void EMAC_RX_IRQHandler(void)
Ethernet MAC receive interrupt.
void nuc472EthTick(NetInterface *interface)
NUC472 Ethernet MAC timer handler.
__weak_func void nuc472EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t nuc472EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t nuc472EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
const NicDriver nuc472EthDriver
NUC472 Ethernet MAC driver.
void EMAC_TX_IRQHandler(void)
Ethernet MAC transmit interrupt.
void nuc472EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void nuc472EthDisableIrq(NetInterface *interface)
Disable interrupts.
void nuc472EthEventHandler(NetInterface *interface)
NUC472 Ethernet MAC event handler.
uint16_t nuc472EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void nuc472EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t nuc472EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Nuvoton NUC472 Ethernet MAC driver.
#define NUC472_ETH_IRQ_GROUP_PRIORITY
#define NUC472_ETH_IRQ_PRIORITY_GROUPING
#define NUC472_ETH_IRQ_SUB_PRIORITY
#define NUC472_ETH_TX_BUFFER_SIZE
#define NUC472_ETH_RX_BUFFER_SIZE
#define NUC472_ETH_RX_BUFFER_COUNT
#define NUC472_ETH_TX_BUFFER_COUNT
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
RX DMA descriptor.
TX DMA descriptor.
uint8_t length
Definition: tcp.h:368