nuc472_eth_driver.c
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1 /**
2  * @file nuc472_eth_driver.c
3  * @brief Nuvoton NUC472 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "nuc472_442.h"
34 #include "core/net.h"
36 #include "debug.h"
37 
38 //Underlying network interface
39 static NetInterface *nicDriverInterface;
40 
41 //IAR EWARM compiler?
42 #if defined(__ICCARM__)
43 
44 //Transmit buffer
45 #pragma data_alignment = 4
47 //Receive buffer
48 #pragma data_alignment = 4
50 //Transmit DMA descriptors
51 #pragma data_alignment = 4
53 //Receive DMA descriptors
54 #pragma data_alignment = 4
56 
57 //Keil MDK-ARM or GCC compiler?
58 #else
59 
60 //Transmit buffer
62  __attribute__((aligned(4)));
63 //Receive buffer
65  __attribute__((aligned(4)));
66 //Transmit DMA descriptors
68  __attribute__((aligned(4)));
69 //Receive DMA descriptors
71  __attribute__((aligned(4)));
72 
73 #endif
74 
75 //Current transmit descriptor
76 static uint_t txIndex;
77 //Current receive descriptor
78 static uint_t rxIndex;
79 
80 
81 /**
82  * @brief NUC472 Ethernet MAC driver
83  **/
84 
86 {
88  ETH_MTU,
99  TRUE,
100  TRUE,
101  TRUE,
102  FALSE
103 };
104 
105 
106 /**
107  * @brief NUC472 Ethernet MAC initialization
108  * @param[in] interface Underlying network interface
109  * @return Error code
110  **/
111 
113 {
114  error_t error;
115 
116  //Debug message
117  TRACE_INFO("Initializing NUC472 Ethernet MAC...\r\n");
118 
119  //Save underlying network interface
120  nicDriverInterface = interface;
121 
122  //Enable EMAC clock
123  CLK_EnableModuleClock(EMAC_MODULE);
124  //Select MDC clock frequency
125  CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(100));
126 
127  //Perform a software reset
128  EMAC->CTL |= EMAC_CTL_RST_Msk;
129  //Wait for the reset to complete
130  while(EMAC->CTL & EMAC_CTL_RST_Msk);
131 
132  //GPIO configuration
133  nuc472EthInitGpio(interface);
134 
135  //PHY transceiver initialization
136  error = interface->phyDriver->init(interface);
137  //Failed to initialize PHY transceiver?
138  if(error)
139  return error;
140 
141  //Set the upper 32 bits of the source MAC address
142  EMAC->CAM0M = interface->macAddr.b[3] |
143  (interface->macAddr.b[2] << 8) |
144  (interface->macAddr.b[1] << 16) |
145  (interface->macAddr.b[0] << 24);
146 
147  //Set the lower 16 bits of the source MAC address
148  EMAC->CAM0L = (interface->macAddr.b[5] << 16) |
149  (interface->macAddr.b[4] << 24);
150 
151  //Enable the corresponding CAM entry
152  EMAC->CAMEN = EMAC_CAMEN_CAMxEN_Msk << 0;
153  //Accept broadcast and multicast packets
154  EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | EMAC_CAMCTL_ABP_Msk;
155 
156  //Maximum frame length that can be accepted
157  EMAC->MRFL = NUC472_ETH_RX_BUFFER_SIZE;
158 
159  //Initialize DMA descriptor lists
160  nuc472EthInitDmaDesc(interface);
161 
162  //Enable the desired MAC interrupts
163  EMAC->INTEN = EMAC_INTEN_TXCPIEN_Msk | EMAC_INTEN_TXIEN_Msk |
164  EMAC_INTEN_RXGDIEN_Msk | EMAC_INTEN_RXIEN_Msk;
165 
166  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
167  NVIC_SetPriorityGrouping(NUC472_ETH_IRQ_PRIORITY_GROUPING);
168 
169  //Configure EMAC transmit interrupt priority
170  NVIC_SetPriority(EMAC_TX_IRQn, NVIC_EncodePriority(NUC472_ETH_IRQ_PRIORITY_GROUPING,
172 
173  //Configure EMAC receive interrupt priority
174  NVIC_SetPriority(EMAC_RX_IRQn, NVIC_EncodePriority(NUC472_ETH_IRQ_PRIORITY_GROUPING,
176 
177  //Enable transmission and reception
178  EMAC->CTL |= EMAC_CTL_TXON_Msk | EMAC_CTL_RXON_Msk;
179 
180  //Accept any packets from the upper layer
181  osSetEvent(&interface->nicTxEvent);
182 
183  //Successful initialization
184  return NO_ERROR;
185 }
186 
187 
188 //NuTiny-SDK-NUC472 or NuMaker-PFM-NUC472 evaluation board?
189 #if defined(USE_NUTINY_SDK_NUC472) || defined(USE_NUMAKER_PFM_NUC472)
190 
191 /**
192  * @brief GPIO configuration
193  * @param[in] interface Underlying network interface
194  **/
195 
196 void nuc472EthInitGpio(NetInterface *interface)
197 {
198  //Select RMII interface mode
199  EMAC->CTL |= EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
200 
201  //Configure EMAC_REFCLK (PC.0), EMAC_RXERR (PC.1), EMAC_RXDV (PC.2),
202  //EMAC_RXD1 (PC.3), EMAC_RXD0 (PC.4), EMAC_TXD0 (PC.6) and EMAC_TXD1 (PC.7)
203  SYS->GPC_MFPL = SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK |
204  SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR |
205  SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV |
206  SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 |
207  SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 |
208  SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 |
209  SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
210 
211  //Configure EMAC_TXEN (PC.8)
212  SYS->GPC_MFPH = SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
213 
214  //Enable high slew rate on RMII pins
215  PC->SLEWCTL |= GPIO_SLEWCTL_HSREN0_Msk |
216  GPIO_SLEWCTL_HSREN1_Msk |
217  GPIO_SLEWCTL_HSREN2_Msk |
218  GPIO_SLEWCTL_HSREN3_Msk |
219  GPIO_SLEWCTL_HSREN4_Msk |
220  GPIO_SLEWCTL_HSREN6_Msk |
221  GPIO_SLEWCTL_HSREN7_Msk |
222  GPIO_SLEWCTL_HSREN8_Msk;
223 
224  //Configure EMAC_MDC (PB.14) and EMAC_MDIO (PB.15)
225  SYS->GPB_MFPH = SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC |
226  SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
227 }
228 
229 #endif
230 
231 
232 /**
233  * @brief Initialize DMA descriptor lists
234  * @param[in] interface Underlying network interface
235  **/
236 
238 {
239  uint_t i;
240 
241  //Initialize TX DMA descriptor list
242  for(i = 0; i < NUC472_ETH_TX_BUFFER_COUNT; i++)
243  {
244  //The descriptor is initially owned by the CPU
245  txDmaDesc[i].txdes0 = 0;
246  //Transmit buffer address
247  txDmaDesc[i].txdes1 = (uint32_t) txBuffer[i];
248  //Transmit frame status
249  txDmaDesc[i].txdes2 = 0;
250  //Next descriptor address
251  txDmaDesc[i].txdes3 = (uint32_t) &txDmaDesc[i + 1];
252  }
253 
254  //The last descriptor is chained to the first entry
255  txDmaDesc[i - 1].txdes3 = (uint32_t) &txDmaDesc[0];
256  //Initialize TX descriptor index
257  txIndex = 0;
258 
259  //Initialize RX DMA descriptor list
260  for(i = 0; i < NUC472_ETH_RX_BUFFER_COUNT; i++)
261  {
262  //The descriptor is initially owned by the DMA
263  rxDmaDesc[i].rxdes0 = EMAC_RXDES0_OWNER;
264  //Receive buffer address
265  rxDmaDesc[i].rxdes1 = (uint32_t) rxBuffer[i];
266  //Reserved field
267  rxDmaDesc[i].rxdes2 = 0;
268  //Next descriptor address
269  rxDmaDesc[i].rxdes3 = (uint32_t) &rxDmaDesc[i + 1];
270  }
271 
272  //The last descriptor is chained to the first entry
273  rxDmaDesc[i - 1].rxdes3 = (uint32_t) &rxDmaDesc[0];
274  //Initialize RX descriptor index
275  rxIndex = 0;
276 
277  //Start address of the TX descriptor list
278  EMAC->TXDSA = (uint32_t) txDmaDesc;
279  //Start address of the RX descriptor list
280  EMAC->RXDSA = (uint32_t) rxDmaDesc;
281 }
282 
283 
284 /**
285  * @brief NUC472 Ethernet MAC timer handler
286  *
287  * This routine is periodically called by the TCP/IP stack to
288  * handle periodic operations such as polling the link state
289  *
290  * @param[in] interface Underlying network interface
291  **/
292 
293 void nuc472EthTick(NetInterface *interface)
294 {
295  //Handle periodic operations
296  interface->phyDriver->tick(interface);
297 }
298 
299 
300 /**
301  * @brief Enable interrupts
302  * @param[in] interface Underlying network interface
303  **/
304 
306 {
307  //Enable Ethernet MAC interrupts
308  NVIC_EnableIRQ(EMAC_TX_IRQn);
309  NVIC_EnableIRQ(EMAC_RX_IRQn);
310 
311  //Enable Ethernet PHY interrupts
312  interface->phyDriver->enableIrq(interface);
313 }
314 
315 
316 /**
317  * @brief Disable interrupts
318  * @param[in] interface Underlying network interface
319  **/
320 
322 {
323  //Disable Ethernet MAC interrupts
324  NVIC_DisableIRQ(EMAC_TX_IRQn);
325  NVIC_DisableIRQ(EMAC_RX_IRQn);
326 
327  //Disable Ethernet PHY interrupts
328  interface->phyDriver->disableIrq(interface);
329 }
330 
331 
332 /**
333  * @brief Ethernet MAC transmit interrupt
334  **/
335 
337 {
338  bool_t flag;
339 
340  //Enter interrupt service routine
341  osEnterIsr();
342 
343  //This flag will be set if a higher priority task must be woken
344  flag = FALSE;
345 
346  //A packet has been transmitted?
347  if(EMAC->INTSTS & EMAC_INTSTS_TXCPIF_Msk)
348  {
349  //Clear TXCPIF interrupt flag
350  EMAC->INTSTS = EMAC_INTSTS_TXCPIF_Msk;
351 
352  //Check whether the TX buffer is available for writing
353  if(!(txDmaDesc[txIndex].txdes0 & EMAC_TXDES0_OWNER))
354  {
355  //Notify the TCP/IP stack that the transmitter is ready to send
356  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
357  }
358  }
359 
360  //Leave interrupt service routine
361  osExitIsr(flag);
362 }
363 
364 
365 /**
366  * @brief Ethernet MAC receive interrupt
367  **/
368 
370 {
371  bool_t flag;
372 
373  //Enter interrupt service routine
374  osEnterIsr();
375 
376  //This flag will be set if a higher priority task must be woken
377  flag = FALSE;
378 
379  //A packet has been received?
380  if(EMAC->INTSTS & EMAC_INTSTS_RXGDIF_Msk)
381  {
382  //Disable receive interrupts
383  EMAC->INTEN &= ~EMAC_INTEN_RXIEN_Msk;
384 
385  //Set event flag
386  nicDriverInterface->nicEvent = TRUE;
387  //Notify the TCP/IP stack of the event
388  flag |= osSetEventFromIsr(&netEvent);
389  }
390 
391  //Leave interrupt service routine
392  osExitIsr(flag);
393 }
394 
395 
396 /**
397  * @brief NUC472 Ethernet MAC event handler
398  * @param[in] interface Underlying network interface
399  **/
400 
402 {
403  error_t error;
404 
405  //Packet received?
406  if(EMAC->INTSTS & EMAC_INTSTS_RXGDIF_Msk)
407  {
408  //Clear interrupt flag
409  EMAC->INTSTS = EMAC_INTSTS_RXGDIF_Msk;
410 
411  //Process all pending packets
412  do
413  {
414  //Read incoming packet
415  error = nuc472EthReceivePacket(interface);
416 
417  //No more data in the receive buffer?
418  } while(error != ERROR_BUFFER_EMPTY);
419  }
420 
421  //Re-enable DMA interrupts
422  EMAC->INTEN = EMAC_INTEN_TXCPIEN_Msk | EMAC_INTEN_TXIEN_Msk |
423  EMAC_INTEN_RXGDIEN_Msk | EMAC_INTEN_RXIEN_Msk;
424 }
425 
426 
427 /**
428  * @brief Send a packet
429  * @param[in] interface Underlying network interface
430  * @param[in] buffer Multi-part buffer containing the data to send
431  * @param[in] offset Offset to the first data byte
432  * @return Error code
433  **/
434 
436  const NetBuffer *buffer, size_t offset)
437 {
438  size_t length;
439  uint_t txNextIndex;
440 
441  //Retrieve the length of the packet
442  length = netBufferGetLength(buffer) - offset;
443 
444  //Check the frame length
446  {
447  //The transmitter can accept another packet
448  osSetEvent(&interface->nicTxEvent);
449  //Report an error
450  return ERROR_INVALID_LENGTH;
451  }
452 
453  //Make sure the current buffer is available for writing
454  if(txDmaDesc[txIndex].txdes0 & EMAC_TXDES0_OWNER)
455  return ERROR_FAILURE;
456 
457  //Copy user data to the transmit buffer
458  netBufferRead((uint8_t *) txBuffer[txIndex], buffer, offset, length);
459 
460  //Calculate the index of the next descriptor
461  txNextIndex = txIndex + 1;
462 
463  //Wrap around if necessary
464  if(txNextIndex >= NUC472_ETH_TX_BUFFER_COUNT)
465  txNextIndex = 0;
466 
467  //Set the start address of the buffer
468  txDmaDesc[txIndex].txdes1 = (uint32_t) txBuffer[txIndex];
469  //Write the number of bytes to send
470  txDmaDesc[txIndex].txdes2 = length & EMAC_TXDES2_TBC;
471  //Set the address of the next descriptor
472  txDmaDesc[txIndex].txdes3 = (uint32_t) &txDmaDesc[txNextIndex];
473 
474  //Give the ownership of the descriptor to the DMA
475  txDmaDesc[txIndex].txdes0 = EMAC_TXDES0_OWNER | EMAC_TXDES0_INTEN |
477 
478  //Instruct the DMA to poll the transmit descriptor list
479  EMAC->TXST = 0;
480 
481  //Point to the next register
482  txIndex = txNextIndex;
483 
484  //Check whether the next buffer is available for writing
485  if(!(txDmaDesc[txIndex].txdes0 & EMAC_TXDES0_OWNER))
486  {
487  //The transmitter can accept another packet
488  osSetEvent(&interface->nicTxEvent);
489  }
490 
491  //Data successfully written
492  return NO_ERROR;
493 }
494 
495 
496 /**
497  * @brief Receive a packet
498  * @param[in] interface Underlying network interface
499  * @return Error code
500  **/
501 
503 {
504  error_t error;
505  size_t n;
506  uint_t rxNextIndex;
507 
508  //The current buffer is available for reading?
509  if(!(rxDmaDesc[rxIndex].rxdes0 & EMAC_RXDES0_OWNER))
510  {
511  //Valid frame received?
512  if(rxDmaDesc[rxIndex].rxdes0 & EMAC_RXDES0_RXGDIF)
513  {
514  //Retrieve the length of the frame
515  n = rxDmaDesc[rxIndex].rxdes0 & EMAC_RXDES0_RBC;
516  //Limit the number of data to read
518 
519  //Pass the packet to the upper layer
520  nicProcessPacket(interface, rxBuffer[rxIndex], n);
521 
522  //Valid packet received
523  error = NO_ERROR;
524  }
525  else
526  {
527  //The packet is not valid
528  error = ERROR_INVALID_PACKET;
529  }
530 
531  //Calculate the index of the next descriptor
532  rxNextIndex = rxIndex + 1;
533 
534  //Wrap around if necessary
535  if(rxNextIndex >= NUC472_ETH_RX_BUFFER_COUNT)
536  rxNextIndex = 0;
537 
538  //Set the start address of the buffer
539  rxDmaDesc[rxIndex].rxdes1 = (uint32_t) rxBuffer[rxIndex];
540  //Set the address of the next descriptor
541  rxDmaDesc[rxIndex].rxdes3 = (uint32_t) &rxDmaDesc[rxNextIndex];
542  //Give the ownership of the descriptor back to the DMA
543  rxDmaDesc[rxIndex].rxdes0 = EMAC_RXDES0_OWNER;
544 
545  //Point to the next register
546  rxIndex = rxNextIndex;
547  }
548  else
549  {
550  //No more data in the receive buffer
551  error = ERROR_BUFFER_EMPTY;
552  }
553 
554  //Instruct the DMA to poll the receive descriptor list
555  EMAC->RXST = 0;
556 
557  //Return status code
558  return error;
559 }
560 
561 
562 /**
563  * @brief Configure MAC address filtering
564  * @param[in] interface Underlying network interface
565  * @return Error code
566  **/
567 
569 {
570  uint_t i;
571  bool_t acceptMulticast;
572 
573  //This flag will be set if multicast addresses should be accepted
574  acceptMulticast = FALSE;
575 
576  //The MAC address filter contains the list of MAC addresses to accept
577  //when receiving an Ethernet frame
578  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
579  {
580  //Valid entry?
581  if(interface->macAddrFilter[i].refCount > 0)
582  {
583  //Accept multicast addresses
584  acceptMulticast = TRUE;
585  //We are done
586  break;
587  }
588  }
589 
590  //Enable the reception of multicast frames if necessary
591  if(acceptMulticast)
592  EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk;
593  else
594  EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk;
595 
596  //Successful processing
597  return NO_ERROR;
598 }
599 
600 
601 /**
602  * @brief Adjust MAC configuration parameters for proper operation
603  * @param[in] interface Underlying network interface
604  * @return Error code
605  **/
606 
608 {
609  uint32_t config;
610 
611  //Read MAC control register
612  config = EMAC->CTL;
613 
614  //10BASE-T or 100BASE-TX operation mode?
615  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
616  config |= EMAC_CTL_OPMODE_Msk;
617  else
618  config &= ~EMAC_CTL_OPMODE_Msk;
619 
620  //Half-duplex or full-duplex mode?
621  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
622  config |= EMAC_CTL_FUDUP_Msk;
623  else
624  config &= ~EMAC_CTL_FUDUP_Msk;
625 
626  //Update MAC control register
627  EMAC->CTL = config;
628 
629  //Successful processing
630  return NO_ERROR;
631 }
632 
633 
634 /**
635  * @brief Write PHY register
636  * @param[in] phyAddr PHY address
637  * @param[in] regAddr Register address
638  * @param[in] data Register value
639  **/
640 
641 void nuc472EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
642 {
643  uint32_t value;
644 
645  //Set up a write operation
646  value = EMAC_MIIMCTL_MDCON_Msk | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk;
647  //PHY address
648  value |= (phyAddr << EMAC_MIIMCTL_PHYADDR_Pos) & EMAC_MIIMCTL_PHYADDR_Msk;
649  //Register address
650  value |= (regAddr << EMAC_MIIMCTL_PHYREG_Pos) & EMAC_MIIMCTL_PHYREG_Msk;
651 
652  //Data to be written in the PHY register
653  EMAC->MIIMDAT = data & EMAC_MIIMDAT_DATA_Msk;
654 
655  //Start a write operation
656  EMAC->MIIMCTL = value;
657  //Wait for the write to complete
658  while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
659 }
660 
661 
662 /**
663  * @brief Read PHY register
664  * @param[in] phyAddr PHY address
665  * @param[in] regAddr Register address
666  * @return Register value
667  **/
668 
669 uint16_t nuc472EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
670 {
671  uint32_t value;
672 
673  //Set up a read operation
674  value = EMAC_MIIMCTL_MDCON_Msk | EMAC_MIIMCTL_BUSY_Msk;
675  //PHY address
676  value |= (phyAddr << EMAC_MIIMCTL_PHYADDR_Pos) & EMAC_MIIMCTL_PHYADDR_Msk;
677  //Register address
678  value |= (regAddr << EMAC_MIIMCTL_PHYREG_Pos) & EMAC_MIIMCTL_PHYREG_Msk;
679 
680  //Start a read operation
681  EMAC->MIIMCTL = value;
682  //Wait for the read to complete
683  while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
684 
685  //Return PHY register contents
686  return EMAC->MIIMDAT & EMAC_MIIMDAT_DATA_Msk;
687 }
#define EMAC_RXDES0_OWNER
#define txDmaDesc
TCP/IP stack core.
#define NUC472_ETH_IRQ_GROUP_PRIORITY
Debugging facilities.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define EMAC_TXDES0_OWNER
#define EMAC_TXDES0_PADEN
Generic error code.
Definition: error.h:43
error_t nuc472EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define rxDmaDesc
void nuc472EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define txBuffer
#define NUC472_ETH_TX_BUFFER_SIZE
error_t nuc472EthInit(NetInterface *interface)
NUC472 Ethernet MAC initialization.
TX DMA descriptor.
error_t nuc472EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define NUC472_ETH_IRQ_SUB_PRIORITY
#define EMAC_TXDES0_CRCAPP
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define EMAC_TXDES0_INTEN
RX DMA descriptor.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
void nuc472EthInitGpio(NetInterface *interface)
error_t nuc472EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t nuc472EthReceivePacket(NetInterface *interface)
Receive a packet.
NIC driver.
Definition: nic.h:161
#define NUC472_ETH_IRQ_PRIORITY_GROUPING
void nuc472EthDisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void nuc472EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void EMAC_TX_IRQHandler(void)
Ethernet MAC transmit interrupt.
#define EMAC_RXDES0_RXGDIF
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define EMAC_RXDES0_RBC
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
uint16_t nuc472EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define NUC472_ETH_TX_BUFFER_COUNT
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
void nuc472EthEventHandler(NetInterface *interface)
NUC472 Ethernet MAC event handler.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void EMAC_RX_IRQHandler(void)
Ethernet MAC receive interrupt.
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Nuvoton NUC472 Ethernet MAC controller.
const NicDriver nuc472EthDriver
NUC472 Ethernet MAC driver.
void nuc472EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define osExitIsr(flag)
#define osEnterIsr()
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
#define NUC472_ETH_RX_BUFFER_COUNT
void nuc472EthTick(NetInterface *interface)
NUC472 Ethernet MAC timer handler.
#define EMAC_TXDES2_TBC
#define NUC472_ETH_RX_BUFFER_SIZE