32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "nuc472_442.h"
44 #if defined(__ICCARM__)
47 #pragma data_alignment = 4
50 #pragma data_alignment = 4
53 #pragma data_alignment = 4
56 #pragma data_alignment = 4
119 TRACE_INFO(
"Initializing NUC472 Ethernet MAC...\r\n");
122 nicDriverInterface = interface;
125 CLK_EnableModuleClock(EMAC_MODULE);
127 CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(100));
130 EMAC->CTL |= EMAC_CTL_RST_Msk;
132 while((EMAC->CTL & EMAC_CTL_RST_Msk) != 0)
140 if(interface->phyDriver != NULL)
143 error = interface->phyDriver->init(interface);
145 else if(interface->switchDriver != NULL)
148 error = interface->switchDriver->init(interface);
163 EMAC->CAM0M = interface->macAddr.b[3] |
164 (interface->macAddr.b[2] << 8) |
165 (interface->macAddr.b[1] << 16) |
166 (interface->macAddr.b[0] << 24);
169 EMAC->CAM0L = (interface->macAddr.b[5] << 16) |
170 (interface->macAddr.b[4] << 24);
173 EMAC->CAMEN = EMAC_CAMEN_CAMxEN_Msk << 0;
175 EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | EMAC_CAMCTL_ABP_Msk;
184 EMAC->INTEN = EMAC_INTEN_TXCPIEN_Msk | EMAC_INTEN_TXIEN_Msk |
185 EMAC_INTEN_RXGDIEN_Msk | EMAC_INTEN_RXIEN_Msk;
199 EMAC->CTL |= EMAC_CTL_TXON_Msk | EMAC_CTL_RXON_Msk;
217 #if defined(USE_NUTINY_SDK_NUC472) || defined(USE_NUMAKER_PFM_NUC472)
221 EMAC->CTL |= EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
224 temp = SYS->GPB_MFPH;
225 temp = (temp & ~SYS_GPB_MFPH_PB14MFP_Msk) | SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC;
226 temp = (temp & ~SYS_GPB_MFPH_PB15MFP_Msk) | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
227 SYS->GPB_MFPH = temp;
232 temp = SYS->GPC_MFPL;
233 temp = (temp & ~SYS_GPC_MFPL_PC0MFP_Msk) | SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK;
234 temp = (temp & ~SYS_GPC_MFPL_PC1MFP_Msk) | SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR;
235 temp = (temp & ~SYS_GPC_MFPL_PC2MFP_Msk) | SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV;
236 temp = (temp & ~SYS_GPC_MFPL_PC3MFP_Msk) | SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1;
237 temp = (temp & ~SYS_GPC_MFPL_PC4MFP_Msk) | SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0;
238 temp = (temp & ~SYS_GPC_MFPL_PC6MFP_Msk) | SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0;
239 temp = (temp & ~SYS_GPC_MFPL_PC7MFP_Msk) | SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
240 SYS->GPC_MFPL = temp;
243 temp = SYS->GPC_MFPH;
244 temp = (temp & ~SYS_GPC_MFPH_PC8MFP_Msk) | SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
245 SYS->GPC_MFPH = temp;
248 PC->SLEWCTL |= GPIO_SLEWCTL_HSREN6_Msk | GPIO_SLEWCTL_HSREN7_Msk |
249 GPIO_SLEWCTL_HSREN8_Msk;
318 if(interface->phyDriver != NULL)
321 interface->phyDriver->tick(interface);
323 else if(interface->switchDriver != NULL)
326 interface->switchDriver->tick(interface);
343 NVIC_EnableIRQ(EMAC_TX_IRQn);
344 NVIC_EnableIRQ(EMAC_RX_IRQn);
347 if(interface->phyDriver != NULL)
350 interface->phyDriver->enableIrq(interface);
352 else if(interface->switchDriver != NULL)
355 interface->switchDriver->enableIrq(interface);
372 NVIC_DisableIRQ(EMAC_TX_IRQn);
373 NVIC_DisableIRQ(EMAC_RX_IRQn);
376 if(interface->phyDriver != NULL)
379 interface->phyDriver->disableIrq(interface);
381 else if(interface->switchDriver != NULL)
384 interface->switchDriver->disableIrq(interface);
408 if((EMAC->INTSTS & EMAC_INTSTS_TXCPIF_Msk) != 0)
411 EMAC->INTSTS = EMAC_INTSTS_TXCPIF_Msk;
441 if((EMAC->INTSTS & EMAC_INTSTS_RXGDIF_Msk) != 0)
444 EMAC->INTSTS = EMAC_INTSTS_RXGDIF_Msk;
447 nicDriverInterface->nicEvent =
TRUE;
515 txNextIndex = txIndex + 1;
538 txIndex = txNextIndex;
592 rxNextIndex = rxIndex + 1;
608 rxIndex = rxNextIndex;
639 acceptMulticast =
FALSE;
646 if(interface->macAddrFilter[i].refCount > 0)
649 acceptMulticast =
TRUE;
658 EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk;
662 EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk;
686 config |= EMAC_CTL_OPMODE_Msk;
690 config &= ~EMAC_CTL_OPMODE_Msk;
696 config |= EMAC_CTL_FUDUP_Msk;
700 config &= ~EMAC_CTL_FUDUP_Msk;
728 temp = EMAC_MIIMCTL_MDCON_Msk | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk;
730 temp |= (phyAddr << EMAC_MIIMCTL_PHYADDR_Pos) & EMAC_MIIMCTL_PHYADDR_Msk;
732 temp |= (
regAddr << EMAC_MIIMCTL_PHYREG_Pos) & EMAC_MIIMCTL_PHYREG_Msk;
735 EMAC->MIIMDAT =
data & EMAC_MIIMDAT_DATA_Msk;
738 EMAC->MIIMCTL = temp;
740 while((EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) != 0)
769 temp = EMAC_MIIMCTL_MDCON_Msk | EMAC_MIIMCTL_BUSY_Msk;
771 temp |= (phyAddr << EMAC_MIIMCTL_PHYADDR_Pos) & EMAC_MIIMCTL_PHYADDR_Msk;
773 temp |= (
regAddr << EMAC_MIIMCTL_PHYREG_Pos) & EMAC_MIIMCTL_PHYREG_Msk;
776 EMAC->MIIMCTL = temp;
778 while((EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) != 0)
783 data = EMAC->MIIMDAT & EMAC_MIIMDAT_DATA_Msk;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define MAC_ADDR_FILTER_SIZE
#define EMAC_RXDES0_OWNER
#define EMAC_TXDES0_CRCAPP
#define EMAC_RXDES0_RXGDIF
#define EMAC_TXDES0_OWNER
#define EMAC_TXDES0_PADEN
#define EMAC_TXDES0_INTEN
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
void nuc472EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t nuc472EthInit(NetInterface *interface)
NUC472 Ethernet MAC initialization.
error_t nuc472EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void EMAC_RX_IRQHandler(void)
Ethernet MAC receive interrupt.
void nuc472EthTick(NetInterface *interface)
NUC472 Ethernet MAC timer handler.
__weak_func void nuc472EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t nuc472EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t nuc472EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
const NicDriver nuc472EthDriver
NUC472 Ethernet MAC driver.
void EMAC_TX_IRQHandler(void)
Ethernet MAC transmit interrupt.
void nuc472EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void nuc472EthDisableIrq(NetInterface *interface)
Disable interrupts.
void nuc472EthEventHandler(NetInterface *interface)
NUC472 Ethernet MAC event handler.
uint16_t nuc472EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void nuc472EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t nuc472EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Nuvoton NUC472 Ethernet MAC driver.
#define NUC472_ETH_IRQ_GROUP_PRIORITY
#define NUC472_ETH_IRQ_PRIORITY_GROUPING
#define NUC472_ETH_IRQ_SUB_PRIORITY
#define NUC472_ETH_TX_BUFFER_SIZE
#define NUC472_ETH_RX_BUFFER_SIZE
#define NUC472_ETH_RX_BUFFER_COUNT
#define NUC472_ETH_TX_BUFFER_COUNT
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
Structure describing a buffer that spans multiple chunks.