32 #define TRACE_LEVEL NIC_TRACE_LEVEL
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 8
49 #pragma location = SAM9X6_ETH2_RAM_SECTION
52 #pragma data_alignment = 8
53 #pragma location = SAM9X6_ETH2_RAM_SECTION
56 #pragma data_alignment = 4
57 #pragma location = SAM9X6_ETH2_RAM_SECTION
60 #pragma data_alignment = 4
61 #pragma location = SAM9X6_ETH2_RAM_SECTION
83 static uint_t txBufferIndex;
85 static uint_t rxBufferIndex;
122 volatile uint32_t temp;
125 TRACE_INFO(
"Initializing SAM9X6 Ethernet MAC (EMAC1)...\r\n");
128 nicDriverInterface = interface;
131 PMC_REGS->PMC_PCR = PMC_PCR_PID(ID_EMAC1);
132 temp = PMC_REGS->PMC_PCR;
133 PMC_REGS->PMC_PCR = temp | PMC_PCR_CMD_Msk | PMC_PCR_EN_Msk;
136 EMAC1_REGS->EMAC_NCR = 0;
142 EMAC1_REGS->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
144 EMAC1_REGS->EMAC_NCR |= EMAC_NCR_MPE_Msk;
147 if(interface->phyDriver != NULL)
150 error = interface->phyDriver->init(interface);
152 else if(interface->switchDriver != NULL)
155 error = interface->switchDriver->init(interface);
170 EMAC1_REGS->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171 EMAC1_REGS->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
174 EMAC1_REGS->EMAC_SA[1].EMAC_SAxB = 0;
175 EMAC1_REGS->EMAC_SA[2].EMAC_SAxB = 0;
176 EMAC1_REGS->EMAC_SA[3].EMAC_SAxB = 0;
179 EMAC1_REGS->EMAC_HRB = 0;
180 EMAC1_REGS->EMAC_HRT = 0;
183 EMAC1_REGS->EMAC_NCFGR |= EMAC_NCFGR_BIG_Msk | EMAC_NCFGR_MTI_Msk;
189 EMAC1_REGS->EMAC_TSR = EMAC_TSR_UND_Msk | EMAC_TSR_COMP_Msk |
190 EMAC_TSR_BEX_Msk | EMAC_TSR_TGO_Msk | EMAC_TSR_RLES_Msk |
191 EMAC_TSR_COL_Msk | EMAC_TSR_UBR_Msk;
194 EMAC1_REGS->EMAC_RSR = EMAC_RSR_OVR_Msk | EMAC_RSR_REC_Msk |
198 EMAC1_REGS->EMAC_IDR = 0xFFFFFFFF;
201 EMAC1_REGS->EMAC_IER = EMAC_IER_ROVR_Msk | EMAC_IER_TCOMP_Msk |
202 EMAC_IER_TXERR_Msk | EMAC_IER_RLE_Msk | EMAC_IER_TUND_Msk |
203 EMAC_IER_RXUBR_Msk | EMAC_IER_RCOMP_Msk;
206 temp = EMAC1_REGS->EMAC_ISR;
210 AIC_REGS->AIC_SSR = ID_EMAC1;
215 AIC_REGS->AIC_ICCR = (1 << ID_EMAC1);
218 EMAC1_REGS->EMAC_NCR |= EMAC_NCR_TE_Msk | EMAC_NCR_RE_Msk;
272 rxBufferDesc[i].
status = 0;
281 EMAC1_REGS->EMAC_TBQP = (uint32_t) txBufferDesc;
283 EMAC1_REGS->EMAC_RBQP = (uint32_t) rxBufferDesc;
299 if(interface->phyDriver != NULL)
302 interface->phyDriver->tick(interface);
304 else if(interface->switchDriver != NULL)
307 interface->switchDriver->tick(interface);
324 AIC_REGS->AIC_SSR = AIC_SSR_INTSEL(ID_EMAC1);
325 AIC_REGS->AIC_IECR = AIC_IECR_INTEN_Msk;
328 if(interface->phyDriver != NULL)
331 interface->phyDriver->enableIrq(interface);
333 else if(interface->switchDriver != NULL)
336 interface->switchDriver->enableIrq(interface);
353 AIC_REGS->AIC_SSR = AIC_SSR_INTSEL(ID_EMAC1);
354 AIC_REGS->AIC_IDCR = AIC_IDCR_INTD_Msk;
357 if(interface->phyDriver != NULL)
360 interface->phyDriver->disableIrq(interface);
362 else if(interface->switchDriver != NULL)
365 interface->switchDriver->disableIrq(interface);
381 volatile uint32_t isr;
382 volatile uint32_t tsr;
383 volatile uint32_t rsr;
393 isr = EMAC1_REGS->EMAC_ISR;
394 tsr = EMAC1_REGS->EMAC_TSR;
395 rsr = EMAC1_REGS->EMAC_RSR;
399 if((tsr & (EMAC_TSR_UND_Msk | EMAC_TSR_COMP_Msk | EMAC_TSR_BEX_Msk |
400 EMAC_TSR_TGO_Msk | EMAC_TSR_RLES_Msk | EMAC_TSR_COL_Msk |
401 EMAC_TSR_UBR_Msk)) != 0)
404 EMAC1_REGS->EMAC_TSR = tsr;
407 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
415 if((rsr & (EMAC_RSR_OVR_Msk | EMAC_RSR_REC_Msk | EMAC_RSR_BNA_Msk)) != 0)
418 nicDriverInterface->nicEvent =
TRUE;
423 #if (NET_RTOS_SUPPORT == DISABLED)
425 AIC_REGS->AIC_EOICR = 0;
444 rsr = EMAC1_REGS->EMAC_RSR;
447 if((rsr & (EMAC_RSR_OVR_Msk | EMAC_RSR_REC_Msk | EMAC_RSR_BNA_Msk)) != 0)
450 EMAC1_REGS->EMAC_RSR = rsr;
492 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) == 0)
521 EMAC1_REGS->EMAC_NCR |= EMAC_NCR_TSTART_Msk;
524 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
562 j = rxBufferIndex + i;
585 if((rxBufferDesc[j].status &
EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
599 if(eofIndex != UINT_MAX)
603 else if(sofIndex != UINT_MAX)
616 for(i = 0; i < j; i++)
619 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
679 uint32_t hashTable[2];
687 EMAC1_REGS->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
688 EMAC1_REGS->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
704 entry = &interface->macAddrFilter[i];
716 k = (
p[0] >> 6) ^
p[0];
717 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
718 k ^= (
p[2] >> 2) ^ (
p[2] << 4);
719 k ^= (
p[3] >> 6) ^
p[3];
720 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
721 k ^= (
p[5] >> 2) ^ (
p[5] << 4);
727 hashTable[k / 32] |= (1 << (k % 32));
735 unicastMacAddr[j++] = entry->
addr;
745 EMAC1_REGS->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
746 EMAC1_REGS->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
751 EMAC1_REGS->EMAC_SA[1].EMAC_SAxB = 0;
758 EMAC1_REGS->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
759 EMAC1_REGS->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
764 EMAC1_REGS->EMAC_SA[2].EMAC_SAxB = 0;
771 EMAC1_REGS->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
772 EMAC1_REGS->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
777 EMAC1_REGS->EMAC_SA[3].EMAC_SAxB = 0;
781 EMAC1_REGS->EMAC_HRB = hashTable[0];
782 EMAC1_REGS->EMAC_HRT = hashTable[1];
785 TRACE_DEBUG(
" HRB = %08" PRIX32
"\r\n", EMAC1_REGS->EMAC_HRB);
786 TRACE_DEBUG(
" HRT = %08" PRIX32
"\r\n", EMAC1_REGS->EMAC_HRT);
804 config = EMAC1_REGS->EMAC_NCFGR;
809 config |= EMAC_NCFGR_SPD_Msk;
813 config &= ~EMAC_NCFGR_SPD_Msk;
819 config |= EMAC_NCFGR_FD_Msk;
823 config &= ~EMAC_NCFGR_FD_Msk;
827 EMAC1_REGS->EMAC_NCFGR = config;
851 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
853 temp |= EMAC_MAN_PHYA(phyAddr);
855 temp |= EMAC_MAN_REGA(
regAddr);
857 temp |= EMAC_MAN_DATA(
data);
860 EMAC1_REGS->EMAC_MAN = temp;
862 while((EMAC1_REGS->EMAC_NSR & EMAC_NSR_IDLE_Msk) == 0)
891 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
893 temp |= EMAC_MAN_PHYA(phyAddr);
895 temp |= EMAC_MAN_REGA(
regAddr);
898 EMAC1_REGS->EMAC_MAN = temp;
900 while((EMAC1_REGS->EMAC_NSR & EMAC_NSR_IDLE_Msk) == 0)
905 data = EMAC1_REGS->EMAC_MAN & EMAC_MAN_DATA_Msk;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define ETH_MAX_FRAME_SIZE
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define EMAC_RX_OWNERSHIP
__weak_func void sam9x6Eth2InitGpio(NetInterface *interface)
GPIO configuration.
void sam9x6Eth2DisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver sam9x6Eth2Driver
SAM9X6 Ethernet MAC driver (EMAC1 instance)
error_t sam9x6Eth2Init(NetInterface *interface)
SAM9X6 Ethernet MAC initialization.
void sam9x6Eth2InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void sam9x6Eth2EventHandler(NetInterface *interface)
SAM9X6 Ethernet MAC event handler.
uint16_t sam9x6Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sam9x6Eth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t sam9x6Eth2ReceivePacket(NetInterface *interface)
Receive a packet.
void sam9x6Eth2EnableIrq(NetInterface *interface)
Enable interrupts.
void sam9x6Eth2Tick(NetInterface *interface)
SAM9X6 Ethernet MAC timer handler.
error_t sam9x6Eth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void sam9x6Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void sam9x6Eth2IrqHandler(void)
SAM9X6 Ethernet MAC interrupt service routine.
error_t sam9x6Eth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
SAM9X60 Ethernet MAC driver (EMAC1 instance)
#define SAM9X6_ETH2_RX_BUFFER_COUNT
#define SAM9X6_ETH2_TX_BUFFER_SIZE
#define SAM9X6_ETH2_TX_BUFFER_COUNT
#define SAM9X6_ETH2_RX_BUFFER_SIZE
#define SAM9X6_ETH2_RAM_SECTION
#define SAM9X6_ETH2_IRQ_PRIORITY
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.
Receive buffer descriptor.
Transmit buffer descriptor.