pic32mx_eth_driver.c
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1 /**
2  * @file pic32mx_eth_driver.c
3  * @brief PIC32MX Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <p32xxxx.h>
36 #include <sys/kmem.h>
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //Transmit buffer
46  __attribute__((coherent, aligned(4)));
47 //Receive buffer
49  __attribute__((coherent, aligned(4)));
50 //Transmit buffer descriptors
52  __attribute__((coherent, aligned(4)));
53 //Receive buffer descriptors
55  __attribute__((coherent, aligned(4)));
56 
57 //Pointer to the current TX buffer descriptor
58 static Pic32mxTxBufferDesc *txCurBufferDesc;
59 //Pointer to the current RX buffer descriptor
60 static Pic32mxRxBufferDesc *rxCurBufferDesc;
61 
62 
63 /**
64  * @brief PIC32MX Ethernet MAC driver
65  **/
66 
68 {
70  ETH_MTU,
81  TRUE,
82  TRUE,
83  TRUE,
84  FALSE
85 };
86 
87 
88 /**
89  * @brief PIC32MX Ethernet MAC initialization
90  * @param[in] interface Underlying network interface
91  * @return Error code
92  **/
93 
95 {
96  error_t error;
97 
98  //Debug message
99  TRACE_INFO("Initializing PIC32MX Ethernet MAC...\r\n");
100 
101  //Save underlying network interface
102  nicDriverInterface = interface;
103 
104  //GPIO configuration
105  pic32mxEthInitGpio(interface);
106 
107  //Disable Ethernet interrupts
108  IEC1CLR = _IEC1_ETHIE_MASK;
109  //Turn the Ethernet controller off
110  ETHCON1CLR = _ETHCON1_ON_MASK | _ETHCON1_TXRTS_POSITION | _ETHCON1_RXEN_MASK;
111 
112  //Wait activity abort by polling the ETHBUSY bit
113  while(ETHSTAT & _ETHSTAT_ETHBUSY_MASK)
114  {
115  }
116 
117  //Enable the Ethernet controller by setting the ON bit
118  ETHCON1SET = _ETHCON1_ON_MASK;
119 
120  //Clear Ethernet interrupt flag
121  IFS1CLR = _IFS1_ETHIF_MASK;
122  //Disable any Ethernet controller interrupt generation
123  ETHIEN = 0;
124  ETHIRQ = 0;
125  //Clear the TX and RX start addresses
126  ETHTXST = 0;
127  ETHRXST = 0;
128 
129  //Reset the MAC using SOFTRESET
130  EMAC1CFG1SET = _EMAC1CFG1_SOFTRESET_MASK;
131  EMAC1CFG1CLR = _EMAC1CFG1_SOFTRESET_MASK;
132 
133  //Reset the RMII module
134  EMAC1SUPPSET = _EMAC1SUPP_RESETRMII_MASK;
135  EMAC1SUPPCLR = _EMAC1SUPP_RESETRMII_MASK;
136 
137  //Issue an MIIM block reset by setting the RESETMGMT bit
138  EMAC1MCFGSET = _EMAC1MCFG_RESETMGMT_MASK;
139  EMAC1MCFGCLR = _EMAC1MCFG_RESETMGMT_MASK;
140 
141  //Select the proper divider for the MDC clock
142  EMAC1MCFG = _EMAC1MCFG_CLKSEL_DIV40;
143 
144  //PHY transceiver initialization
145  error = interface->phyDriver->init(interface);
146  //Failed to initialize PHY transceiver?
147  if(error)
148  return error;
149 
150  //Optionally set the station MAC address
151  if(macCompAddr(&interface->macAddr, &MAC_UNSPECIFIED_ADDR))
152  {
153  //Use the factory preprogrammed station address
154  interface->macAddr.w[0] = EMAC1SA2;
155  interface->macAddr.w[1] = EMAC1SA1;
156  interface->macAddr.w[2] = EMAC1SA0;
157 
158  //Generate the 64-bit interface identifier
159  macAddrToEui64(&interface->macAddr, &interface->eui64);
160  }
161  else
162  {
163  //Override the factory preprogrammed address
164  EMAC1SA0 = interface->macAddr.w[2];
165  EMAC1SA1 = interface->macAddr.w[1];
166  EMAC1SA2 = interface->macAddr.w[0];
167  }
168 
169  //Initialize hash table
170  ETHHT0 = 0;
171  ETHHT1 = 0;
172 
173  //Configure the receive filter
174  ETHRXFC = _ETHRXFC_HTEN_MASK | _ETHRXFC_CRCOKEN_MASK |
175  _ETHRXFC_RUNTEN_MASK | _ETHRXFC_UCEN_MASK | _ETHRXFC_BCEN_MASK;
176 
177  //Disable flow control
178  EMAC1CFG1 = _EMAC1CFG1_RXENABLE_MASK;
179  //Automatic padding and CRC generation
180  EMAC1CFG2 = _EMAC1CFG2_PADENABLE_MASK | _EMAC1CFG2_CRCENABLE_MASK;
181  //Set the maximum frame length
182  EMAC1MAXF = PIC32MX_ETH_RX_BUFFER_SIZE;
183 
184  //Initialize DMA descriptor lists
185  pic32mxEthInitBufferDesc(interface);
186 
187  //Enable desired interrupts
188  ETHIENSET = _ETHIEN_PKTPENDIE_MASK | _ETHIEN_TXDONEIE_MASK;
189 
190  //Set interrupt priority
191  IPC12CLR = _IPC12_ETHIP_MASK;
192  IPC12SET = (PIC32MX_ETH_IRQ_PRIORITY << _IPC12_ETHIP_POSITION);
193  //Set interrupt subpriority
194  IPC12CLR = _IPC12_ETHIS_MASK;
195  IPC12SET = (PIC32MX_ETH_IRQ_SUB_PRIORITY << _IPC12_ETHIS_POSITION);
196 
197  //Enable the reception by setting the RXEN bit
198  ETHCON1SET = _ETHCON1_RXEN_MASK;
199 
200  //Accept any packets from the upper layer
201  osSetEvent(&interface->nicTxEvent);
202 
203  //Successful initialization
204  return NO_ERROR;
205 }
206 
207 
208 //PIC32 Ethernet Starter Kit, PIC32 Ethernet Starter Kit II or
209 //chipKIT Pro MX7 evaluation board?
210 #if defined(USE_PIC32_ETH_STARTER_KIT) || defined(USE_PIC32_ETH_STARTER_KIT_2) || \
211  defined(USE_CHIPKIT_PRO_MX7)
212 
213 /**
214  * @brief GPIO configuration
215  * @param[in] interface Underlying network interface
216  **/
217 
218 void pic32mxEthInitGpio(NetInterface *interface)
219 {
220  //No analog pins are shared with the alternate RMII interface
221 }
222 
223 #endif
224 
225 
226 /**
227  * @brief Initialize DMA descriptor lists
228  * @param[in] interface Underlying network interface
229  **/
230 
232 {
233  uint_t i;
234 
235  //Initialize TX descriptor list
236  for(i = 0; i < PIC32MX_ETH_TX_BUFFER_COUNT; i++)
237  {
238  //Point to the current descriptor
239  txCurBufferDesc = &txBufferDesc[i];
240 
241  //Use linked list rather than linear list
242  txCurBufferDesc->control = ETH_TX_CTRL_NPV;
243  //Transmit buffer address
244  txCurBufferDesc->address = KVA_TO_PA(txBuffer[i]);
245  //Transmit status vector
246  txCurBufferDesc->status1 = 0;
247  txCurBufferDesc->status2 = 0;
248  //Next descriptor address
249  txCurBufferDesc->next = KVA_TO_PA(&txBufferDesc[i + 1]);
250  }
251 
252  //The last descriptor is chained to the first entry
253  txCurBufferDesc->next = KVA_TO_PA(&txBufferDesc[0]);
254  //Point to the very first descriptor
255  txCurBufferDesc = &txBufferDesc[0];
256 
257  //Initialize RX descriptor list
258  for(i = 0; i < PIC32MX_ETH_RX_BUFFER_COUNT; i++)
259  {
260  //Point to the current descriptor
261  rxCurBufferDesc = &rxBufferDesc[i];
262 
263  //The descriptor is initially owned by the DMA
264  rxCurBufferDesc->control = ETH_RX_CTRL_NPV | ETH_RX_CTRL_EOWN;
265  //Receive buffer address
266  rxCurBufferDesc->address = KVA_TO_PA(rxBuffer[i]);
267  //Receive status vector
268  rxCurBufferDesc->status1 = 0;
269  rxCurBufferDesc->status2 = 0;
270  //Next descriptor address
271  rxCurBufferDesc->next = KVA_TO_PA(&rxBufferDesc[i + 1]);
272  }
273 
274  //The last descriptor is chained to the first entry
275  rxCurBufferDesc->next = KVA_TO_PA(&rxBufferDesc[0]);
276  //Point to the very first descriptor
277  rxCurBufferDesc = &rxBufferDesc[0];
278 
279  //Starting address of TX descriptor table
280  ETHTXST = KVA_TO_PA(&txBufferDesc[0]);
281  //Starting address of RX descriptor table
282  ETHRXST = KVA_TO_PA(&rxBufferDesc[0]);
283  //Set receive buffer size
284  ETHCON2 = PIC32MX_ETH_RX_BUFFER_SIZE;
285 }
286 
287 
288 /**
289  * @brief PIC32MX Ethernet MAC timer handler
290  *
291  * This routine is periodically called by the TCP/IP stack to
292  * handle periodic operations such as polling the link state
293  *
294  * @param[in] interface Underlying network interface
295  **/
296 
297 void pic32mxEthTick(NetInterface *interface)
298 {
299  //Handle periodic operations
300  interface->phyDriver->tick(interface);
301 }
302 
303 
304 /**
305  * @brief Enable interrupts
306  * @param[in] interface Underlying network interface
307  **/
308 
310 {
311  //Enable Ethernet MAC interrupts
312  IEC1SET = _IEC1_ETHIE_MASK;
313  //Enable Ethernet PHY interrupts
314  interface->phyDriver->enableIrq(interface);
315 }
316 
317 
318 /**
319  * @brief Disable interrupts
320  * @param[in] interface Underlying network interface
321  **/
322 
324 {
325  //Disable Ethernet MAC interrupts
326  IEC1CLR = _IEC1_ETHIE_MASK;
327  //Disable Ethernet PHY interrupts
328  interface->phyDriver->disableIrq(interface);
329 }
330 
331 
332 /**
333  * @brief PIC32MX Ethernet MAC interrupt service routine
334  **/
335 
337 {
338  bool_t flag;
339  uint32_t status;
340 
341  //Interrupt service routine prologue
342  osEnterIsr();
343 
344  //This flag will be set if a higher priority task must be woken
345  flag = FALSE;
346 
347  //Read interrupt status register
348  status = ETHIRQ;
349 
350  //A packet has been transmitted?
351  if(status & _ETHIRQ_TXDONE_MASK)
352  {
353  //Clear TXDONE interrupt flag
354  ETHIRQCLR = _ETHIRQ_TXDONE_MASK;
355 
356  //Check whether the TX buffer is available for writing
357  if(!(txCurBufferDesc->control & ETH_TX_CTRL_EOWN))
358  {
359  //Notify the TCP/IP stack that the transmitter is ready to send
360  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
361  }
362  }
363 
364  //A packet has been received?
365  if(status & _ETHIRQ_PKTPEND_MASK)
366  {
367  //Disable PKTPEND interrupt
368  ETHIENCLR = _ETHIEN_PKTPENDIE_MASK;
369 
370  //Set event flag
371  nicDriverInterface->nicEvent = TRUE;
372  //Notify the TCP/IP stack of the event
373  flag |= osSetEventFromIsr(&netEvent);
374  }
375 
376  //Clear ETHIF interrupt flag before exiting the service routine
377  IFS1CLR = _IFS1_ETHIF_MASK;
378 
379  //Interrupt service routine epilogue
380  osExitIsr(flag);
381 }
382 
383 
384 /**
385  * @brief PIC32MX Ethernet MAC event handler
386  * @param[in] interface Underlying network interface
387  **/
388 
390 {
391  error_t error;
392 
393  //Packet received?
394  if(ETHIRQ & _ETHIRQ_PKTPEND_MASK)
395  {
396  //Process all pending packets
397  do
398  {
399  //Read incoming packet
400  error = pic32mxEthReceivePacket(interface);
401 
402  //No more data in the receive buffer?
403  } while(error != ERROR_BUFFER_EMPTY);
404  }
405 
406  //Re-enable PKTPEND interrupt
407  ETHIENSET = _ETHIEN_PKTPENDIE_MASK;
408 }
409 
410 
411 /**
412  * @brief Send a packet
413  * @param[in] interface Underlying network interface
414  * @param[in] buffer Multi-part buffer containing the data to send
415  * @param[in] offset Offset to the first data byte
416  * @return Error code
417  **/
418 
420  const NetBuffer *buffer, size_t offset)
421 {
422  size_t length;
423  uint32_t value;
424 
425  //Retrieve the length of the packet
426  length = netBufferGetLength(buffer) - offset;
427 
428  //Check the frame length
430  {
431  //The transmitter can accept another packet
432  osSetEvent(&interface->nicTxEvent);
433  //Report an error
434  return ERROR_INVALID_LENGTH;
435  }
436 
437  //Make sure the current buffer is available for writing
438  if(txCurBufferDesc->control & ETH_TX_CTRL_EOWN)
439  return ERROR_FAILURE;
440 
441  //Copy user data to the transmit buffer
442  netBufferRead(PA_TO_KVA1(txCurBufferDesc->address), buffer, offset, length);
443 
444  //Write the number of bytes to send
445  value = (length << 16) & ETH_TX_CTRL_BYTE_COUNT;
446  //Set SOP and EOP flags since the data fits in a single buffer
448  //Give the ownership of the descriptor to the DMA
449  txCurBufferDesc->control = value | ETH_TX_CTRL_EOWN;
450 
451  //Set TXRTS bit to start the transmission
452  ETHCON1SET = _ETHCON1_TXRTS_MASK;
453 
454  //Point to the next descriptor in the list
455  txCurBufferDesc = PA_TO_KVA1(txCurBufferDesc->next);
456 
457  //Check whether the next buffer is available for writing
458  if(!(txCurBufferDesc->control & ETH_TX_CTRL_EOWN))
459  {
460  //The transmitter can accept another packet
461  osSetEvent(&interface->nicTxEvent);
462  }
463 
464  //Data successfully written
465  return NO_ERROR;
466 }
467 
468 
469 /**
470  * @brief Receive a packet
471  * @param[in] interface Underlying network interface
472  * @return Error code
473  **/
474 
476 {
477  static uint8_t temp[PIC32MX_ETH_RX_BUFFER_SIZE];
478  error_t error;
479  size_t n;
480 
481  //The current buffer is available for reading?
482  if(!(rxCurBufferDesc->control & ETH_RX_CTRL_EOWN))
483  {
484  //SOP and EOP flags should be set
485  if((rxCurBufferDesc->control & ETH_RX_CTRL_SOP) &&
486  (rxCurBufferDesc->control & ETH_RX_CTRL_EOP))
487  {
488  //Make sure no error occurred
489  if(rxCurBufferDesc->status2 & ETH_RX_STATUS2_OK)
490  {
491  //Retrieve the length of the frame
492  n = (rxCurBufferDesc->control & ETH_RX_CTRL_BYTE_COUNT) >> 16;
493  //Limit the number of data to read
495 
496  //Copy data from the receive buffer
497  memcpy(temp, PA_TO_KVA1(rxCurBufferDesc->address), n);
498 
499  //Pass the packet to the upper layer
500  nicProcessPacket(interface, temp, n);
501 
502  //Valid packet received
503  error = NO_ERROR;
504  }
505  else
506  {
507  //The received packet contains an error
508  error = ERROR_INVALID_PACKET;
509  }
510  }
511  else
512  {
513  //The packet is not valid
514  error = ERROR_INVALID_PACKET;
515  }
516 
517  //Give the ownership of the descriptor back to the DMA
518  rxCurBufferDesc->control = ETH_RX_CTRL_NPV | ETH_RX_CTRL_EOWN;
519 
520  //Point to the next descriptor in the list
521  rxCurBufferDesc = PA_TO_KVA1(rxCurBufferDesc->next);
522 
523  //Decrement BUFCNT counter
524  ETHCON1SET = _ETHCON1_BUFCDEC_MASK;
525  }
526  else
527  {
528  //No more data in the receive buffer
529  error = ERROR_BUFFER_EMPTY;
530  }
531 
532  //Return status code
533  return error;
534 }
535 
536 
537 /**
538  * @brief Configure MAC address filtering
539  * @param[in] interface Underlying network interface
540  * @return Error code
541  **/
542 
544 {
545  uint_t i;
546  uint_t k;
547  uint32_t crc;
548  uint32_t hashTable[2];
549  MacFilterEntry *entry;
550 
551  //Debug message
552  TRACE_DEBUG("Updating MAC filter...\r\n");
553 
554  //Clear hash table
555  hashTable[0] = 0;
556  hashTable[1] = 0;
557 
558  //The MAC address filter contains the list of MAC addresses to accept
559  //when receiving an Ethernet frame
560  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
561  {
562  //Point to the current entry
563  entry = &interface->macAddrFilter[i];
564 
565  //Valid entry?
566  if(entry->refCount > 0)
567  {
568  //Compute CRC over the current MAC address
569  crc = pic32mxEthCalcCrc(&entry->addr, sizeof(MacAddr));
570  //Calculate the corresponding index in the table
571  k = (crc >> 23) & 0x3F;
572  //Update hash table contents
573  hashTable[k / 32] |= (1 << (k % 32));
574  }
575  }
576 
577  //Write the hash table
578  ETHHT0 = hashTable[0];
579  ETHHT1 = hashTable[1];
580 
581  //Debug message
582  TRACE_DEBUG(" ETHHT0 = %08" PRIX32 "\r\n", ETHHT0);
583  TRACE_DEBUG(" ETHHT1 = %08" PRIX32 "\r\n", ETHHT1);
584 
585  //Successful processing
586  return NO_ERROR;
587 }
588 
589 
590 /**
591  * @brief Adjust MAC configuration parameters for proper operation
592  * @param[in] interface Underlying network interface
593  * @return Error code
594  **/
595 
597 {
598  //Check current operating speed
599  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
600  {
601  //100BASE-TX operation mode
602  EMAC1SUPPSET = _EMAC1SUPP_SPEEDRMII_MASK;
603  }
604  else
605  {
606  //10BASE-T operation mode
607  EMAC1SUPPCLR = _EMAC1SUPP_SPEEDRMII_MASK;
608  }
609 
610  //Half-duplex or full-duplex mode?
611  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
612  {
613  //Configure FULLDPLX bit to match the current duplex mode
614  EMAC1CFG2SET = _EMAC1CFG2_FULLDPLX_MASK;
615  //Configure the Back-to-Back Inter-Packet Gap register
616  EMAC1IPGT = 0x15;
617  }
618  else
619  {
620  //Configure FULLDPLX bit to match the current duplex mode
621  EMAC1CFG2CLR = _EMAC1CFG2_FULLDPLX_MASK;
622  //Configure the Back-to-Back Inter-Packet Gap register
623  EMAC1IPGT = 0x12;
624  }
625 
626  //Successful processing
627  return NO_ERROR;
628 }
629 
630 
631 /**
632  * @brief Write PHY register
633  * @param[in] opcode Access type (2 bits)
634  * @param[in] phyAddr PHY address (5 bits)
635  * @param[in] regAddr Register address (5 bits)
636  * @param[in] data Register value
637  **/
638 
639 void pic32mxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
640  uint8_t regAddr, uint16_t data)
641 {
642  //Valid opcode?
643  if(opcode == SMI_OPCODE_WRITE)
644  {
645  //Set PHY address and register address
646  EMAC1MADR = (phyAddr << _EMAC1MADR_PHYADDR_POSITION) | regAddr;
647  //Start a write operation
648  EMAC1MWTD = data & _EMAC1MWTD_MWTD_MASK;
649 
650  //Wait for busy bit to be set
651  __asm__ __volatile__ ("nop;");
652  __asm__ __volatile__ ("nop;");
653  __asm__ __volatile__ ("nop;");
654 
655  //Wait for the write to complete
656  while(EMAC1MIND & _EMAC1MIND_MIIMBUSY_MASK)
657  {
658  }
659  }
660  else
661  {
662  //The MAC peripheral only supports standard Clause 22 opcodes
663  }
664 }
665 
666 
667 /**
668  * @brief Read PHY register
669  * @param[in] opcode Access type (2 bits)
670  * @param[in] phyAddr PHY address (5 bits)
671  * @param[in] regAddr Register address (5 bits)
672  * @return Register value
673  **/
674 
675 uint16_t pic32mxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
676  uint8_t regAddr)
677 {
678  uint16_t data;
679 
680  //Valid opcode?
681  if(opcode == SMI_OPCODE_READ)
682  {
683  //Set PHY address and register address
684  EMAC1MADR = (phyAddr << _EMAC1MADR_PHYADDR_POSITION) | regAddr;
685  //Start a read operation
686  EMAC1MCMD = _EMAC1MCMD_READ_MASK;
687 
688  //Wait for busy bit to be set
689  __asm__ __volatile__ ("nop;");
690  __asm__ __volatile__ ("nop;");
691  __asm__ __volatile__ ("nop;");
692 
693  //Wait for the read to complete
694  while(EMAC1MIND & _EMAC1MIND_MIIMBUSY_MASK)
695  {
696  }
697 
698  //Clear command register
699  EMAC1MCMD = 0;
700  //Get register value
701  data = EMAC1MRDD & _EMAC1MRDD_MRDD_MASK;
702  }
703  else
704  {
705  //The MAC peripheral only supports standard Clause 22 opcodes
706  data = 0;
707  }
708 
709  //Return the value of the PHY register
710  return data;
711 }
712 
713 
714 /**
715  * @brief CRC calculation
716  * @param[in] data Pointer to the data over which to calculate the CRC
717  * @param[in] length Number of bytes to process
718  * @return Resulting CRC value
719  **/
720 
721 uint32_t pic32mxEthCalcCrc(const void *data, size_t length)
722 {
723  uint_t i;
724  uint_t j;
725 
726  //Point to the data over which to calculate the CRC
727  const uint8_t *p = (uint8_t *) data;
728  //CRC preset value
729  uint32_t crc = 0xFFFFFFFF;
730 
731  //Loop through data
732  for(i = 0; i < length; i++)
733  {
734  //The message is processed bit by bit
735  for(j = 0; j < 8; j++)
736  {
737  //Update CRC value
738  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
739  crc = (crc << 1) ^ 0x04C11DB7;
740  else
741  crc = crc << 1;
742  }
743  }
744 
745  //Return CRC value
746  return crc;
747 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define ETH_TX_CTRL_BYTE_COUNT
#define PIC32MX_ETH_RX_BUFFER_COUNT
#define PIC32MX_ETH_RX_BUFFER_SIZE
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
error_t pic32mxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
error_t pic32mxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void macAddrToEui64(const MacAddr *macAddr, Eui64 *interfaceId)
Map a MAC address to the IPv6 modified EUI-64 identifier.
Definition: ethernet.c:800
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define ETH_RX_CTRL_SOP
#define ETH_RX_CTRL_NPV
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
error_t pic32mxEthInit(NetInterface *interface)
PIC32MX Ethernet MAC initialization.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
void pic32mxEthInitBufferDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t pic32mxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define osExitIsr(flag)
#define ETH_RX_CTRL_EOP
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define PIC32MX_ETH_IRQ_PRIORITY
void pic32mxEthTick(NetInterface *interface)
PIC32MX Ethernet MAC timer handler.
#define ETH_TX_CTRL_EOP
uint16_t pic32mxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define ETH_TX_CTRL_SOP
#define FALSE
Definition: os_port.h:46
#define ETH_RX_CTRL_EOWN
error_t
Error codes.
Definition: error.h:42
void pic32mxEthIrqHandler(void)
PIC32MX Ethernet MAC interrupt service routine.
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define PIC32MX_ETH_IRQ_SUB_PRIORITY
#define txBuffer
@ ERROR_INVALID_PACKET
Definition: error.h:138
#define NetInterface
Definition: net.h:36
#define PIC32MX_ETH_TX_BUFFER_COUNT
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ETH_TX_CTRL_NPV
@ ERROR_INVALID_LENGTH
Definition: error.h:109
PIC32MX Ethernet MAC controller.
void pic32mxEthInitGpio(NetInterface *interface)
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
error_t pic32mxEthReceivePacket(NetInterface *interface)
Receive a packet.
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define PIC32MX_ETH_TX_BUFFER_SIZE
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
uint32_t pic32mxEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define TRACE_DEBUG(...)
Definition: debug.h:106
void pic32mxEthEventHandler(NetInterface *interface)
PIC32MX Ethernet MAC event handler.
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
#define osEnterIsr()
RX buffer descriptor.
#define macCompAddr(macAddr1, macAddr2)
Definition: ethernet.h:107
void pic32mxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
TX buffer descriptor.
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
#define ETH_RX_CTRL_BYTE_COUNT
uint8_t value[]
Definition: dtls_misc.h:150
unsigned int uint_t
Definition: compiler_port.h:45
#define ETH_TX_CTRL_EOWN
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
void pic32mxEthDisableIrq(NetInterface *interface)
Disable interrupts.
NIC driver.
Definition: nic.h:179
const NicDriver pic32mxEthDriver
PIC32MX Ethernet MAC driver.
void pic32mxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
#define ETH_RX_STATUS2_OK
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
__start_packed struct @108 MacAddr
MAC address.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79
#define _EMAC1MCFG_CLKSEL_DIV40