pic32mx_eth_driver.c
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1 /**
2  * @file pic32mx_eth_driver.c
3  * @brief PIC32MX Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <p32xxxx.h>
34 #include <sys/kmem.h>
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //Transmit buffer
44  __attribute__((aligned(4)));
45 //Receive buffer
47  __attribute__((aligned(4)));
48 //Transmit buffer descriptors
50  __attribute__((aligned(4)));
51 //Receive buffer descriptors
53  __attribute__((aligned(4)));
54 
55 //Pointer to the current TX buffer descriptor
56 static Pic32mxTxBufferDesc *txCurBufferDesc;
57 //Pointer to the current RX buffer descriptor
58 static Pic32mxRxBufferDesc *rxCurBufferDesc;
59 
60 
61 /**
62  * @brief PIC32MX Ethernet MAC driver
63  **/
64 
66 {
68  ETH_MTU,
79  TRUE,
80  TRUE,
81  TRUE,
82  FALSE
83 };
84 
85 
86 /**
87  * @brief PIC32MX Ethernet MAC initialization
88  * @param[in] interface Underlying network interface
89  * @return Error code
90  **/
91 
93 {
94  error_t error;
95 
96  //Debug message
97  TRACE_INFO("Initializing PIC32MX Ethernet MAC...\r\n");
98 
99  //Save underlying network interface
100  nicDriverInterface = interface;
101 
102  //GPIO configuration
103  pic32mxEthInitGpio(interface);
104 
105  //Disable Ethernet interrupts
106  IEC1CLR = _IEC1_ETHIE_MASK;
107  //Turn the Ethernet controller off
108  ETHCON1CLR = _ETHCON1_ON_MASK | _ETHCON1_TXRTS_POSITION | _ETHCON1_RXEN_MASK;
109 
110  //Wait activity abort by polling the ETHBUSY bit
111  while(ETHSTAT & _ETHSTAT_ETHBUSY_MASK);
112 
113  //Enable the Ethernet controller by setting the ON bit
114  ETHCON1SET = _ETHCON1_ON_MASK;
115 
116  //Clear Ethernet interrupt flag
117  IFS1CLR = _IFS1_ETHIF_MASK;
118  //Disable any Ethernet controller interrupt generation
119  ETHIEN = 0;
120  ETHIRQ = 0;
121  //Clear the TX and RX start addresses
122  ETHTXST = 0;
123  ETHRXST = 0;
124 
125  //Reset the MAC using SOFTRESET
126  EMAC1CFG1SET = _EMAC1CFG1_SOFTRESET_MASK;
127  EMAC1CFG1CLR = _EMAC1CFG1_SOFTRESET_MASK;
128 
129  //Reset the RMII module
130  EMAC1SUPPSET = _EMAC1SUPP_RESETRMII_MASK;
131  EMAC1SUPPCLR = _EMAC1SUPP_RESETRMII_MASK;
132 
133  //Issue an MIIM block reset by setting the RESETMGMT bit
134  EMAC1MCFGSET = _EMAC1MCFG_RESETMGMT_MASK;
135  EMAC1MCFGCLR = _EMAC1MCFG_RESETMGMT_MASK;
136 
137  //Select the proper divider for the MDC clock
138  EMAC1MCFG = _EMAC1MCFG_CLKSEL_DIV40;
139 
140  //PHY transceiver initialization
141  error = interface->phyDriver->init(interface);
142  //Failed to initialize PHY transceiver?
143  if(error)
144  return error;
145 
146  //Optionally set the station MAC address
147  if(macCompAddr(&interface->macAddr, &MAC_UNSPECIFIED_ADDR))
148  {
149  //Use the factory preprogrammed station address
150  interface->macAddr.w[0] = EMAC1SA2;
151  interface->macAddr.w[1] = EMAC1SA1;
152  interface->macAddr.w[2] = EMAC1SA0;
153 
154  //Generate the 64-bit interface identifier
155  macAddrToEui64(&interface->macAddr, &interface->eui64);
156  }
157  else
158  {
159  //Override the factory preprogrammed address
160  EMAC1SA0 = interface->macAddr.w[2];
161  EMAC1SA1 = interface->macAddr.w[1];
162  EMAC1SA2 = interface->macAddr.w[0];
163  }
164 
165  //Initialize hash table
166  ETHHT0 = 0;
167  ETHHT1 = 0;
168 
169  //Configure the receive filter
170  ETHRXFC = _ETHRXFC_HTEN_MASK | _ETHRXFC_CRCOKEN_MASK |
171  _ETHRXFC_RUNTEN_MASK | _ETHRXFC_UCEN_MASK | _ETHRXFC_BCEN_MASK;
172 
173  //Disable flow control
174  EMAC1CFG1 = _EMAC1CFG1_RXENABLE_MASK;
175  //Automatic padding and CRC generation
176  EMAC1CFG2 = _EMAC1CFG2_PADENABLE_MASK | _EMAC1CFG2_CRCENABLE_MASK;
177  //Set the maximum frame length
178  EMAC1MAXF = 1518;
179 
180  //Initialize DMA descriptor lists
181  pic32mxEthInitBufferDesc(interface);
182 
183  //Enable desired interrupts
184  ETHIENSET = _ETHIEN_PKTPENDIE_MASK | _ETHIEN_TXDONEIE_MASK;
185 
186  //Set interrupt priority
187  IPC12CLR = _IPC12_ETHIP_MASK;
188  IPC12SET = (PIC32MX_ETH_IRQ_PRIORITY << _IPC12_ETHIP_POSITION);
189  //Set interrupt subpriority
190  IPC12CLR = _IPC12_ETHIS_MASK;
191  IPC12SET = (PIC32MX_ETH_IRQ_SUB_PRIORITY << _IPC12_ETHIS_POSITION);
192 
193  //Enable the reception by setting the RXEN bit
194  ETHCON1SET = _ETHCON1_RXEN_MASK;
195 
196  //Accept any packets from the upper layer
197  osSetEvent(&interface->nicTxEvent);
198 
199  //Successful initialization
200  return NO_ERROR;
201 }
202 
203 
204 //PIC32 Ethernet Starter Kit, PIC32 Ethernet Starter Kit II or
205 //chipKIT Pro MX7 evaluation board?
206 #if defined(USE_PIC32_ETH_STARTER_KIT) || defined(USE_PIC32_ETH_STARTER_KIT_2) || \
207  defined(USE_CHIPKIT_PRO_MX7)
208 
209 /**
210  * @brief GPIO configuration
211  * @param[in] interface Underlying network interface
212  **/
213 
214 void pic32mxEthInitGpio(NetInterface *interface)
215 {
216  //No analog pins are shared with the alternate RMII interface
217 }
218 
219 #endif
220 
221 
222 /**
223  * @brief Initialize DMA descriptor lists
224  * @param[in] interface Underlying network interface
225  **/
226 
228 {
229  uint_t i;
230 
231  //Initialize TX descriptor list
232  for(i = 0; i < PIC32MX_ETH_TX_BUFFER_COUNT; i++)
233  {
234  //Point to the current descriptor
235  txCurBufferDesc = KVA0_TO_KVA1(&txBufferDesc[i]);
236 
237  //Use linked list rather than linear list
238  txCurBufferDesc->control = ETH_TX_CTRL_NPV;
239  //Transmit buffer address
240  txCurBufferDesc->address = (uint32_t) KVA_TO_PA(txBuffer[i]);
241  //Transmit status vector
242  txCurBufferDesc->status1 = 0;
243  txCurBufferDesc->status2 = 0;
244  //Next descriptor address
245  txCurBufferDesc->next = (uint32_t) KVA_TO_PA(&txBufferDesc[i + 1]);
246  }
247 
248  //The last descriptor is chained to the first entry
249  txCurBufferDesc->next = (uint32_t) KVA_TO_PA(&txBufferDesc[0]);
250  //Point to the very first descriptor
251  txCurBufferDesc = KVA0_TO_KVA1(&txBufferDesc[0]);
252 
253  //Initialize RX descriptor list
254  for(i = 0; i < PIC32MX_ETH_RX_BUFFER_COUNT; i++)
255  {
256  //Point to the current descriptor
257  rxCurBufferDesc = KVA0_TO_KVA1(&rxBufferDesc[i]);
258 
259  //The descriptor is initially owned by the DMA
260  rxCurBufferDesc->control = ETH_RX_CTRL_NPV | ETH_RX_CTRL_EOWN;
261  //Receive buffer address
262  rxCurBufferDesc->address = (uint32_t) KVA_TO_PA(rxBuffer[i]);
263  //Receive status vector
264  rxCurBufferDesc->status1 = 0;
265  rxCurBufferDesc->status2 = 0;
266  //Next descriptor address
267  rxCurBufferDesc->next = (uint32_t) KVA_TO_PA(&rxBufferDesc[i + 1]);
268  }
269 
270  //The last descriptor is chained to the first entry
271  rxCurBufferDesc->next = (uint32_t) KVA_TO_PA(&rxBufferDesc[0]);
272  //Point to the very first descriptor
273  rxCurBufferDesc = KVA0_TO_KVA1(&rxBufferDesc[0]);
274 
275  //Starting address of TX descriptor table
276  ETHTXST = (uint32_t) KVA_TO_PA(&txBufferDesc[0]);
277  //Starting address of RX descriptor table
278  ETHRXST = (uint32_t) KVA_TO_PA(&rxBufferDesc[0]);
279  //Set receive buffer size
280  ETHCON2 = PIC32MX_ETH_RX_BUFFER_SIZE;
281 }
282 
283 
284 /**
285  * @brief PIC32MX Ethernet MAC timer handler
286  *
287  * This routine is periodically called by the TCP/IP stack to
288  * handle periodic operations such as polling the link state
289  *
290  * @param[in] interface Underlying network interface
291  **/
292 
293 void pic32mxEthTick(NetInterface *interface)
294 {
295  //Handle periodic operations
296  interface->phyDriver->tick(interface);
297 }
298 
299 
300 /**
301  * @brief Enable interrupts
302  * @param[in] interface Underlying network interface
303  **/
304 
306 {
307  //Enable Ethernet MAC interrupts
308  IEC1SET = _IEC1_ETHIE_MASK;
309  //Enable Ethernet PHY interrupts
310  interface->phyDriver->enableIrq(interface);
311 }
312 
313 
314 /**
315  * @brief Disable interrupts
316  * @param[in] interface Underlying network interface
317  **/
318 
320 {
321  //Disable Ethernet MAC interrupts
322  IEC1CLR = _IEC1_ETHIE_MASK;
323  //Disable Ethernet PHY interrupts
324  interface->phyDriver->disableIrq(interface);
325 }
326 
327 
328 /**
329  * @brief PIC32MX Ethernet MAC interrupt service routine
330  **/
331 
333 {
334  bool_t flag;
335  uint32_t status;
336 
337  //Enter interrupt service routine
338  osEnterIsr();
339 
340  //This flag will be set if a higher priority task must be woken
341  flag = FALSE;
342 
343  //Read interrupt status register
344  status = ETHIRQ;
345 
346  //A packet has been transmitted?
347  if(status & _ETHIRQ_TXDONE_MASK)
348  {
349  //Clear TXDONE interrupt flag
350  ETHIRQCLR = _ETHIRQ_TXDONE_MASK;
351 
352  //Check whether the TX buffer is available for writing
353  if(!(txCurBufferDesc->control & ETH_TX_CTRL_EOWN))
354  {
355  //Notify the TCP/IP stack that the transmitter is ready to send
356  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
357  }
358  }
359 
360  //A packet has been received?
361  if(status & _ETHIRQ_PKTPEND_MASK)
362  {
363  //Disable PKTPEND interrupt
364  ETHIENCLR = _ETHIEN_PKTPENDIE_MASK;
365 
366  //Set event flag
367  nicDriverInterface->nicEvent = TRUE;
368  //Notify the TCP/IP stack of the event
369  flag |= osSetEventFromIsr(&netEvent);
370  }
371 
372  //Clear ETHIF interrupt flag before exiting the service routine
373  IFS1CLR = _IFS1_ETHIF_MASK;
374 
375  //Leave interrupt service routine
376  osExitIsr(flag);
377 }
378 
379 
380 /**
381  * @brief PIC32MX Ethernet MAC event handler
382  * @param[in] interface Underlying network interface
383  **/
384 
386 {
387  error_t error;
388 
389  //Packet received?
390  if(ETHIRQ & _ETHIRQ_PKTPEND_MASK)
391  {
392  //Process all pending packets
393  do
394  {
395  //Read incoming packet
396  error = pic32mxEthReceivePacket(interface);
397 
398  //No more data in the receive buffer?
399  } while(error != ERROR_BUFFER_EMPTY);
400  }
401 
402  //Re-enable PKTPEND interrupt
403  ETHIENSET = _ETHIEN_PKTPENDIE_MASK;
404 }
405 
406 
407 /**
408  * @brief Send a packet
409  * @param[in] interface Underlying network interface
410  * @param[in] buffer Multi-part buffer containing the data to send
411  * @param[in] offset Offset to the first data byte
412  * @return Error code
413  **/
414 
416  const NetBuffer *buffer, size_t offset)
417 {
418  size_t length;
419  uint32_t value;
420 
421  //Retrieve the length of the packet
422  length = netBufferGetLength(buffer) - offset;
423 
424  //Check the frame length
426  {
427  //The transmitter can accept another packet
428  osSetEvent(&interface->nicTxEvent);
429  //Report an error
430  return ERROR_INVALID_LENGTH;
431  }
432 
433  //Make sure the current buffer is available for writing
434  if(txCurBufferDesc->control & ETH_TX_CTRL_EOWN)
435  return ERROR_FAILURE;
436 
437  //Copy user data to the transmit buffer
438  netBufferRead(PA_TO_KVA1(txCurBufferDesc->address), buffer, offset, length);
439 
440  //Write the number of bytes to send
441  value = (length << 16) & ETH_TX_CTRL_BYTE_COUNT;
442  //Set SOP and EOP flags since the data fits in a single buffer
444  //Give the ownership of the descriptor to the DMA
445  txCurBufferDesc->control = value | ETH_TX_CTRL_EOWN;
446 
447  //Set TXRTS bit to start the transmission
448  ETHCON1SET = _ETHCON1_TXRTS_MASK;
449 
450  //Point to the next descriptor in the list
451  txCurBufferDesc = PA_TO_KVA1(txCurBufferDesc->next);
452 
453  //Check whether the next buffer is available for writing
454  if(!(txCurBufferDesc->control & ETH_TX_CTRL_EOWN))
455  {
456  //The transmitter can accept another packet
457  osSetEvent(&interface->nicTxEvent);
458  }
459 
460  //Data successfully written
461  return NO_ERROR;
462 }
463 
464 
465 /**
466  * @brief Receive a packet
467  * @param[in] interface Underlying network interface
468  * @return Error code
469  **/
470 
472 {
473  static uint8_t temp[PIC32MX_ETH_RX_BUFFER_SIZE];
474  error_t error;
475  size_t n;
476 
477  //The current buffer is available for reading?
478  if(!(rxCurBufferDesc->control & ETH_RX_CTRL_EOWN))
479  {
480  //SOP and EOP flags should be set
481  if((rxCurBufferDesc->control & ETH_RX_CTRL_SOP) &&
482  (rxCurBufferDesc->control & ETH_RX_CTRL_EOP))
483  {
484  //Make sure no error occurred
485  if(rxCurBufferDesc->status2 & ETH_RX_STATUS2_OK)
486  {
487  //Retrieve the length of the frame
488  n = (rxCurBufferDesc->control & ETH_RX_CTRL_BYTE_COUNT) >> 16;
489  //Limit the number of data to read
491 
492  //Copy data from the receive buffer
493  memcpy(temp, PA_TO_KVA1(rxCurBufferDesc->address), n);
494 
495  //Pass the packet to the upper layer
496  nicProcessPacket(interface, temp, n);
497 
498  //Valid packet received
499  error = NO_ERROR;
500  }
501  else
502  {
503  //The received packet contains an error
504  error = ERROR_INVALID_PACKET;
505  }
506  }
507  else
508  {
509  //The packet is not valid
510  error = ERROR_INVALID_PACKET;
511  }
512 
513  //Give the ownership of the descriptor back to the DMA
514  rxCurBufferDesc->control = ETH_RX_CTRL_NPV | ETH_RX_CTRL_EOWN;
515 
516  //Point to the next descriptor in the list
517  rxCurBufferDesc = PA_TO_KVA1(rxCurBufferDesc->next);
518 
519  //Decrement BUFCNT counter
520  ETHCON1SET = _ETHCON1_BUFCDEC_MASK;
521  }
522  else
523  {
524  //No more data in the receive buffer
525  error = ERROR_BUFFER_EMPTY;
526  }
527 
528  //Return status code
529  return error;
530 }
531 
532 
533 /**
534  * @brief Configure MAC address filtering
535  * @param[in] interface Underlying network interface
536  * @return Error code
537  **/
538 
540 {
541  uint_t i;
542  uint_t k;
543  uint32_t crc;
544  uint32_t hashTable[2];
545  MacFilterEntry *entry;
546 
547  //Debug message
548  TRACE_DEBUG("Updating PIC32MX hash table...\r\n");
549 
550  //Clear hash table
551  hashTable[0] = 0;
552  hashTable[1] = 0;
553 
554  //The MAC address filter contains the list of MAC addresses to accept
555  //when receiving an Ethernet frame
556  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
557  {
558  //Point to the current entry
559  entry = &interface->macAddrFilter[i];
560 
561  //Valid entry?
562  if(entry->refCount > 0)
563  {
564  //Compute CRC over the current MAC address
565  crc = pic32mxEthCalcCrc(&entry->addr, sizeof(MacAddr));
566  //Calculate the corresponding index in the table
567  k = (crc >> 23) & 0x3F;
568  //Update hash table contents
569  hashTable[k / 32] |= (1 << (k % 32));
570  }
571  }
572 
573  //Write the hash table
574  ETHHT0 = hashTable[0];
575  ETHHT1 = hashTable[1];
576 
577  //Debug message
578  TRACE_DEBUG(" ETHHT0 = %08" PRIX32 "\r\n", ETHHT0);
579  TRACE_DEBUG(" ETHHT1 = %08" PRIX32 "\r\n", ETHHT1);
580 
581  //Successful processing
582  return NO_ERROR;
583 }
584 
585 
586 /**
587  * @brief Adjust MAC configuration parameters for proper operation
588  * @param[in] interface Underlying network interface
589  * @return Error code
590  **/
591 
593 {
594  //Check current operating speed
595  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
596  {
597  //100BASE-TX operation mode
598  EMAC1SUPPSET = _EMAC1SUPP_SPEEDRMII_MASK;
599  }
600  else
601  {
602  //10BASE-T operation mode
603  EMAC1SUPPCLR = _EMAC1SUPP_SPEEDRMII_MASK;
604  }
605 
606  //Half-duplex or full-duplex mode?
607  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
608  {
609  //Configure FULLDPLX bit to match the current duplex mode
610  EMAC1CFG2SET = _EMAC1CFG2_FULLDPLX_MASK;
611  //Configure the Back-to-Back Inter-Packet Gap register
612  EMAC1IPGT = 0x15;
613  }
614  else
615  {
616  //Configure FULLDPLX bit to match the current duplex mode
617  EMAC1CFG2CLR = _EMAC1CFG2_FULLDPLX_MASK;
618  //Configure the Back-to-Back Inter-Packet Gap register
619  EMAC1IPGT = 0x12;
620  }
621 
622  //Successful processing
623  return NO_ERROR;
624 }
625 
626 
627 /**
628  * @brief Write PHY register
629  * @param[in] phyAddr PHY address
630  * @param[in] regAddr Register address
631  * @param[in] data Register value
632  **/
633 
634 void pic32mxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
635 {
636  //Set PHY address and register address
637  EMAC1MADR = (phyAddr << _EMAC1MADR_PHYADDR_POSITION) | regAddr;
638  //Start a write operation
639  EMAC1MWTD = data & _EMAC1MWTD_MWTD_MASK;
640 
641  //Wait for busy bit to be set
642  __asm__ __volatile__ ("nop;");
643  __asm__ __volatile__ ("nop;");
644  __asm__ __volatile__ ("nop;");
645 
646  //Wait for the write to complete
647  while(EMAC1MIND & _EMAC1MIND_MIIMBUSY_MASK);
648 }
649 
650 
651 /**
652  * @brief Read PHY register
653  * @param[in] phyAddr PHY address
654  * @param[in] regAddr Register address
655  * @return Register value
656  **/
657 
658 uint16_t pic32mxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
659 {
660  //Set PHY address and register address
661  EMAC1MADR = (phyAddr << _EMAC1MADR_PHYADDR_POSITION) | regAddr;
662  //Start a read operation
663  EMAC1MCMD = _EMAC1MCMD_READ_MASK;
664 
665  //Wait for busy bit to be set
666  __asm__ __volatile__ ("nop;");
667  __asm__ __volatile__ ("nop;");
668  __asm__ __volatile__ ("nop;");
669 
670  //Wait for the read to complete
671  while(EMAC1MIND & _EMAC1MIND_MIIMBUSY_MASK);
672 
673  //Clear command register
674  EMAC1MCMD = 0;
675  //Return PHY register contents
676  return EMAC1MRDD & _EMAC1MRDD_MRDD_MASK;
677 }
678 
679 
680 /**
681  * @brief CRC calculation
682  * @param[in] data Pointer to the data over which to calculate the CRC
683  * @param[in] length Number of bytes to process
684  * @return Resulting CRC value
685  **/
686 
687 uint32_t pic32mxEthCalcCrc(const void *data, size_t length)
688 {
689  uint_t i;
690  uint_t j;
691 
692  //Point to the data over which to calculate the CRC
693  const uint8_t *p = (uint8_t *) data;
694  //CRC preset value
695  uint32_t crc = 0xFFFFFFFF;
696 
697  //Loop through data
698  for(i = 0; i < length; i++)
699  {
700  //The message is processed bit by bit
701  for(j = 0; j < 8; j++)
702  {
703  //Update CRC value
704  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
705  crc = (crc << 1) ^ 0x04C11DB7;
706  else
707  crc = crc << 1;
708  }
709  }
710 
711  //Return CRC value
712  return crc;
713 }
error_t pic32mxEthInit(NetInterface *interface)
PIC32MX Ethernet MAC initialization.
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define PIC32MX_ETH_TX_BUFFER_SIZE
void pic32mxEthEnableIrq(NetInterface *interface)
Enable interrupts.
TCP/IP stack core.
#define ETH_TX_CTRL_BYTE_COUNT
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define PIC32MX_ETH_RX_BUFFER_SIZE
Generic error code.
Definition: error.h:43
#define txBuffer
error_t pic32mxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ETH_TX_CTRL_SOP
error_t pic32mxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint32_t pic32mxEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ETH_RX_CTRL_EOP
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define ETH_RX_CTRL_BYTE_COUNT
const NicDriver pic32mxEthDriver
PIC32MX Ethernet MAC driver.
PIC32MX Ethernet MAC controller.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define ETH_TX_CTRL_EOWN
RX buffer descriptor.
#define PIC32MX_ETH_TX_BUFFER_COUNT
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
void pic32mxEthEventHandler(NetInterface *interface)
PIC32MX Ethernet MAC event handler.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define _EMAC1MCFG_CLKSEL_DIV40
#define ETH_TX_CTRL_NPV
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
error_t pic32mxEthReceivePacket(NetInterface *interface)
Receive a packet.
#define ETH_TX_CTRL_EOP
void pic32mxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void pic32mxEthDisableIrq(NetInterface *interface)
Disable interrupts.
TX buffer descriptor.
void macAddrToEui64(const MacAddr *macAddr, Eui64 *interfaceId)
Map a MAC address to the IPv6 modified EUI-64 identifier.
Definition: ethernet.c:1266
#define PIC32MX_ETH_IRQ_PRIORITY
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_RX_CTRL_NPV
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define PIC32MX_ETH_IRQ_SUB_PRIORITY
#define ETH_RX_STATUS2_OK
#define rxBuffer
uint16_t pic32mxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define ETH_RX_CTRL_EOWN
#define PIC32MX_ETH_RX_BUFFER_COUNT
unsigned int uint_t
Definition: compiler_port.h:43
void pic32mxEthInitBufferDesc(NetInterface *interface)
Initialize DMA descriptor lists.
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
#define macCompAddr(macAddr1, macAddr2)
Definition: ethernet.h:95
void pic32mxEthTick(NetInterface *interface)
PIC32MX Ethernet MAC timer handler.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
error_t pic32mxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void pic32mxEthInitGpio(NetInterface *interface)
#define osExitIsr(flag)
#define osEnterIsr()
void pic32mxEthIrqHandler(void)
PIC32MX Ethernet MAC interrupt service routine.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98
#define ETH_RX_CTRL_SOP