32 #define TRACE_LEVEL NIC_TRACE_LEVEL
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 8
51 #pragma data_alignment = 8
54 #pragma data_alignment = 4
57 #pragma data_alignment = 4
79 static uint_t txBufferIndex;
81 static uint_t rxBufferIndex;
118 volatile uint32_t status;
121 TRACE_INFO(
"Initializing SAM3X Ethernet MAC...\r\n");
124 nicDriverInterface = interface;
127 PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
136 EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
138 EMAC->EMAC_NCR |= EMAC_NCR_MPE;
141 if(interface->phyDriver != NULL)
144 error = interface->phyDriver->init(interface);
146 else if(interface->switchDriver != NULL)
149 error = interface->switchDriver->init(interface);
164 EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
165 EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
168 EMAC->EMAC_SA[1].EMAC_SAxB = 0;
169 EMAC->EMAC_SA[2].EMAC_SAxB = 0;
170 EMAC->EMAC_SA[3].EMAC_SAxB = 0;
177 EMAC->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
183 EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
184 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
187 EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
190 EMAC->EMAC_IDR = 0xFFFFFFFF;
193 EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
194 EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
197 status = EMAC->EMAC_ISR;
208 EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
226 #if defined(USE_SAM3X_EK)
230 PMC->PMC_PCER0 = (1 << ID_PIOB);
233 mask = PIO_PB9A_EMDIO | PIO_PB8A_EMDC | PIO_PB7A_ERXER | PIO_PB6A_ERX1 |
234 PIO_PB5A_ERX0 | PIO_PB4A_ERXDV | PIO_PB3A_ETX1 | PIO_PB2A_ETX0 |
235 PIO_PB1A_ETXEN | PIO_PB0A_ETXCK;
238 PIOB->PIO_PUDR =
mask;
240 PIOB->PIO_IDR =
mask;
242 PIOB->PIO_ABSR &= ~
mask;
244 PIOB->PIO_PDR =
mask;
247 EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
286 rxBufferDesc[i].
status = 0;
295 EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
297 EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
313 if(interface->phyDriver != NULL)
316 interface->phyDriver->tick(interface);
318 else if(interface->switchDriver != NULL)
321 interface->switchDriver->tick(interface);
338 NVIC_EnableIRQ(EMAC_IRQn);
341 if(interface->phyDriver != NULL)
344 interface->phyDriver->enableIrq(interface);
346 else if(interface->switchDriver != NULL)
349 interface->switchDriver->enableIrq(interface);
366 NVIC_DisableIRQ(EMAC_IRQn);
369 if(interface->phyDriver != NULL)
372 interface->phyDriver->disableIrq(interface);
374 else if(interface->switchDriver != NULL)
377 interface->switchDriver->disableIrq(interface);
393 volatile uint32_t isr;
394 volatile uint32_t tsr;
395 volatile uint32_t rsr;
405 isr = EMAC->EMAC_ISR;
406 tsr = EMAC->EMAC_TSR;
407 rsr = EMAC->EMAC_RSR;
411 if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
412 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
415 EMAC->EMAC_TSR = tsr;
418 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
426 if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
429 nicDriverInterface->nicEvent =
TRUE;
450 rsr = EMAC->EMAC_RSR;
453 if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
456 EMAC->EMAC_RSR = rsr;
498 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) == 0)
527 EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
530 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
568 j = rxBufferIndex + i;
591 if((rxBufferDesc[j].status &
EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
605 if(eofIndex != UINT_MAX)
609 else if(sofIndex != UINT_MAX)
622 for(i = 0; i < j; i++)
625 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
685 uint32_t hashTable[2];
693 EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
694 EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
710 entry = &interface->macAddrFilter[i];
722 k = (
p[0] >> 6) ^
p[0];
723 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
724 k ^= (
p[2] >> 2) ^ (
p[2] << 4);
725 k ^= (
p[3] >> 6) ^
p[3];
726 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
727 k ^= (
p[5] >> 2) ^ (
p[5] << 4);
733 hashTable[k / 32] |= (1 << (k % 32));
741 unicastMacAddr[j++] = entry->
addr;
751 EMAC->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
752 EMAC->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
757 EMAC->EMAC_SA[1].EMAC_SAxB = 0;
764 EMAC->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
765 EMAC->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
770 EMAC->EMAC_SA[2].EMAC_SAxB = 0;
777 EMAC->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
778 EMAC->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
783 EMAC->EMAC_SA[3].EMAC_SAxB = 0;
787 EMAC->EMAC_HRB = hashTable[0];
788 EMAC->EMAC_HRT = hashTable[1];
791 TRACE_DEBUG(
" HRB = %08" PRIX32
"\r\n", EMAC->EMAC_HRB);
792 TRACE_DEBUG(
" HRT = %08" PRIX32
"\r\n", EMAC->EMAC_HRT);
810 config = EMAC->EMAC_NCFGR;
815 config |= EMAC_NCFGR_SPD;
819 config &= ~EMAC_NCFGR_SPD;
825 config |= EMAC_NCFGR_FD;
829 config &= ~EMAC_NCFGR_FD;
833 EMAC->EMAC_NCFGR = config;
857 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
859 temp |= EMAC_MAN_PHYA(phyAddr);
861 temp |= EMAC_MAN_REGA(
regAddr);
863 temp |= EMAC_MAN_DATA(
data);
866 EMAC->EMAC_MAN = temp;
868 while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
897 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
899 temp |= EMAC_MAN_PHYA(phyAddr);
901 temp |= EMAC_MAN_REGA(
regAddr);
904 EMAC->EMAC_MAN = temp;
906 while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
911 data = EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;