sam3x_eth_driver.c
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1 /**
2  * @file sam3x_eth_driver.c
3  * @brief SAM3X Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2025 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.5.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "sam3xa.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
50 //RX buffer
51 #pragma data_alignment = 8
53 //TX buffer descriptors
54 #pragma data_alignment = 4
55 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT];
56 //RX buffer descriptors
57 #pragma data_alignment = 4
58 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT];
59 
60 //Keil MDK-ARM or GCC compiler?
61 #else
62 
63 //TX buffer
65  __attribute__((aligned(8)));
66 //RX buffer
68  __attribute__((aligned(8)));
69 //TX buffer descriptors
71  __attribute__((aligned(4)));
72 //RX buffer descriptors
74  __attribute__((aligned(4)));
75 
76 #endif
77 
78 //TX buffer index
79 static uint_t txBufferIndex;
80 //RX buffer index
81 static uint_t rxBufferIndex;
82 
83 
84 /**
85  * @brief SAM3X Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  FALSE
106 };
107 
108 
109 /**
110  * @brief SAM3X Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118  volatile uint32_t status;
119 
120  //Debug message
121  TRACE_INFO("Initializing SAM3X Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Enable EMAC peripheral clock
127  PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
128 
129  //Disable transmit and receive circuits
130  EMAC->EMAC_NCR = 0;
131 
132  //GPIO configuration
133  sam3xEthInitGpio(interface);
134 
135  //Configure MDC clock speed
136  EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
137  //Enable management port (MDC and MDIO)
138  EMAC->EMAC_NCR |= EMAC_NCR_MPE;
139 
140  //Valid Ethernet PHY or switch driver?
141  if(interface->phyDriver != NULL)
142  {
143  //Ethernet PHY initialization
144  error = interface->phyDriver->init(interface);
145  }
146  else if(interface->switchDriver != NULL)
147  {
148  //Ethernet switch initialization
149  error = interface->switchDriver->init(interface);
150  }
151  else
152  {
153  //The interface is not properly configured
154  error = ERROR_FAILURE;
155  }
156 
157  //Any error to report?
158  if(error)
159  {
160  return error;
161  }
162 
163  //Set the MAC address of the station
164  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
165  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
166 
167  //The MAC supports 3 additional addresses for unicast perfect filtering
168  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
169  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
170  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
171 
172  //Initialize hash table
173  EMAC->EMAC_HRB = 0;
174  EMAC->EMAC_HRT = 0;
175 
176  //Configure the receive filter
177  EMAC->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
178 
179  //Initialize buffer descriptors
180  sam3xEthInitBufferDesc(interface);
181 
182  //Clear transmit status register
183  EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
184  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
185 
186  //Clear receive status register
187  EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
188 
189  //First disable all EMAC interrupts
190  EMAC->EMAC_IDR = 0xFFFFFFFF;
191 
192  //Only the desired ones are enabled
193  EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
194  EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
195 
196  //Read EMAC_ISR register to clear any pending interrupt
197  status = EMAC->EMAC_ISR;
198  (void) status;
199 
200  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
201  NVIC_SetPriorityGrouping(SAM3X_ETH_IRQ_PRIORITY_GROUPING);
202 
203  //Configure EMAC interrupt priority
204  NVIC_SetPriority(EMAC_IRQn, NVIC_EncodePriority(SAM3X_ETH_IRQ_PRIORITY_GROUPING,
206 
207  //Enable the EMAC to transmit and receive data
208  EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
209 
210  //Accept any packets from the upper layer
211  osSetEvent(&interface->nicTxEvent);
212 
213  //Successful initialization
214  return NO_ERROR;
215 }
216 
217 
218 /**
219  * @brief GPIO configuration
220  * @param[in] interface Underlying network interface
221  **/
222 
223 __weak_func void sam3xEthInitGpio(NetInterface *interface)
224 {
225 //SAM3X-EK evaluation board?
226 #if defined(USE_SAM3X_EK)
227  uint32_t mask;
228 
229  //Enable PIO peripheral clock
230  PMC->PMC_PCER0 = (1 << ID_PIOB);
231 
232  //Configure RMII pins
233  mask = PIO_PB9A_EMDIO | PIO_PB8A_EMDC | PIO_PB7A_ERXER | PIO_PB6A_ERX1 |
234  PIO_PB5A_ERX0 | PIO_PB4A_ERXDV | PIO_PB3A_ETX1 | PIO_PB2A_ETX0 |
235  PIO_PB1A_ETXEN | PIO_PB0A_ETXCK;
236 
237  //Disable pull-up resistors on RMII pins
238  PIOB->PIO_PUDR = mask;
239  //Disable interrupts-on-change
240  PIOB->PIO_IDR = mask;
241  //Assign RMII pins to peripheral A function
242  PIOB->PIO_ABSR &= ~mask;
243  //Disable the PIO from controlling the corresponding pins
244  PIOB->PIO_PDR = mask;
245 
246  //Select RMII operation mode and enable transceiver clock
247  EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
248 #endif
249 }
250 
251 
252 /**
253  * @brief Initialize buffer descriptors
254  * @param[in] interface Underlying network interface
255  **/
256 
258 {
259  uint_t i;
260  uint32_t address;
261 
262  //Initialize TX buffer descriptors
263  for(i = 0; i < SAM3X_ETH_TX_BUFFER_COUNT; i++)
264  {
265  //Calculate the address of the current TX buffer
266  address = (uint32_t) txBuffer[i];
267  //Write the address to the descriptor entry
268  txBufferDesc[i].address = address;
269  //Initialize status field
270  txBufferDesc[i].status = EMAC_TX_USED;
271  }
272 
273  //Mark the last descriptor entry with the wrap flag
274  txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
275  //Initialize TX buffer index
276  txBufferIndex = 0;
277 
278  //Initialize RX buffer descriptors
279  for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
280  {
281  //Calculate the address of the current RX buffer
282  address = (uint32_t) rxBuffer[i];
283  //Write the address to the descriptor entry
284  rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
285  //Clear status field
286  rxBufferDesc[i].status = 0;
287  }
288 
289  //Mark the last descriptor entry with the wrap flag
290  rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
291  //Initialize RX buffer index
292  rxBufferIndex = 0;
293 
294  //Start location of the TX descriptor list
295  EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
296  //Start location of the RX descriptor list
297  EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
298 }
299 
300 
301 /**
302  * @brief SAM3X Ethernet MAC timer handler
303  *
304  * This routine is periodically called by the TCP/IP stack to handle periodic
305  * operations such as polling the link state
306  *
307  * @param[in] interface Underlying network interface
308  **/
309 
310 void sam3xEthTick(NetInterface *interface)
311 {
312  //Valid Ethernet PHY or switch driver?
313  if(interface->phyDriver != NULL)
314  {
315  //Handle periodic operations
316  interface->phyDriver->tick(interface);
317  }
318  else if(interface->switchDriver != NULL)
319  {
320  //Handle periodic operations
321  interface->switchDriver->tick(interface);
322  }
323  else
324  {
325  //Just for sanity
326  }
327 }
328 
329 
330 /**
331  * @brief Enable interrupts
332  * @param[in] interface Underlying network interface
333  **/
334 
336 {
337  //Enable Ethernet MAC interrupts
338  NVIC_EnableIRQ(EMAC_IRQn);
339 
340  //Valid Ethernet PHY or switch driver?
341  if(interface->phyDriver != NULL)
342  {
343  //Enable Ethernet PHY interrupts
344  interface->phyDriver->enableIrq(interface);
345  }
346  else if(interface->switchDriver != NULL)
347  {
348  //Enable Ethernet switch interrupts
349  interface->switchDriver->enableIrq(interface);
350  }
351  else
352  {
353  //Just for sanity
354  }
355 }
356 
357 
358 /**
359  * @brief Disable interrupts
360  * @param[in] interface Underlying network interface
361  **/
362 
364 {
365  //Disable Ethernet MAC interrupts
366  NVIC_DisableIRQ(EMAC_IRQn);
367 
368  //Valid Ethernet PHY or switch driver?
369  if(interface->phyDriver != NULL)
370  {
371  //Disable Ethernet PHY interrupts
372  interface->phyDriver->disableIrq(interface);
373  }
374  else if(interface->switchDriver != NULL)
375  {
376  //Disable Ethernet switch interrupts
377  interface->switchDriver->disableIrq(interface);
378  }
379  else
380  {
381  //Just for sanity
382  }
383 }
384 
385 
386 /**
387  * @brief SAM3X Ethernet MAC interrupt service routine
388  **/
389 
390 void EMAC_Handler(void)
391 {
392  bool_t flag;
393  volatile uint32_t isr;
394  volatile uint32_t tsr;
395  volatile uint32_t rsr;
396 
397  //Interrupt service routine prologue
398  osEnterIsr();
399 
400  //This flag will be set if a higher priority task must be woken
401  flag = FALSE;
402 
403  //Each time the software reads EMAC_ISR, it has to check the contents
404  //of EMAC_TSR, EMAC_RSR and EMAC_NSR
405  isr = EMAC->EMAC_ISR;
406  tsr = EMAC->EMAC_TSR;
407  rsr = EMAC->EMAC_RSR;
408  (void) isr;
409 
410  //Packet transmitted?
411  if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
412  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
413  {
414  //Only clear TSR flags that are currently set
415  EMAC->EMAC_TSR = tsr;
416 
417  //Check whether the TX buffer is available for writing
418  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
419  {
420  //Notify the TCP/IP stack that the transmitter is ready to send
421  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
422  }
423  }
424 
425  //Packet received?
426  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
427  {
428  //Set event flag
429  nicDriverInterface->nicEvent = TRUE;
430  //Notify the TCP/IP stack of the event
431  flag |= osSetEventFromIsr(&netEvent);
432  }
433 
434  //Interrupt service routine epilogue
435  osExitIsr(flag);
436 }
437 
438 
439 /**
440  * @brief SAM3X Ethernet MAC event handler
441  * @param[in] interface Underlying network interface
442  **/
443 
445 {
446  error_t error;
447  uint32_t rsr;
448 
449  //Read receive status
450  rsr = EMAC->EMAC_RSR;
451 
452  //Packet received?
453  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
454  {
455  //Only clear RSR flags that are currently set
456  EMAC->EMAC_RSR = rsr;
457 
458  //Process all pending packets
459  do
460  {
461  //Read incoming packet
462  error = sam3xEthReceivePacket(interface);
463 
464  //No more data in the receive buffer?
465  } while(error != ERROR_BUFFER_EMPTY);
466  }
467 }
468 
469 
470 /**
471  * @brief Send a packet
472  * @param[in] interface Underlying network interface
473  * @param[in] buffer Multi-part buffer containing the data to send
474  * @param[in] offset Offset to the first data byte
475  * @param[in] ancillary Additional options passed to the stack along with
476  * the packet
477  * @return Error code
478  **/
479 
481  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
482 {
483  size_t length;
484 
485  //Retrieve the length of the packet
486  length = netBufferGetLength(buffer) - offset;
487 
488  //Check the frame length
490  {
491  //The transmitter can accept another packet
492  osSetEvent(&interface->nicTxEvent);
493  //Report an error
494  return ERROR_INVALID_LENGTH;
495  }
496 
497  //Make sure the current buffer is available for writing
498  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) == 0)
499  {
500  return ERROR_FAILURE;
501  }
502 
503  //Copy user data to the transmit buffer
504  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
505 
506  //Set the necessary flags in the descriptor entry
507  if(txBufferIndex < (SAM3X_ETH_TX_BUFFER_COUNT - 1))
508  {
509  //Write the status word
510  txBufferDesc[txBufferIndex].status = EMAC_TX_LAST |
512 
513  //Point to the next buffer
514  txBufferIndex++;
515  }
516  else
517  {
518  //Write the status word
519  txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP | EMAC_TX_LAST |
521 
522  //Wrap around
523  txBufferIndex = 0;
524  }
525 
526  //Set the TSTART bit to initiate transmission
527  EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
528 
529  //Check whether the next buffer is available for writing
530  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
531  {
532  //The transmitter can accept another packet
533  osSetEvent(&interface->nicTxEvent);
534  }
535 
536  //Successful processing
537  return NO_ERROR;
538 }
539 
540 
541 /**
542  * @brief Receive a packet
543  * @param[in] interface Underlying network interface
544  * @return Error code
545  **/
546 
548 {
549  static uint32_t temp[ETH_MAX_FRAME_SIZE / 4];
550  error_t error;
551  uint_t i;
552  uint_t j;
553  uint_t sofIndex;
554  uint_t eofIndex;
555  size_t n;
556  size_t size;
557  size_t length;
558 
559  //Initialize variables
560  size = 0;
561  sofIndex = UINT_MAX;
562  eofIndex = UINT_MAX;
563 
564  //Search for SOF and EOF flags
565  for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
566  {
567  //Point to the current entry
568  j = rxBufferIndex + i;
569 
570  //Wrap around to the beginning of the buffer if necessary
572  {
574  }
575 
576  //No more entries to process?
577  if((rxBufferDesc[j].address & EMAC_RX_OWNERSHIP) == 0)
578  {
579  //Stop processing
580  break;
581  }
582 
583  //A valid SOF has been found?
584  if((rxBufferDesc[j].status & EMAC_RX_SOF) != 0)
585  {
586  //Save the position of the SOF
587  sofIndex = i;
588  }
589 
590  //A valid EOF has been found?
591  if((rxBufferDesc[j].status & EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
592  {
593  //Save the position of the EOF
594  eofIndex = i;
595  //Retrieve the length of the frame
596  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
597  //Limit the number of data to read
598  size = MIN(size, ETH_MAX_FRAME_SIZE);
599  //Stop processing since we have reached the end of the frame
600  break;
601  }
602  }
603 
604  //Determine the number of entries to process
605  if(eofIndex != UINT_MAX)
606  {
607  j = eofIndex + 1;
608  }
609  else if(sofIndex != UINT_MAX)
610  {
611  j = sofIndex;
612  }
613  else
614  {
615  j = i;
616  }
617 
618  //Total number of bytes that have been copied from the receive buffer
619  length = 0;
620 
621  //Process incoming frame
622  for(i = 0; i < j; i++)
623  {
624  //Any data to copy from current buffer?
625  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
626  {
627  //Calculate the number of bytes to read at a time
628  n = MIN(size, SAM3X_ETH_RX_BUFFER_SIZE);
629  //Copy data from receive buffer
630  osMemcpy((uint8_t *) temp + length, rxBuffer[rxBufferIndex], n);
631  //Update byte counters
632  length += n;
633  size -= n;
634  }
635 
636  //Mark the current buffer as free
637  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
638 
639  //Point to the following entry
640  rxBufferIndex++;
641 
642  //Wrap around to the beginning of the buffer if necessary
643  if(rxBufferIndex >= SAM3X_ETH_RX_BUFFER_COUNT)
644  {
645  rxBufferIndex = 0;
646  }
647  }
648 
649  //Any packet to process?
650  if(length > 0)
651  {
652  NetRxAncillary ancillary;
653 
654  //Additional options can be passed to the stack along with the packet
655  ancillary = NET_DEFAULT_RX_ANCILLARY;
656 
657  //Pass the packet to the upper layer
658  nicProcessPacket(interface, (uint8_t *) temp, length, &ancillary);
659  //Valid packet received
660  error = NO_ERROR;
661  }
662  else
663  {
664  //No more data in the receive buffer
665  error = ERROR_BUFFER_EMPTY;
666  }
667 
668  //Return status code
669  return error;
670 }
671 
672 
673 /**
674  * @brief Configure MAC address filtering
675  * @param[in] interface Underlying network interface
676  * @return Error code
677  **/
678 
680 {
681  uint_t i;
682  uint_t j;
683  uint_t k;
684  uint8_t *p;
685  uint32_t hashTable[2];
686  MacAddr unicastMacAddr[3];
687  MacFilterEntry *entry;
688 
689  //Debug message
690  TRACE_DEBUG("Updating MAC filter...\r\n");
691 
692  //Set the MAC address of the station
693  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
694  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
695 
696  //The MAC supports 3 additional addresses for unicast perfect filtering
697  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
698  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
699  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
700 
701  //The hash table is used for multicast address filtering
702  hashTable[0] = 0;
703  hashTable[1] = 0;
704 
705  //The MAC address filter contains the list of MAC addresses to accept
706  //when receiving an Ethernet frame
707  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
708  {
709  //Point to the current entry
710  entry = &interface->macAddrFilter[i];
711 
712  //Valid entry?
713  if(entry->refCount > 0)
714  {
715  //Multicast address?
716  if(macIsMulticastAddr(&entry->addr))
717  {
718  //Point to the MAC address
719  p = entry->addr.b;
720 
721  //Apply the hash function
722  k = (p[0] >> 6) ^ p[0];
723  k ^= (p[1] >> 4) ^ (p[1] << 2);
724  k ^= (p[2] >> 2) ^ (p[2] << 4);
725  k ^= (p[3] >> 6) ^ p[3];
726  k ^= (p[4] >> 4) ^ (p[4] << 2);
727  k ^= (p[5] >> 2) ^ (p[5] << 4);
728 
729  //The hash value is reduced to a 6-bit index
730  k &= 0x3F;
731 
732  //Update hash table contents
733  hashTable[k / 32] |= (1 << (k % 32));
734  }
735  else
736  {
737  //Up to 3 additional MAC addresses can be specified
738  if(j < 3)
739  {
740  //Save the unicast address
741  unicastMacAddr[j++] = entry->addr;
742  }
743  }
744  }
745  }
746 
747  //Configure the first unicast address filter
748  if(j >= 1)
749  {
750  //The address is activated when SAT register is written
751  EMAC->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
752  EMAC->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
753  }
754  else
755  {
756  //The address is deactivated when SAB register is written
757  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
758  }
759 
760  //Configure the second unicast address filter
761  if(j >= 2)
762  {
763  //The address is activated when SAT register is written
764  EMAC->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
765  EMAC->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
766  }
767  else
768  {
769  //The address is deactivated when SAB register is written
770  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
771  }
772 
773  //Configure the third unicast address filter
774  if(j >= 3)
775  {
776  //The address is activated when SAT register is written
777  EMAC->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
778  EMAC->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
779  }
780  else
781  {
782  //The address is deactivated when SAB register is written
783  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
784  }
785 
786  //Configure the multicast hash table
787  EMAC->EMAC_HRB = hashTable[0];
788  EMAC->EMAC_HRT = hashTable[1];
789 
790  //Debug message
791  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
792  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
793 
794  //Successful processing
795  return NO_ERROR;
796 }
797 
798 
799 /**
800  * @brief Adjust MAC configuration parameters for proper operation
801  * @param[in] interface Underlying network interface
802  * @return Error code
803  **/
804 
806 {
807  uint32_t config;
808 
809  //Read network configuration register
810  config = EMAC->EMAC_NCFGR;
811 
812  //10BASE-T or 100BASE-TX operation mode?
813  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
814  {
815  config |= EMAC_NCFGR_SPD;
816  }
817  else
818  {
819  config &= ~EMAC_NCFGR_SPD;
820  }
821 
822  //Half-duplex or full-duplex mode?
823  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
824  {
825  config |= EMAC_NCFGR_FD;
826  }
827  else
828  {
829  config &= ~EMAC_NCFGR_FD;
830  }
831 
832  //Write configuration value back to NCFGR register
833  EMAC->EMAC_NCFGR = config;
834 
835  //Successful processing
836  return NO_ERROR;
837 }
838 
839 
840 /**
841  * @brief Write PHY register
842  * @param[in] opcode Access type (2 bits)
843  * @param[in] phyAddr PHY address (5 bits)
844  * @param[in] regAddr Register address (5 bits)
845  * @param[in] data Register value
846  **/
847 
848 void sam3xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
849  uint8_t regAddr, uint16_t data)
850 {
851  uint32_t temp;
852 
853  //Valid opcode?
854  if(opcode == SMI_OPCODE_WRITE)
855  {
856  //Set up a write operation
857  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
858  //PHY address
859  temp |= EMAC_MAN_PHYA(phyAddr);
860  //Register address
861  temp |= EMAC_MAN_REGA(regAddr);
862  //Register value
863  temp |= EMAC_MAN_DATA(data);
864 
865  //Start a write operation
866  EMAC->EMAC_MAN = temp;
867  //Wait for the write to complete
868  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
869  {
870  }
871  }
872  else
873  {
874  //The MAC peripheral only supports standard Clause 22 opcodes
875  }
876 }
877 
878 
879 /**
880  * @brief Read PHY register
881  * @param[in] opcode Access type (2 bits)
882  * @param[in] phyAddr PHY address (5 bits)
883  * @param[in] regAddr Register address (5 bits)
884  * @return Register value
885  **/
886 
887 uint16_t sam3xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
888  uint8_t regAddr)
889 {
890  uint16_t data;
891  uint32_t temp;
892 
893  //Valid opcode?
894  if(opcode == SMI_OPCODE_READ)
895  {
896  //Set up a read operation
897  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
898  //PHY address
899  temp |= EMAC_MAN_PHYA(phyAddr);
900  //Register address
901  temp |= EMAC_MAN_REGA(regAddr);
902 
903  //Start a read operation
904  EMAC->EMAC_MAN = temp;
905  //Wait for the read to complete
906  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
907  {
908  }
909 
910  //Get register value
911  data = EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
912  }
913  else
914  {
915  //The MAC peripheral only supports standard Clause 22 opcodes
916  data = 0;
917  }
918 
919  //Return the value of the PHY register
920  return data;
921 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
error_t sam3xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint8_t opcode
Definition: dns_common.h:188
int bool_t
Definition: compiler_port.h:61
Transmit buffer descriptor.
#define netEvent
Definition: net_legacy.h:196
void sam3xEthEventHandler(NetInterface *interface)
SAM3X Ethernet MAC event handler.
const NicDriver sam3xEthDriver
SAM3X Ethernet MAC driver.
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
#define SAM3X_ETH_TX_BUFFER_COUNT
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:690
error_t sam3xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint8_t p
Definition: ndp.h:300
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
void sam3xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
#define EMAC_RX_WRAP
Receive buffer descriptor.
#define TRUE
Definition: os_port.h:50
uint8_t data[]
Definition: ethernet.h:222
__weak_func void sam3xEthInitGpio(NetInterface *interface)
GPIO configuration.
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
void sam3xEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define EMAC_RX_EOF
#define EMAC_RX_OWNERSHIP
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:392
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define osExitIsr(flag)
void sam3xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define SMI_OPCODE_WRITE
Definition: nic.h:66
#define EMAC_RX_LENGTH
error_t sam3xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define FALSE
Definition: os_port.h:46
#define osMemcpy(dest, src, length)
Definition: os_port.h:144
#define EMAC_TX_LENGTH
error_t
Error codes.
Definition: error.h:43
#define SAM3X_ETH_IRQ_PRIORITY_GROUPING
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:105
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
SAM3X Ethernet MAC driver.
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:263
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_BUFFER_EMPTY
Definition: error.h:142
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t mask
Definition: web_socket.h:319
#define SMI_OPCODE_READ
Definition: nic.h:67
#define TRACE_INFO(...)
Definition: debug.h:105
uint8_t length
Definition: tcp.h:375
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:63
#define rxBuffer
#define SAM3X_ETH_RX_BUFFER_SIZE
MacAddr
Definition: ethernet.h:195
#define TRACE_DEBUG(...)
Definition: debug.h:119
void sam3xEthTick(NetInterface *interface)
SAM3X Ethernet MAC timer handler.
uint16_t regAddr
error_t sam3xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define EMAC_TX_USED
#define ETH_MTU
Definition: ethernet.h:116
uint8_t n
MAC filter table entry.
Definition: ethernet.h:262
Ipv6Addr address[]
Definition: ipv6.h:325
#define osEnterIsr()
#define SAM3X_ETH_IRQ_SUB_PRIORITY
void EMAC_Handler(void)
SAM3X Ethernet MAC interrupt service routine.
#define EMAC_RX_ADDRESS
#define EMAC_TX_WRAP
#define EMAC_RX_SOF
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void sam3xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
unsigned int uint_t
Definition: compiler_port.h:57
error_t sam3xEthInit(NetInterface *interface)
SAM3X Ethernet MAC initialization.
TCP/IP stack core.
NIC driver.
Definition: nic.h:286
#define SAM3X_ETH_TX_BUFFER_SIZE
uint16_t sam3xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define SAM3X_ETH_IRQ_GROUP_PRIORITY
#define SAM3X_ETH_RX_BUFFER_COUNT
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define EMAC_TX_LAST
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83