sam3x_eth_driver.c
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1 /**
2  * @file sam3x_eth_driver.c
3  * @brief SAM3X Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "sam3xa.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
48 //RX buffer
49 #pragma data_alignment = 8
51 //TX buffer descriptors
52 #pragma data_alignment = 4
53 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT];
54 //RX buffer descriptors
55 #pragma data_alignment = 4
56 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT];
57 
58 //Keil MDK-ARM or GCC compiler?
59 #else
60 
61 //TX buffer
63  __attribute__((aligned(8)));
64 //RX buffer
66  __attribute__((aligned(8)));
67 //TX buffer descriptors
69  __attribute__((aligned(4)));
70 //RX buffer descriptors
72  __attribute__((aligned(4)));
73 
74 #endif
75 
76 //TX buffer index
77 static uint_t txBufferIndex;
78 //RX buffer index
79 static uint_t rxBufferIndex;
80 
81 
82 /**
83  * @brief SAM3X Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  FALSE
104 };
105 
106 
107 /**
108  * @brief SAM3X Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116  volatile uint32_t status;
117 
118  //Debug message
119  TRACE_INFO("Initializing SAM3X Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable EMAC peripheral clock
125  PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
126 
127  //GPIO configuration
128  sam3xEthInitGpio(interface);
129 
130  //Configure MDC clock speed
131  EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
132  //Enable management port (MDC and MDIO)
133  EMAC->EMAC_NCR |= EMAC_NCR_MPE;
134 
135  //PHY transceiver initialization
136  error = interface->phyDriver->init(interface);
137  //Failed to initialize PHY transceiver?
138  if(error)
139  return error;
140 
141  //Set the MAC address
142  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
143  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
144 
145  //Configure the receive filter
146  EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI | EMAC_NCFGR_MTI;
147 
148  //Initialize hash table
149  EMAC->EMAC_HRB = 0;
150  EMAC->EMAC_HRT = 0;
151 
152  //Initialize buffer descriptors
153  sam3xEthInitBufferDesc(interface);
154 
155  //Clear transmit status register
156  EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
157  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
158  //Clear receive status register
159  EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
160 
161  //First disable all EMAC interrupts
162  EMAC->EMAC_IDR = 0xFFFFFFFF;
163  //Only the desired ones are enabled
164  EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
165  EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
166 
167  //Read EMAC ISR register to clear any pending interrupt
168  status = EMAC->EMAC_ISR;
169 
170  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
171  NVIC_SetPriorityGrouping(SAM3X_ETH_IRQ_PRIORITY_GROUPING);
172 
173  //Configure EMAC interrupt priority
174  NVIC_SetPriority(EMAC_IRQn, NVIC_EncodePriority(SAM3X_ETH_IRQ_PRIORITY_GROUPING,
176 
177  //Enable the EMAC to transmit and receive data
178  EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
179 
180  //Accept any packets from the upper layer
181  osSetEvent(&interface->nicTxEvent);
182 
183  //Successful initialization
184  return NO_ERROR;
185 }
186 
187 
188 //SAM3X-EK evaluation board?
189 #if defined(USE_SAM3X_EK)
190 
191 /**
192  * @brief GPIO configuration
193  * @param[in] interface Underlying network interface
194  **/
195 
196 void sam3xEthInitGpio(NetInterface *interface)
197 {
198  //Enable PIO peripheral clock
199  PMC->PMC_PCER0 = (1 << ID_PIOB);
200 
201  //Disable pull-up resistors on RMII pins
202  PIOB->PIO_PUDR = EMAC_RMII_MASK;
203  //Disable interrupts-on-change
204  PIOB->PIO_IDR = EMAC_RMII_MASK;
205  //Assign RMII pins to peripheral A function
206  PIOB->PIO_ABSR &= ~EMAC_RMII_MASK;
207  //Disable the PIO from controlling the corresponding pins
208  PIOB->PIO_PDR = EMAC_RMII_MASK;
209 
210  //Select RMII operation mode and enable transceiver clock
211  EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
212 }
213 
214 #endif
215 
216 
217 /**
218  * @brief Initialize buffer descriptors
219  * @param[in] interface Underlying network interface
220  **/
221 
223 {
224  uint_t i;
225  uint32_t address;
226 
227  //Initialize TX buffer descriptors
228  for(i = 0; i < SAM3X_ETH_TX_BUFFER_COUNT; i++)
229  {
230  //Calculate the address of the current TX buffer
231  address = (uint32_t) txBuffer[i];
232  //Write the address to the descriptor entry
233  txBufferDesc[i].address = address;
234  //Initialize status field
235  txBufferDesc[i].status = EMAC_TX_USED;
236  }
237 
238  //Mark the last descriptor entry with the wrap flag
239  txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
240  //Initialize TX buffer index
241  txBufferIndex = 0;
242 
243  //Initialize RX buffer descriptors
244  for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
245  {
246  //Calculate the address of the current RX buffer
247  address = (uint32_t) rxBuffer[i];
248  //Write the address to the descriptor entry
249  rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
250  //Clear status field
251  rxBufferDesc[i].status = 0;
252  }
253 
254  //Mark the last descriptor entry with the wrap flag
255  rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
256  //Initialize RX buffer index
257  rxBufferIndex = 0;
258 
259  //Start location of the TX descriptor list
260  EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
261  //Start location of the RX descriptor list
262  EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
263 }
264 
265 
266 /**
267  * @brief SAM3X Ethernet MAC timer handler
268  *
269  * This routine is periodically called by the TCP/IP stack to
270  * handle periodic operations such as polling the link state
271  *
272  * @param[in] interface Underlying network interface
273  **/
274 
275 void sam3xEthTick(NetInterface *interface)
276 {
277  //Handle periodic operations
278  interface->phyDriver->tick(interface);
279 }
280 
281 
282 /**
283  * @brief Enable interrupts
284  * @param[in] interface Underlying network interface
285  **/
286 
288 {
289  //Enable Ethernet MAC interrupts
290  NVIC_EnableIRQ(EMAC_IRQn);
291  //Enable Ethernet PHY interrupts
292  interface->phyDriver->enableIrq(interface);
293 }
294 
295 
296 /**
297  * @brief Disable interrupts
298  * @param[in] interface Underlying network interface
299  **/
300 
302 {
303  //Disable Ethernet MAC interrupts
304  NVIC_DisableIRQ(EMAC_IRQn);
305  //Disable Ethernet PHY interrupts
306  interface->phyDriver->disableIrq(interface);
307 }
308 
309 
310 /**
311  * @brief SAM3X Ethernet MAC interrupt service routine
312  **/
313 
314 void EMAC_Handler(void)
315 {
316  bool_t flag;
317  volatile uint32_t isr;
318  volatile uint32_t tsr;
319  volatile uint32_t rsr;
320 
321  //Enter interrupt service routine
322  osEnterIsr();
323 
324  //This flag will be set if a higher priority task must be woken
325  flag = FALSE;
326 
327  //Each time the software reads EMAC_ISR, it has to check the
328  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
329  isr = EMAC->EMAC_ISR;
330  tsr = EMAC->EMAC_TSR;
331  rsr = EMAC->EMAC_RSR;
332 
333  //A packet has been transmitted?
334  if(tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
335  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR))
336  {
337  //Only clear TSR flags that are currently set
338  EMAC->EMAC_TSR = tsr;
339 
340  //Check whether the TX buffer is available for writing
341  if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
342  {
343  //Notify the TCP/IP stack that the transmitter is ready to send
344  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
345  }
346  }
347 
348  //A packet has been received?
349  if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
350  {
351  //Set event flag
352  nicDriverInterface->nicEvent = TRUE;
353  //Notify the TCP/IP stack of the event
354  flag |= osSetEventFromIsr(&netEvent);
355  }
356 
357  //Leave interrupt service routine
358  osExitIsr(flag);
359 }
360 
361 
362 /**
363  * @brief SAM3X Ethernet MAC event handler
364  * @param[in] interface Underlying network interface
365  **/
366 
368 {
369  error_t error;
370  uint32_t rsr;
371 
372  //Read receive status
373  rsr = EMAC->EMAC_RSR;
374 
375  //Packet received?
376  if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
377  {
378  //Only clear RSR flags that are currently set
379  EMAC->EMAC_RSR = rsr;
380 
381  //Process all pending packets
382  do
383  {
384  //Read incoming packet
385  error = sam3xEthReceivePacket(interface);
386 
387  //No more data in the receive buffer?
388  } while(error != ERROR_BUFFER_EMPTY);
389  }
390 }
391 
392 
393 /**
394  * @brief Send a packet
395  * @param[in] interface Underlying network interface
396  * @param[in] buffer Multi-part buffer containing the data to send
397  * @param[in] offset Offset to the first data byte
398  * @return Error code
399  **/
400 
402  const NetBuffer *buffer, size_t offset)
403 {
404  size_t length;
405 
406  //Retrieve the length of the packet
407  length = netBufferGetLength(buffer) - offset;
408 
409  //Check the frame length
411  {
412  //The transmitter can accept another packet
413  osSetEvent(&interface->nicTxEvent);
414  //Report an error
415  return ERROR_INVALID_LENGTH;
416  }
417 
418  //Make sure the current buffer is available for writing
419  if(!(txBufferDesc[txBufferIndex].status & EMAC_TX_USED))
420  return ERROR_FAILURE;
421 
422  //Copy user data to the transmit buffer
423  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
424 
425  //Set the necessary flags in the descriptor entry
426  if(txBufferIndex < (SAM3X_ETH_TX_BUFFER_COUNT - 1))
427  {
428  //Write the status word
429  txBufferDesc[txBufferIndex].status =
431 
432  //Point to the next buffer
433  txBufferIndex++;
434  }
435  else
436  {
437  //Write the status word
438  txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP |
440 
441  //Wrap around
442  txBufferIndex = 0;
443  }
444 
445  //Set the TSTART bit to initiate transmission
446  EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
447 
448  //Check whether the next buffer is available for writing
449  if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
450  {
451  //The transmitter can accept another packet
452  osSetEvent(&interface->nicTxEvent);
453  }
454 
455  //Successful processing
456  return NO_ERROR;
457 }
458 
459 
460 /**
461  * @brief Receive a packet
462  * @param[in] interface Underlying network interface
463  * @return Error code
464  **/
465 
467 {
468  static uint8_t temp[ETH_MAX_FRAME_SIZE];
469  error_t error;
470  uint_t i;
471  uint_t j;
472  uint_t sofIndex;
473  uint_t eofIndex;
474  size_t n;
475  size_t size;
476  size_t length;
477 
478  //Initialize SOF and EOF indices
479  sofIndex = UINT_MAX;
480  eofIndex = UINT_MAX;
481 
482  //Search for SOF and EOF flags
483  for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
484  {
485  //Point to the current entry
486  j = rxBufferIndex + i;
487 
488  //Wrap around to the beginning of the buffer if necessary
491 
492  //No more entries to process?
493  if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
494  {
495  //Stop processing
496  break;
497  }
498  //A valid SOF has been found?
499  if(rxBufferDesc[j].status & EMAC_RX_SOF)
500  {
501  //Save the position of the SOF
502  sofIndex = i;
503  }
504  //A valid EOF has been found?
505  if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
506  {
507  //Save the position of the EOF
508  eofIndex = i;
509  //Retrieve the length of the frame
510  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
511  //Limit the number of data to read
512  size = MIN(size, ETH_MAX_FRAME_SIZE);
513  //Stop processing since we have reached the end of the frame
514  break;
515  }
516  }
517 
518  //Determine the number of entries to process
519  if(eofIndex != UINT_MAX)
520  j = eofIndex + 1;
521  else if(sofIndex != UINT_MAX)
522  j = sofIndex;
523  else
524  j = i;
525 
526  //Total number of bytes that have been copied from the receive buffer
527  length = 0;
528 
529  //Process incoming frame
530  for(i = 0; i < j; i++)
531  {
532  //Any data to copy from current buffer?
533  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
534  {
535  //Calculate the number of bytes to read at a time
536  n = MIN(size, SAM3X_ETH_RX_BUFFER_SIZE);
537  //Copy data from receive buffer
538  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
539  //Update byte counters
540  length += n;
541  size -= n;
542  }
543 
544  //Mark the current buffer as free
545  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
546 
547  //Point to the following entry
548  rxBufferIndex++;
549 
550  //Wrap around to the beginning of the buffer if necessary
551  if(rxBufferIndex >= SAM3X_ETH_RX_BUFFER_COUNT)
552  rxBufferIndex = 0;
553  }
554 
555  //Any packet to process?
556  if(length > 0)
557  {
558  //Pass the packet to the upper layer
559  nicProcessPacket(interface, temp, length);
560  //Valid packet received
561  error = NO_ERROR;
562  }
563  else
564  {
565  //No more data in the receive buffer
566  error = ERROR_BUFFER_EMPTY;
567  }
568 
569  //Return status code
570  return error;
571 }
572 
573 
574 /**
575  * @brief Configure MAC address filtering
576  * @param[in] interface Underlying network interface
577  * @return Error code
578  **/
579 
581 {
582  uint_t i;
583  uint_t k;
584  uint8_t *p;
585  uint32_t hashTable[2];
586  MacFilterEntry *entry;
587 
588  //Debug message
589  TRACE_DEBUG("Updating SAM3X hash table...\r\n");
590 
591  //Clear hash table
592  hashTable[0] = 0;
593  hashTable[1] = 0;
594 
595  //The MAC address filter contains the list of MAC addresses to accept
596  //when receiving an Ethernet frame
597  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
598  {
599  //Point to the current entry
600  entry = &interface->macAddrFilter[i];
601 
602  //Valid entry?
603  if(entry->refCount > 0)
604  {
605  //Point to the MAC address
606  p = entry->addr.b;
607 
608  //Apply the hash function
609  k = (p[0] >> 6) ^ p[0];
610  k ^= (p[1] >> 4) ^ (p[1] << 2);
611  k ^= (p[2] >> 2) ^ (p[2] << 4);
612  k ^= (p[3] >> 6) ^ p[3];
613  k ^= (p[4] >> 4) ^ (p[4] << 2);
614  k ^= (p[5] >> 2) ^ (p[5] << 4);
615 
616  //The hash value is reduced to a 6-bit index
617  k &= 0x3F;
618 
619  //Update hash table contents
620  hashTable[k / 32] |= (1 << (k % 32));
621  }
622  }
623 
624  //Write the hash table
625  EMAC->EMAC_HRB = hashTable[0];
626  EMAC->EMAC_HRT = hashTable[1];
627 
628  //Debug message
629  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
630  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
631 
632  //Successful processing
633  return NO_ERROR;
634 }
635 
636 
637 /**
638  * @brief Adjust MAC configuration parameters for proper operation
639  * @param[in] interface Underlying network interface
640  * @return Error code
641  **/
642 
644 {
645  uint32_t config;
646 
647  //Read network configuration register
648  config = EMAC->EMAC_NCFGR;
649 
650  //10BASE-T or 100BASE-TX operation mode?
651  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
652  config |= EMAC_NCFGR_SPD;
653  else
654  config &= ~EMAC_NCFGR_SPD;
655 
656  //Half-duplex or full-duplex mode?
657  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
658  config |= EMAC_NCFGR_FD;
659  else
660  config &= ~EMAC_NCFGR_FD;
661 
662  //Write configuration value back to NCFGR register
663  EMAC->EMAC_NCFGR = config;
664 
665  //Successful processing
666  return NO_ERROR;
667 }
668 
669 
670 /**
671  * @brief Write PHY register
672  * @param[in] phyAddr PHY address
673  * @param[in] regAddr Register address
674  * @param[in] data Register value
675  **/
676 
677 void sam3xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
678 {
679  uint32_t value;
680 
681  //Set up a write operation
682  value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
683  //PHY address
684  value |= EMAC_MAN_PHYA(phyAddr);
685  //Register address
686  value |= EMAC_MAN_REGA(regAddr);
687  //Register value
688  value |= EMAC_MAN_DATA(data);
689 
690  //Start a write operation
691  EMAC->EMAC_MAN = value;
692  //Wait for the write to complete
693  while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
694 }
695 
696 
697 /**
698  * @brief Read PHY register
699  * @param[in] phyAddr PHY address
700  * @param[in] regAddr Register address
701  * @return Register value
702  **/
703 
704 uint16_t sam3xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
705 {
706  uint32_t value;
707 
708  //Set up a read operation
709  value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
710  //PHY address
711  value |= EMAC_MAN_PHYA(phyAddr);
712  //Register address
713  value |= EMAC_MAN_REGA(regAddr);
714 
715  //Start a read operation
716  EMAC->EMAC_MAN = value;
717  //Wait for the read to complete
718  while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
719 
720  //Return PHY register contents
721  return EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
722 }
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
#define EMAC_RX_ADDRESS
TCP/IP stack core.
SAM3X Ethernet MAC controller.
Debugging facilities.
void EMAC_Handler(void)
SAM3X Ethernet MAC interrupt service routine.
#define SAM3X_ETH_IRQ_PRIORITY_GROUPING
uint8_t p
Definition: ndp.h:295
#define EMAC_TX_WRAP
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define EMAC_RX_SOF
error_t sam3xEthInit(NetInterface *interface)
SAM3X Ethernet MAC initialization.
Generic error code.
Definition: error.h:43
#define txBuffer
void sam3xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define SAM3X_ETH_RX_BUFFER_SIZE
#define SAM3X_ETH_TX_BUFFER_SIZE
#define SAM3X_ETH_IRQ_GROUP_PRIORITY
#define EMAC_TX_USED
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
error_t sam3xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define SAM3X_ETH_TX_BUFFER_COUNT
#define EMAC_RX_EOF
#define SAM3X_ETH_IRQ_SUB_PRIORITY
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
void sam3xEthEnableIrq(NetInterface *interface)
Enable interrupts.
NIC driver.
Definition: nic.h:161
void sam3xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define EMAC_RX_LENGTH
Transmit buffer descriptor.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void sam3xEthInitGpio(NetInterface *interface)
void sam3xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define SAM3X_ETH_RX_BUFFER_COUNT
error_t sam3xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define EMAC_TX_LAST
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
Receive buffer descriptor.
#define rxBuffer
error_t sam3xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
const NicDriver sam3xEthDriver
SAM3X Ethernet MAC driver.
uint16_t sam3xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define EMAC_TX_LENGTH
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void sam3xEthEventHandler(NetInterface *interface)
SAM3X Ethernet MAC event handler.
#define osExitIsr(flag)
#define EMAC_RX_OWNERSHIP
#define EMAC_RMII_MASK
#define EMAC_RX_WRAP
#define osEnterIsr()
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
void sam3xEthTick(NetInterface *interface)
SAM3X Ethernet MAC timer handler.
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
error_t sam3xEthReceivePacket(NetInterface *interface)
Receive a packet.
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98