sam9263_eth_driver.c
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1 /**
2  * @file sam9263_eth_driver.c
3  * @brief AT91SAM9263 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "at91sam9263.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
50 //RX buffer
51 #pragma data_alignment = 8
53 //TX buffer descriptors
54 #pragma data_alignment = 4
56 //RX buffer descriptors
57 #pragma data_alignment = 4
59 
60 //Keil MDK-ARM or GCC compiler?
61 #else
62 
63 //TX buffer
65  __attribute__((aligned(8)));
66 //RX buffer
68  __attribute__((aligned(8)));
69 //TX buffer descriptors
71  __attribute__((aligned(4)));
72 //RX buffer descriptors
74  __attribute__((aligned(4)));
75 
76 #endif
77 
78 //TX buffer index
79 static uint_t txBufferIndex;
80 //RX buffer index
81 static uint_t rxBufferIndex;
82 
83 
84 /**
85  * @brief SAM9263 Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  FALSE
106 };
107 
108 
109 /**
110  * @brief SAM9263 Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118  volatile uint32_t status;
119 
120  //Debug message
121  TRACE_INFO("Initializing SAM9263 Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Enable EMAC peripheral clock
127  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_EMAC);
128 
129  //Disable transmit and receive circuits
130  AT91C_BASE_EMAC->EMAC_NCR = 0;
131 
132  //GPIO configuration
133  sam9263EthInitGpio(interface);
134 
135  //Configure MDC clock speed
136  AT91C_BASE_EMAC->EMAC_NCFGR = AT91C_EMAC_CLK_HCLK_64;
137  //Enable management port (MDC and MDIO)
138  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
139 
140  //PHY transceiver initialization
141  error = interface->phyDriver->init(interface);
142  //Failed to initialize PHY transceiver?
143  if(error)
144  return error;
145 
146  //Set the MAC address of the station
147  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
148  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
149 
150  //The MAC supports 3 additional addresses for unicast perfect filtering
151  AT91C_BASE_EMAC->EMAC_SA2L = 0;
152  AT91C_BASE_EMAC->EMAC_SA3L = 0;
153  AT91C_BASE_EMAC->EMAC_SA4L = 0;
154 
155  //Initialize hash table
156  AT91C_BASE_EMAC->EMAC_HRB = 0;
157  AT91C_BASE_EMAC->EMAC_HRT = 0;
158 
159  //Configure the receive filter
160  AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_BIG | AT91C_EMAC_MTI;
161 
162  //Initialize buffer descriptors
163  sam9263EthInitBufferDesc(interface);
164 
165  //Clear transmit status register
166  AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
167  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR;
168  //Clear receive status register
169  AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA;
170 
171  //First disable all EMAC interrupts
172  AT91C_BASE_EMAC->EMAC_IDR = 0xFFFFFFFF;
173  //Only the desired ones are enabled
174  AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_ROVR | AT91C_EMAC_TCOMP | AT91C_EMAC_TXERR |
175  AT91C_EMAC_RLEX | AT91C_EMAC_TUNDR | AT91C_EMAC_RXUBR | AT91C_EMAC_RCOMP;
176 
177  //Read EMAC ISR register to clear any pending interrupt
178  status = AT91C_BASE_EMAC->EMAC_ISR;
179 
180  //Configure interrupt controller
181  AT91C_BASE_AIC->AIC_SMR[AT91C_ID_EMAC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
182  AT91C_BASE_AIC->AIC_SVR[AT91C_ID_EMAC] = (uint32_t) emacIrqWrapper;
183 
184  //Clear EMAC interrupt flag
185  AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_EMAC);
186 
187  //Enable the EMAC to transmit and receive data
188  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE;
189 
190  //Accept any packets from the upper layer
191  osSetEvent(&interface->nicTxEvent);
192 
193  //Successful initialization
194  return NO_ERROR;
195 }
196 
197 
198 //SAM9263-EK evaluation board?
199 #if defined(USE_SAM9263_EK)
200 
201 /**
202  * @brief GPIO configuration
203  * @param[in] interface Underlying network interface
204  **/
205 
206 void sam9263EthInitGpio(NetInterface *interface)
207 {
208  //Enable PIO peripheral clocks
209  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOCDE);
210 
211  //Disable pull-up resistors on RMII pins
212  AT91C_BASE_PIOC->PIO_PPUDR = AT91C_EMAC_RMII_MASK_C;
213  AT91C_BASE_PIOE->PIO_PPUDR = AT91C_EMAC_RMII_MASK_E;
214  //Disable interrupts-on-change
215  AT91C_BASE_PIOC->PIO_IDR = AT91C_EMAC_RMII_MASK_C;
216  AT91C_BASE_PIOE->PIO_IDR = AT91C_EMAC_RMII_MASK_E;
217  //Assign RMII pins to to the relevant peripheral function
218  AT91C_BASE_PIOC->PIO_BSR = AT91C_EMAC_RMII_MASK_C;
219  AT91C_BASE_PIOE->PIO_ASR = AT91C_EMAC_RMII_MASK_E;
220  //Disable the PIO from controlling the corresponding pins
221  AT91C_BASE_PIOC->PIO_PDR = AT91C_EMAC_RMII_MASK_C;
222  AT91C_BASE_PIOE->PIO_PDR = AT91C_EMAC_RMII_MASK_E;
223 
224  //Select RMII operation mode and enable transceiver clock
225  AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII;
226 }
227 
228 #endif
229 
230 
231 /**
232  * @brief Initialize buffer descriptors
233  * @param[in] interface Underlying network interface
234  **/
235 
237 {
238  uint_t i;
239  uint32_t address;
240 
241  //Initialize TX buffer descriptors
242  for(i = 0; i < SAM9263_ETH_TX_BUFFER_COUNT; i++)
243  {
244  //Calculate the address of the current TX buffer
245  address = (uint32_t) txBuffer[i];
246  //Write the address to the descriptor entry
247  txBufferDesc[i].address = address;
248  //Initialize status field
249  txBufferDesc[i].status = AT91C_EMAC_TX_USED;
250  }
251 
252  //Mark the last descriptor entry with the wrap flag
253  txBufferDesc[i - 1].status |= AT91C_EMAC_TX_WRAP;
254  //Initialize TX buffer index
255  txBufferIndex = 0;
256 
257  //Initialize RX buffer descriptors
258  for(i = 0; i < SAM9263_ETH_RX_BUFFER_COUNT; i++)
259  {
260  //Calculate the address of the current RX buffer
261  address = (uint32_t) rxBuffer[i];
262  //Write the address to the descriptor entry
263  rxBufferDesc[i].address = address & AT91C_EMAC_RX_ADDRESS;
264  //Clear status field
265  rxBufferDesc[i].status = 0;
266  }
267 
268  //Mark the last descriptor entry with the wrap flag
269  rxBufferDesc[i - 1].address |= AT91C_EMAC_RX_WRAP;
270  //Initialize RX buffer index
271  rxBufferIndex = 0;
272 
273  //Start location of the TX descriptor list
274  AT91C_BASE_EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
275  //Start location of the RX descriptor list
276  AT91C_BASE_EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
277 }
278 
279 
280 /**
281  * @brief SAM9263 Ethernet MAC timer handler
282  *
283  * This routine is periodically called by the TCP/IP stack to
284  * handle periodic operations such as polling the link state
285  *
286  * @param[in] interface Underlying network interface
287  **/
288 
289 void sam9263EthTick(NetInterface *interface)
290 {
291  //Handle periodic operations
292  interface->phyDriver->tick(interface);
293 }
294 
295 
296 /**
297  * @brief Enable interrupts
298  * @param[in] interface Underlying network interface
299  **/
300 
302 {
303  //Enable Ethernet MAC interrupts
304  AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_EMAC);
305  //Enable Ethernet PHY interrupts
306  interface->phyDriver->enableIrq(interface);
307 }
308 
309 
310 /**
311  * @brief Disable interrupts
312  * @param[in] interface Underlying network interface
313  **/
314 
316 {
317  //Disable Ethernet MAC interrupts
318  AT91C_BASE_AIC->AIC_IDCR = (1 << AT91C_ID_EMAC);
319  //Disable Ethernet PHY interrupts
320  interface->phyDriver->disableIrq(interface);
321 }
322 
323 
324 /**
325  * @brief SAM9263 Ethernet MAC interrupt service routine
326  **/
327 
329 {
330  bool_t flag;
331  volatile uint32_t isr;
332  volatile uint32_t tsr;
333  volatile uint32_t rsr;
334 
335  //Interrupt service routine prologue
336  osEnterIsr();
337 
338  //This flag will be set if a higher priority task must be woken
339  flag = FALSE;
340 
341  //Each time the software reads EMAC_ISR, it has to check the
342  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
343  isr = AT91C_BASE_EMAC->EMAC_ISR;
344  tsr = AT91C_BASE_EMAC->EMAC_TSR;
345  rsr = AT91C_BASE_EMAC->EMAC_RSR;
346 
347  //A packet has been transmitted?
348  if(tsr & (AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
349  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR))
350  {
351  //Only clear TSR flags that are currently set
352  AT91C_BASE_EMAC->EMAC_TSR = tsr;
353 
354  //Check whether the TX buffer is available for writing
355  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
356  {
357  //Notify the TCP/IP stack that the transmitter is ready to send
358  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
359  }
360  }
361 
362  //A packet has been received?
363  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
364  {
365  //Set event flag
366  nicDriverInterface->nicEvent = TRUE;
367  //Notify the TCP/IP stack of the event
368  flag |= osSetEventFromIsr(&netEvent);
369  }
370 
371  //Write AIC_EOICR register before exiting
372  AT91C_BASE_AIC->AIC_EOICR = 0;
373 
374  //Interrupt service routine epilogue
375  osExitIsr(flag);
376 }
377 
378 
379 /**
380  * @brief SAM9263 Ethernet MAC event handler
381  * @param[in] interface Underlying network interface
382  **/
383 
385 {
386  error_t error;
387  uint32_t rsr;
388 
389  //Read receive status
390  rsr = AT91C_BASE_EMAC->EMAC_RSR;
391 
392  //Packet received?
393  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
394  {
395  //Only clear RSR flags that are currently set
396  AT91C_BASE_EMAC->EMAC_RSR = rsr;
397 
398  //Process all pending packets
399  do
400  {
401  //Read incoming packet
402  error = sam9263EthReceivePacket(interface);
403 
404  //No more data in the receive buffer?
405  } while(error != ERROR_BUFFER_EMPTY);
406  }
407 }
408 
409 
410 /**
411  * @brief Send a packet
412  * @param[in] interface Underlying network interface
413  * @param[in] buffer Multi-part buffer containing the data to send
414  * @param[in] offset Offset to the first data byte
415  * @return Error code
416  **/
417 
419  const NetBuffer *buffer, size_t offset)
420 {
421  size_t length;
422 
423  //Retrieve the length of the packet
424  length = netBufferGetLength(buffer) - offset;
425 
426  //Check the frame length
428  {
429  //The transmitter can accept another packet
430  osSetEvent(&interface->nicTxEvent);
431  //Report an error
432  return ERROR_INVALID_LENGTH;
433  }
434 
435  //Make sure the current buffer is available for writing
436  if(!(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED))
437  return ERROR_FAILURE;
438 
439  //Copy user data to the transmit buffer
440  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
441 
442  //Set the necessary flags in the descriptor entry
443  if(txBufferIndex < (SAM9263_ETH_TX_BUFFER_COUNT - 1))
444  {
445  //Write the status word
446  txBufferDesc[txBufferIndex].status =
448 
449  //Point to the next buffer
450  txBufferIndex++;
451  }
452  else
453  {
454  //Write the status word
455  txBufferDesc[txBufferIndex].status = AT91C_EMAC_TX_WRAP |
457 
458  //Wrap around
459  txBufferIndex = 0;
460  }
461 
462  //Set the TSTART bit to initiate transmission
463  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
464 
465  //Check whether the next buffer is available for writing
466  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
467  {
468  //The transmitter can accept another packet
469  osSetEvent(&interface->nicTxEvent);
470  }
471 
472  //Successful processing
473  return NO_ERROR;
474 }
475 
476 
477 /**
478  * @brief Receive a packet
479  * @param[in] interface Underlying network interface
480  * @return Error code
481  **/
482 
484 {
485  static uint8_t temp[ETH_MAX_FRAME_SIZE];
486  error_t error;
487  uint_t i;
488  uint_t j;
489  uint_t sofIndex;
490  uint_t eofIndex;
491  size_t n;
492  size_t size;
493  size_t length;
494 
495  //Initialize SOF and EOF indices
496  sofIndex = UINT_MAX;
497  eofIndex = UINT_MAX;
498 
499  //Search for SOF and EOF flags
500  for(i = 0; i < SAM9263_ETH_RX_BUFFER_COUNT; i++)
501  {
502  //Point to the current entry
503  j = rxBufferIndex + i;
504 
505  //Wrap around to the beginning of the buffer if necessary
508 
509  //No more entries to process?
510  if(!(rxBufferDesc[j].address & AT91C_EMAC_RX_OWNERSHIP))
511  {
512  //Stop processing
513  break;
514  }
515  //A valid SOF has been found?
516  if(rxBufferDesc[j].status & AT91C_EMAC_RX_SOF)
517  {
518  //Save the position of the SOF
519  sofIndex = i;
520  }
521  //A valid EOF has been found?
522  if((rxBufferDesc[j].status & AT91C_EMAC_RX_EOF) && sofIndex != UINT_MAX)
523  {
524  //Save the position of the EOF
525  eofIndex = i;
526  //Retrieve the length of the frame
527  size = rxBufferDesc[j].status & AT91C_EMAC_RX_LENGTH;
528  //Limit the number of data to read
529  size = MIN(size, ETH_MAX_FRAME_SIZE);
530  //Stop processing since we have reached the end of the frame
531  break;
532  }
533  }
534 
535  //Determine the number of entries to process
536  if(eofIndex != UINT_MAX)
537  j = eofIndex + 1;
538  else if(sofIndex != UINT_MAX)
539  j = sofIndex;
540  else
541  j = i;
542 
543  //Total number of bytes that have been copied from the receive buffer
544  length = 0;
545 
546  //Process incoming frame
547  for(i = 0; i < j; i++)
548  {
549  //Any data to copy from current buffer?
550  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
551  {
552  //Calculate the number of bytes to read at a time
554  //Copy data from receive buffer
555  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
556  //Update byte counters
557  length += n;
558  size -= n;
559  }
560 
561  //Mark the current buffer as free
562  rxBufferDesc[rxBufferIndex].address &= ~AT91C_EMAC_RX_OWNERSHIP;
563 
564  //Point to the following entry
565  rxBufferIndex++;
566 
567  //Wrap around to the beginning of the buffer if necessary
568  if(rxBufferIndex >= SAM9263_ETH_RX_BUFFER_COUNT)
569  rxBufferIndex = 0;
570  }
571 
572  //Any packet to process?
573  if(length > 0)
574  {
575  //Pass the packet to the upper layer
576  nicProcessPacket(interface, temp, length);
577  //Valid packet received
578  error = NO_ERROR;
579  }
580  else
581  {
582  //No more data in the receive buffer
583  error = ERROR_BUFFER_EMPTY;
584  }
585 
586  //Return status code
587  return error;
588 }
589 
590 
591 /**
592  * @brief Configure MAC address filtering
593  * @param[in] interface Underlying network interface
594  * @return Error code
595  **/
596 
598 {
599  uint_t i;
600  uint_t j;
601  uint_t k;
602  uint8_t *p;
603  uint32_t hashTable[2];
604  MacAddr unicastMacAddr[3];
605  MacFilterEntry *entry;
606 
607  //Debug message
608  TRACE_DEBUG("Updating MAC filter...\r\n");
609 
610  //Set the MAC address of the station
611  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
612  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
613 
614  //The MAC supports 3 additional addresses for unicast perfect filtering
615  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
616  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
617  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
618 
619  //The hash table is used for multicast address filtering
620  hashTable[0] = 0;
621  hashTable[1] = 0;
622 
623  //The MAC address filter contains the list of MAC addresses to accept
624  //when receiving an Ethernet frame
625  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
626  {
627  //Point to the current entry
628  entry = &interface->macAddrFilter[i];
629 
630  //Valid entry?
631  if(entry->refCount > 0)
632  {
633  //Multicast address?
634  if(macIsMulticastAddr(&entry->addr))
635  {
636  //Point to the MAC address
637  p = entry->addr.b;
638 
639  //Apply the hash function
640  k = (p[0] >> 6) ^ p[0];
641  k ^= (p[1] >> 4) ^ (p[1] << 2);
642  k ^= (p[2] >> 2) ^ (p[2] << 4);
643  k ^= (p[3] >> 6) ^ p[3];
644  k ^= (p[4] >> 4) ^ (p[4] << 2);
645  k ^= (p[5] >> 2) ^ (p[5] << 4);
646 
647  //The hash value is reduced to a 6-bit index
648  k &= 0x3F;
649 
650  //Update hash table contents
651  hashTable[k / 32] |= (1 << (k % 32));
652  }
653  else
654  {
655  //Up to 3 additional MAC addresses can be specified
656  if(j < 3)
657  {
658  //Save the unicast address
659  unicastMacAddr[j++] = entry->addr;
660  }
661  }
662  }
663  }
664 
665  //Configure the first unicast address filter
666  if(j >= 1)
667  {
668  //The address is activated when SAH register is written
669  AT91C_BASE_EMAC->EMAC_SA2L = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
670  AT91C_BASE_EMAC->EMAC_SA2H = unicastMacAddr[0].w[2];
671  }
672  else
673  {
674  //The address is deactivated when SAL register is written
675  AT91C_BASE_EMAC->EMAC_SA2L = 0;
676  }
677 
678  //Configure the second unicast address filter
679  if(j >= 2)
680  {
681  //The address is activated when SAH register is written
682  AT91C_BASE_EMAC->EMAC_SA3L = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
683  AT91C_BASE_EMAC->EMAC_SA3H = unicastMacAddr[1].w[2];
684  }
685  else
686  {
687  //The address is deactivated when SAL register is written
688  AT91C_BASE_EMAC->EMAC_SA3L = 0;
689  }
690 
691  //Configure the third unicast address filter
692  if(j >= 3)
693  {
694  //The address is activated when SAH register is written
695  AT91C_BASE_EMAC->EMAC_SA4L = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
696  AT91C_BASE_EMAC->EMAC_SA4H = unicastMacAddr[2].w[2];
697  }
698  else
699  {
700  //The address is deactivated when SAL register is written
701  AT91C_BASE_EMAC->EMAC_SA4L = 0;
702  }
703 
704  //Configure the multicast address filter
705  AT91C_BASE_EMAC->EMAC_HRB = hashTable[0];
706  AT91C_BASE_EMAC->EMAC_HRT = hashTable[1];
707 
708  //Debug message
709  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRB);
710  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRT);
711 
712  //Successful processing
713  return NO_ERROR;
714 }
715 
716 
717 /**
718  * @brief Adjust MAC configuration parameters for proper operation
719  * @param[in] interface Underlying network interface
720  * @return Error code
721  **/
722 
724 {
725  uint32_t config;
726 
727  //Read network configuration register
728  config = AT91C_BASE_EMAC->EMAC_NCFGR;
729 
730  //10BASE-T or 100BASE-TX operation mode?
731  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
732  config |= AT91C_EMAC_SPD;
733  else
734  config &= ~AT91C_EMAC_SPD;
735 
736  //Half-duplex or full-duplex mode?
737  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
738  config |= AT91C_EMAC_FD;
739  else
740  config &= ~AT91C_EMAC_FD;
741 
742  //Write configuration value back to NCFGR register
743  AT91C_BASE_EMAC->EMAC_NCFGR = config;
744 
745  //Successful processing
746  return NO_ERROR;
747 }
748 
749 
750 /**
751  * @brief Write PHY register
752  * @param[in] opcode Access type (2 bits)
753  * @param[in] phyAddr PHY address (5 bits)
754  * @param[in] regAddr Register address (5 bits)
755  * @param[in] data Register value
756  **/
757 
758 void sam9263EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
759  uint8_t regAddr, uint16_t data)
760 {
761  uint32_t temp;
762 
763  //Valid opcode?
764  if(opcode == SMI_OPCODE_WRITE)
765  {
766  //Set up a write operation
768  //PHY address
769  temp |= (phyAddr << 23) & AT91C_EMAC_PHYA;
770  //Register address
771  temp |= (regAddr << 18) & AT91C_EMAC_REGA;
772  //Register value
773  temp |= data & AT91C_EMAC_DATA;
774 
775  //Start a write operation
776  AT91C_BASE_EMAC->EMAC_MAN = temp;
777  //Wait for the write to complete
778  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
779  {
780  }
781  }
782  else
783  {
784  //The MAC peripheral only supports standard Clause 22 opcodes
785  }
786 }
787 
788 
789 /**
790  * @brief Read PHY register
791  * @param[in] opcode Access type (2 bits)
792  * @param[in] phyAddr PHY address (5 bits)
793  * @param[in] regAddr Register address (5 bits)
794  * @return Register value
795  **/
796 
797 uint16_t sam9263EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
798  uint8_t regAddr)
799 {
800  uint16_t data;
801  uint32_t temp;
802 
803  //Valid opcode?
804  if(opcode == SMI_OPCODE_READ)
805  {
806  //Set up a read operation
808  //PHY address
809  temp |= (phyAddr << 23) & AT91C_EMAC_PHYA;
810  //Register address
811  temp |= (regAddr << 18) & AT91C_EMAC_REGA;
812 
813  //Start a read operation
814  AT91C_BASE_EMAC->EMAC_MAN = temp;
815  //Wait for the read to complete
816  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
817  {
818  }
819 
820  //Get register value
821  data = AT91C_BASE_EMAC->EMAC_MAN & AT91C_EMAC_DATA;
822  }
823  else
824  {
825  //The MAC peripheral only supports standard Clause 22 opcodes
826  data = 0;
827  }
828 
829  //Return the value of the PHY register
830  return data;
831 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
const NicDriver sam9263EthDriver
SAM9263 Ethernet MAC driver.
uint8_t length
Definition: dtls_misc.h:149
void sam9263EthIrqHandler(void)
SAM9263 Ethernet MAC interrupt service routine.
#define AT91C_EMAC_CODE_10
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
void sam9263EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void sam9263EthInitGpio(NetInterface *interface)
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
error_t sam9263EthInit(NetInterface *interface)
SAM9263 Ethernet MAC initialization.
#define AT91C_EMAC_RX_OWNERSHIP
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define AT91C_EMAC_RW_10
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define AT91C_EMAC_RX_WRAP
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
#define AT91C_EMAC_RX_EOF
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
void emacIrqWrapper(void)
#define SAM9263_ETH_TX_BUFFER_SIZE
error_t sam9263EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define osExitIsr(flag)
error_t sam9263EthReceivePacket(NetInterface *interface)
Receive a packet.
#define SMI_OPCODE_WRITE
Definition: nic.h:62
void sam9263EthEventHandler(NetInterface *interface)
SAM9263 Ethernet MAC event handler.
#define SAM9263_ETH_RX_BUFFER_SIZE
#define AT91C_EMAC_RW_01
#define FALSE
Definition: os_port.h:46
void sam9263EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define AT91C_EMAC_RX_LENGTH
void sam9263EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t
Error codes.
Definition: error.h:42
uint16_t sam9263EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Generic error code.
Definition: error.h:45
#define AT91C_EMAC_RMII_MASK_C
#define txBuffer
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:222
AT91SAM9263 Ethernet MAC controller.
Transmit buffer descriptor.
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define AT91C_EMAC_TX_LENGTH
#define SAM9263_ETH_RX_BUFFER_COUNT
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void sam9263EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define SAM9263_ETH_TX_BUFFER_COUNT
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
#define AT91C_EMAC_SOF_01
Receive buffer descriptor.
#define AT91C_EMAC_RX_SOF
#define TRACE_DEBUG(...)
Definition: debug.h:106
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
void sam9263EthTick(NetInterface *interface)
SAM9263 Ethernet MAC timer handler.
#define osEnterIsr()
error_t sam9263EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define AT91C_EMAC_TX_LAST
#define AT91C_EMAC_RX_ADDRESS
#define AT91C_EMAC_TX_USED
Ipv6Addr address
error_t sam9263EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
unsigned int uint_t
Definition: compiler_port.h:45
#define AT91C_BASE_EMAC
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
#define AT91C_EMAC_RMII_MASK_E
#define AT91C_EMAC_TX_WRAP
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
__start_packed struct @108 MacAddr
MAC address.
Ethernet interface.
Definition: nic.h:79