sam9263_eth_driver.c
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1 /**
2  * @file sam9263_eth_driver.c
3  * @brief AT91SAM9263 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "at91sam9263.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
48 //RX buffer
49 #pragma data_alignment = 8
51 //TX buffer descriptors
52 #pragma data_alignment = 4
54 //RX buffer descriptors
55 #pragma data_alignment = 4
57 
58 //Keil MDK-ARM or GCC compiler?
59 #else
60 
61 //TX buffer
63  __attribute__((aligned(8)));
64 //RX buffer
66  __attribute__((aligned(8)));
67 //TX buffer descriptors
69  __attribute__((aligned(4)));
70 //RX buffer descriptors
72  __attribute__((aligned(4)));
73 
74 #endif
75 
76 //TX buffer index
77 static uint_t txBufferIndex;
78 //RX buffer index
79 static uint_t rxBufferIndex;
80 
81 
82 /**
83  * @brief SAM9263 Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  FALSE
104 };
105 
106 
107 /**
108  * @brief SAM9263 Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116  volatile uint32_t status;
117 
118  //Debug message
119  TRACE_INFO("Initializing SAM9263 Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable EMAC peripheral clock
125  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_EMAC);
126 
127  //GPIO configuration
128  sam9263EthInitGpio(interface);
129 
130  //Configure MDC clock speed
131  AT91C_BASE_EMAC->EMAC_NCFGR = AT91C_EMAC_CLK_HCLK_64;
132  //Enable management port (MDC and MDIO)
133  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
134 
135  //PHY transceiver initialization
136  error = interface->phyDriver->init(interface);
137  //Failed to initialize PHY transceiver?
138  if(error)
139  return error;
140 
141  //Set the MAC address
142  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
143  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
144 
145  //Configure the receive filter
146  AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_UNI | AT91C_EMAC_MTI;
147 
148  //Initialize hash table
149  AT91C_BASE_EMAC->EMAC_HRB = 0;
150  AT91C_BASE_EMAC->EMAC_HRT = 0;
151 
152  //Initialize buffer descriptors
153  sam9263EthInitBufferDesc(interface);
154 
155  //Clear transmit status register
156  AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
157  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR;
158  //Clear receive status register
159  AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA;
160 
161  //First disable all EMAC interrupts
162  AT91C_BASE_EMAC->EMAC_IDR = 0xFFFFFFFF;
163  //Only the desired ones are enabled
164  AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_ROVR | AT91C_EMAC_TCOMP | AT91C_EMAC_TXERR |
165  AT91C_EMAC_RLEX | AT91C_EMAC_TUNDR | AT91C_EMAC_RXUBR | AT91C_EMAC_RCOMP;
166 
167  //Read EMAC ISR register to clear any pending interrupt
168  status = AT91C_BASE_EMAC->EMAC_ISR;
169 
170  //Configure interrupt controller
171  AT91C_BASE_AIC->AIC_SMR[AT91C_ID_EMAC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
172  AT91C_BASE_AIC->AIC_SVR[AT91C_ID_EMAC] = (uint32_t) emacIrqWrapper;
173 
174  //Clear EMAC interrupt flag
175  AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_EMAC);
176 
177  //Enable the EMAC to transmit and receive data
178  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE;
179 
180  //Accept any packets from the upper layer
181  osSetEvent(&interface->nicTxEvent);
182 
183  //Successful initialization
184  return NO_ERROR;
185 }
186 
187 
188 //SAM9263-EK evaluation board?
189 #if defined(USE_SAM9263_EK)
190 
191 /**
192  * @brief GPIO configuration
193  * @param[in] interface Underlying network interface
194  **/
195 
196 void sam9263EthInitGpio(NetInterface *interface)
197 {
198  //Enable PIO peripheral clocks
199  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOCDE);
200 
201  //Disable pull-up resistors on RMII pins
202  AT91C_BASE_PIOC->PIO_PPUDR = AT91C_EMAC_RMII_MASK_C;
203  AT91C_BASE_PIOE->PIO_PPUDR = AT91C_EMAC_RMII_MASK_E;
204  //Disable interrupts-on-change
205  AT91C_BASE_PIOC->PIO_IDR = AT91C_EMAC_RMII_MASK_C;
206  AT91C_BASE_PIOE->PIO_IDR = AT91C_EMAC_RMII_MASK_E;
207  //Assign RMII pins to to the relevant peripheral function
208  AT91C_BASE_PIOC->PIO_BSR = AT91C_EMAC_RMII_MASK_C;
209  AT91C_BASE_PIOE->PIO_ASR = AT91C_EMAC_RMII_MASK_E;
210  //Disable the PIO from controlling the corresponding pins
211  AT91C_BASE_PIOC->PIO_PDR = AT91C_EMAC_RMII_MASK_C;
212  AT91C_BASE_PIOE->PIO_PDR = AT91C_EMAC_RMII_MASK_E;
213 
214  //Select RMII operation mode and enable transceiver clock
215  AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII;
216 }
217 
218 #endif
219 
220 
221 /**
222  * @brief Initialize buffer descriptors
223  * @param[in] interface Underlying network interface
224  **/
225 
227 {
228  uint_t i;
229  uint32_t address;
230 
231  //Initialize TX buffer descriptors
232  for(i = 0; i < SAM9263_ETH_TX_BUFFER_COUNT; i++)
233  {
234  //Calculate the address of the current TX buffer
235  address = (uint32_t) txBuffer[i];
236  //Write the address to the descriptor entry
237  txBufferDesc[i].address = address;
238  //Initialize status field
239  txBufferDesc[i].status = AT91C_EMAC_TX_USED;
240  }
241 
242  //Mark the last descriptor entry with the wrap flag
243  txBufferDesc[i - 1].status |= AT91C_EMAC_TX_WRAP;
244  //Initialize TX buffer index
245  txBufferIndex = 0;
246 
247  //Initialize RX buffer descriptors
248  for(i = 0; i < SAM9263_ETH_RX_BUFFER_COUNT; i++)
249  {
250  //Calculate the address of the current RX buffer
251  address = (uint32_t) rxBuffer[i];
252  //Write the address to the descriptor entry
253  rxBufferDesc[i].address = address & AT91C_EMAC_RX_ADDRESS;
254  //Clear status field
255  rxBufferDesc[i].status = 0;
256  }
257 
258  //Mark the last descriptor entry with the wrap flag
259  rxBufferDesc[i - 1].address |= AT91C_EMAC_RX_WRAP;
260  //Initialize RX buffer index
261  rxBufferIndex = 0;
262 
263  //Start location of the TX descriptor list
264  AT91C_BASE_EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
265  //Start location of the RX descriptor list
266  AT91C_BASE_EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
267 }
268 
269 
270 /**
271  * @brief SAM9263 Ethernet MAC timer handler
272  *
273  * This routine is periodically called by the TCP/IP stack to
274  * handle periodic operations such as polling the link state
275  *
276  * @param[in] interface Underlying network interface
277  **/
278 
279 void sam9263EthTick(NetInterface *interface)
280 {
281  //Handle periodic operations
282  interface->phyDriver->tick(interface);
283 }
284 
285 
286 /**
287  * @brief Enable interrupts
288  * @param[in] interface Underlying network interface
289  **/
290 
292 {
293  //Enable Ethernet MAC interrupts
294  AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_EMAC);
295  //Enable Ethernet PHY interrupts
296  interface->phyDriver->enableIrq(interface);
297 }
298 
299 
300 /**
301  * @brief Disable interrupts
302  * @param[in] interface Underlying network interface
303  **/
304 
306 {
307  //Disable Ethernet MAC interrupts
308  AT91C_BASE_AIC->AIC_IDCR = (1 << AT91C_ID_EMAC);
309  //Disable Ethernet PHY interrupts
310  interface->phyDriver->disableIrq(interface);
311 }
312 
313 
314 /**
315  * @brief SAM9263 Ethernet MAC interrupt service routine
316  **/
317 
319 {
320  bool_t flag;
321  volatile uint32_t isr;
322  volatile uint32_t tsr;
323  volatile uint32_t rsr;
324 
325  //Enter interrupt service routine
326  osEnterIsr();
327 
328  //This flag will be set if a higher priority task must be woken
329  flag = FALSE;
330 
331  //Each time the software reads EMAC_ISR, it has to check the
332  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
333  isr = AT91C_BASE_EMAC->EMAC_ISR;
334  tsr = AT91C_BASE_EMAC->EMAC_TSR;
335  rsr = AT91C_BASE_EMAC->EMAC_RSR;
336 
337  //A packet has been transmitted?
338  if(tsr & (AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
339  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR))
340  {
341  //Only clear TSR flags that are currently set
342  AT91C_BASE_EMAC->EMAC_TSR = tsr;
343 
344  //Check whether the TX buffer is available for writing
345  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
346  {
347  //Notify the TCP/IP stack that the transmitter is ready to send
348  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
349  }
350  }
351 
352  //A packet has been received?
353  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
354  {
355  //Set event flag
356  nicDriverInterface->nicEvent = TRUE;
357  //Notify the TCP/IP stack of the event
358  flag |= osSetEventFromIsr(&netEvent);
359  }
360 
361  //Write AIC_EOICR register before exiting
362  AT91C_BASE_AIC->AIC_EOICR = 0;
363 
364  //Leave interrupt service routine
365  osExitIsr(flag);
366 }
367 
368 
369 /**
370  * @brief SAM9263 Ethernet MAC event handler
371  * @param[in] interface Underlying network interface
372  **/
373 
375 {
376  error_t error;
377  uint32_t rsr;
378 
379  //Read receive status
380  rsr = AT91C_BASE_EMAC->EMAC_RSR;
381 
382  //Packet received?
383  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
384  {
385  //Only clear RSR flags that are currently set
386  AT91C_BASE_EMAC->EMAC_RSR = rsr;
387 
388  //Process all pending packets
389  do
390  {
391  //Read incoming packet
392  error = sam9263EthReceivePacket(interface);
393 
394  //No more data in the receive buffer?
395  } while(error != ERROR_BUFFER_EMPTY);
396  }
397 }
398 
399 
400 /**
401  * @brief Send a packet
402  * @param[in] interface Underlying network interface
403  * @param[in] buffer Multi-part buffer containing the data to send
404  * @param[in] offset Offset to the first data byte
405  * @return Error code
406  **/
407 
409  const NetBuffer *buffer, size_t offset)
410 {
411  size_t length;
412 
413  //Retrieve the length of the packet
414  length = netBufferGetLength(buffer) - offset;
415 
416  //Check the frame length
418  {
419  //The transmitter can accept another packet
420  osSetEvent(&interface->nicTxEvent);
421  //Report an error
422  return ERROR_INVALID_LENGTH;
423  }
424 
425  //Make sure the current buffer is available for writing
426  if(!(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED))
427  return ERROR_FAILURE;
428 
429  //Copy user data to the transmit buffer
430  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
431 
432  //Set the necessary flags in the descriptor entry
433  if(txBufferIndex < (SAM9263_ETH_TX_BUFFER_COUNT - 1))
434  {
435  //Write the status word
436  txBufferDesc[txBufferIndex].status =
438 
439  //Point to the next buffer
440  txBufferIndex++;
441  }
442  else
443  {
444  //Write the status word
445  txBufferDesc[txBufferIndex].status = AT91C_EMAC_TX_WRAP |
447 
448  //Wrap around
449  txBufferIndex = 0;
450  }
451 
452  //Set the TSTART bit to initiate transmission
453  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
454 
455  //Check whether the next buffer is available for writing
456  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
457  {
458  //The transmitter can accept another packet
459  osSetEvent(&interface->nicTxEvent);
460  }
461 
462  //Successful processing
463  return NO_ERROR;
464 }
465 
466 
467 /**
468  * @brief Receive a packet
469  * @param[in] interface Underlying network interface
470  * @return Error code
471  **/
472 
474 {
475  static uint8_t temp[ETH_MAX_FRAME_SIZE];
476  error_t error;
477  uint_t i;
478  uint_t j;
479  uint_t sofIndex;
480  uint_t eofIndex;
481  size_t n;
482  size_t size;
483  size_t length;
484 
485  //Initialize SOF and EOF indices
486  sofIndex = UINT_MAX;
487  eofIndex = UINT_MAX;
488 
489  //Search for SOF and EOF flags
490  for(i = 0; i < SAM9263_ETH_RX_BUFFER_COUNT; i++)
491  {
492  //Point to the current entry
493  j = rxBufferIndex + i;
494 
495  //Wrap around to the beginning of the buffer if necessary
498 
499  //No more entries to process?
500  if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
501  {
502  //Stop processing
503  break;
504  }
505  //A valid SOF has been found?
506  if(rxBufferDesc[j].status & EMAC_RX_SOF)
507  {
508  //Save the position of the SOF
509  sofIndex = i;
510  }
511  //A valid EOF has been found?
512  if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
513  {
514  //Save the position of the EOF
515  eofIndex = i;
516  //Retrieve the length of the frame
517  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
518  //Limit the number of data to read
519  size = MIN(size, ETH_MAX_FRAME_SIZE);
520  //Stop processing since we have reached the end of the frame
521  break;
522  }
523  }
524 
525  //Determine the number of entries to process
526  if(eofIndex != UINT_MAX)
527  j = eofIndex + 1;
528  else if(sofIndex != UINT_MAX)
529  j = sofIndex;
530  else
531  j = i;
532 
533  //Total number of bytes that have been copied from the receive buffer
534  length = 0;
535 
536  //Process incoming frame
537  for(i = 0; i < j; i++)
538  {
539  //Any data to copy from current buffer?
540  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
541  {
542  //Calculate the number of bytes to read at a time
544  //Copy data from receive buffer
545  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
546  //Update byte counters
547  length += n;
548  size -= n;
549  }
550 
551  //Mark the current buffer as free
552  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
553 
554  //Point to the following entry
555  rxBufferIndex++;
556 
557  //Wrap around to the beginning of the buffer if necessary
558  if(rxBufferIndex >= SAM9263_ETH_RX_BUFFER_COUNT)
559  rxBufferIndex = 0;
560  }
561 
562  //Any packet to process?
563  if(length > 0)
564  {
565  //Pass the packet to the upper layer
566  nicProcessPacket(interface, temp, length);
567  //Valid packet received
568  error = NO_ERROR;
569  }
570  else
571  {
572  //No more data in the receive buffer
573  error = ERROR_BUFFER_EMPTY;
574  }
575 
576  //Return status code
577  return error;
578 }
579 
580 
581 /**
582  * @brief Configure MAC address filtering
583  * @param[in] interface Underlying network interface
584  * @return Error code
585  **/
586 
588 {
589  uint_t i;
590  uint_t k;
591  uint8_t *p;
592  uint32_t hashTable[2];
593  MacFilterEntry *entry;
594 
595  //Debug message
596  TRACE_DEBUG("Updating SAM9263 hash table...\r\n");
597 
598  //Clear hash table
599  hashTable[0] = 0;
600  hashTable[1] = 0;
601 
602  //The MAC address filter contains the list of MAC addresses to accept
603  //when receiving an Ethernet frame
604  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
605  {
606  //Point to the current entry
607  entry = &interface->macAddrFilter[i];
608 
609  //Valid entry?
610  if(entry->refCount > 0)
611  {
612  //Point to the MAC address
613  p = entry->addr.b;
614 
615  //Apply the hash function
616  k = (p[0] >> 6) ^ p[0];
617  k ^= (p[1] >> 4) ^ (p[1] << 2);
618  k ^= (p[2] >> 2) ^ (p[2] << 4);
619  k ^= (p[3] >> 6) ^ p[3];
620  k ^= (p[4] >> 4) ^ (p[4] << 2);
621  k ^= (p[5] >> 2) ^ (p[5] << 4);
622 
623  //The hash value is reduced to a 6-bit index
624  k &= 0x3F;
625 
626  //Update hash table contents
627  hashTable[k / 32] |= (1 << (k % 32));
628  }
629  }
630 
631  //Write the hash table
632  AT91C_BASE_EMAC->EMAC_HRB = hashTable[0];
633  AT91C_BASE_EMAC->EMAC_HRT = hashTable[1];
634 
635  //Debug message
636  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRB);
637  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRT);
638 
639  //Successful processing
640  return NO_ERROR;
641 }
642 
643 
644 /**
645  * @brief Adjust MAC configuration parameters for proper operation
646  * @param[in] interface Underlying network interface
647  * @return Error code
648  **/
649 
651 {
652  uint32_t config;
653 
654  //Read network configuration register
655  config = AT91C_BASE_EMAC->EMAC_NCFGR;
656 
657  //10BASE-T or 100BASE-TX operation mode?
658  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
659  config |= AT91C_EMAC_SPD;
660  else
661  config &= ~AT91C_EMAC_SPD;
662 
663  //Half-duplex or full-duplex mode?
664  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
665  config |= AT91C_EMAC_FD;
666  else
667  config &= ~AT91C_EMAC_FD;
668 
669  //Write configuration value back to NCFGR register
670  AT91C_BASE_EMAC->EMAC_NCFGR = config;
671 
672  //Successful processing
673  return NO_ERROR;
674 }
675 
676 
677 /**
678  * @brief Write PHY register
679  * @param[in] phyAddr PHY address
680  * @param[in] regAddr Register address
681  * @param[in] data Register value
682  **/
683 
684 void sam9263EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
685 {
686  uint32_t value;
687 
688  //Set up a write operation
690  //PHY address
691  value |= (phyAddr << 23) & AT91C_EMAC_PHYA;
692  //Register address
693  value |= (regAddr << 18) & AT91C_EMAC_REGA;
694  //Register value
695  value |= data & AT91C_EMAC_DATA;
696 
697  //Start a write operation
698  AT91C_BASE_EMAC->EMAC_MAN = value;
699  //Wait for the write to complete
700  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
701 }
702 
703 
704 /**
705  * @brief Read PHY register
706  * @param[in] phyAddr PHY address
707  * @param[in] regAddr Register address
708  * @return Register value
709  **/
710 
711 uint16_t sam9263EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
712 {
713  uint32_t value;
714 
715  //Set up a read operation
717  //PHY address
718  value |= (phyAddr << 23) & AT91C_EMAC_PHYA;
719  //Register address
720  value |= (regAddr << 18) & AT91C_EMAC_REGA;
721 
722  //Start a read operation
723  AT91C_BASE_EMAC->EMAC_MAN = value;
724  //Wait for the read to complete
725  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
726 
727  //Return PHY register contents
728  return AT91C_BASE_EMAC->EMAC_MAN & AT91C_EMAC_DATA;
729 }
error_t sam9263EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void sam9263EthDisableIrq(NetInterface *interface)
Disable interrupts.
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
uint16_t sam9263EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sam9263EthReceivePacket(NetInterface *interface)
Receive a packet.
TCP/IP stack core.
Debugging facilities.
#define SAM9263_ETH_RX_BUFFER_COUNT
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define AT91C_EMAC_TX_USED
#define EMAC_RX_SOF
Generic error code.
Definition: error.h:43
#define txBuffer
#define AT91C_BASE_EMAC
#define AT91C_EMAC_RMII_MASK_E
void sam9263EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define SAM9263_ETH_TX_BUFFER_SIZE
#define AT91C_EMAC_TX_WRAP
void sam9263EthIrqHandler(void)
SAM9263 Ethernet MAC interrupt service routine.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
void sam9263EthTick(NetInterface *interface)
SAM9263 Ethernet MAC timer handler.
#define AT91C_EMAC_RW_10
#define AT91C_EMAC_CODE_10
#define AT91C_EMAC_RX_WRAP
#define AT91C_EMAC_TX_LAST
#define AT91C_EMAC_RX_ADDRESS
error_t sam9263EthInit(NetInterface *interface)
SAM9263 Ethernet MAC initialization.
#define EMAC_RX_EOF
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
error_t sam9263EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void emacIrqWrapper(void)
NIC driver.
Definition: nic.h:161
error_t sam9263EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define EMAC_RX_LENGTH
#define SAM9263_ETH_TX_BUFFER_COUNT
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
#define AT91C_EMAC_RW_01
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define SAM9263_ETH_RX_BUFFER_SIZE
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void sam9263EthInitGpio(NetInterface *interface)
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define AT91C_EMAC_TX_LENGTH
#define osExitIsr(flag)
#define EMAC_RX_OWNERSHIP
#define AT91C_EMAC_RMII_MASK_C
AT91SAM9263 Ethernet MAC controller.
const NicDriver sam9263EthDriver
SAM9263 Ethernet MAC driver.
#define osEnterIsr()
Transmit buffer descriptor.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
void sam9263EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define FALSE
Definition: os_port.h:44
#define AT91C_EMAC_SOF_01
int bool_t
Definition: compiler_port.h:47
void sam9263EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Receive buffer descriptor.
MAC filter table entry.
Definition: ethernet.h:208
void sam9263EthEventHandler(NetInterface *interface)
SAM9263 Ethernet MAC event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:98