sama5d2_eth_driver.c
Go to the documentation of this file.
1 /**
2  * @file sama5d2_eth_driver.c
3  * @brief SAMA5D2 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "chip.h"
37 #include "peripherals/aic.h"
38 #include "peripherals/pio.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 8
51 #pragma location = SAMA5D2_ETH_RAM_SECTION
53 //RX buffer
54 #pragma data_alignment = 8
55 #pragma location = SAMA5D2_ETH_RAM_SECTION
57 //TX buffer descriptors
58 #pragma data_alignment = 4
59 #pragma location = SAMA5D2_ETH_RAM_SECTION
61 //RX buffer descriptors
62 #pragma data_alignment = 4
63 #pragma location = SAMA5D2_ETH_RAM_SECTION
65 
66 //Dummy TX buffer
67 #pragma data_alignment = 8
68 #pragma location = SAMA5D2_ETH_RAM_SECTION
70 //Dummy RX buffer
71 #pragma data_alignment = 8
72 #pragma location = SAMA5D2_ETH_RAM_SECTION
74 //Dummy TX buffer descriptors
75 #pragma data_alignment = 4
76 #pragma location = SAMA5D2_ETH_RAM_SECTION
77 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
78 //Dummy RX buffer descriptors
79 #pragma data_alignment = 4
80 #pragma location = SAMA5D2_ETH_RAM_SECTION
81 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
82 
83 //GCC compiler?
84 #else
85 
86 //TX buffer
88  __attribute__((aligned(8), __section__(SAMA5D2_ETH_RAM_SECTION)));
89 //RX buffer
91  __attribute__((aligned(8), __section__(SAMA5D2_ETH_RAM_SECTION)));
92 //TX buffer descriptors
94  __attribute__((aligned(4), __section__(SAMA5D2_ETH_RAM_SECTION)));
95 //RX buffer descriptors
97  __attribute__((aligned(4), __section__(SAMA5D2_ETH_RAM_SECTION)));
98 
99 //Dummy TX buffer
101  __attribute__((aligned(8), __section__(SAMA5D2_ETH_RAM_SECTION)));
102 //Dummy RX buffer
104  __attribute__((aligned(8), __section__(SAMA5D2_ETH_RAM_SECTION)));
105 //Dummy TX buffer descriptors
106 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
107  __attribute__((aligned(4), __section__(SAMA5D2_ETH_RAM_SECTION)));
108 //Dummy RX buffer descriptors
109 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
110  __attribute__((aligned(4), __section__(SAMA5D2_ETH_RAM_SECTION)));
111 
112 #endif
113 
114 //TX buffer index
115 static uint_t txBufferIndex;
116 //RX buffer index
117 static uint_t rxBufferIndex;
118 
119 
120 /**
121  * @brief SAMA5D2 Ethernet MAC driver
122  **/
123 
125 {
127  ETH_MTU,
138  TRUE,
139  TRUE,
140  TRUE,
141  FALSE
142 };
143 
144 
145 /**
146  * @brief SAMA5D2 Ethernet MAC initialization
147  * @param[in] interface Underlying network interface
148  * @return Error code
149  **/
150 
152 {
153  error_t error;
154  volatile uint32_t status;
155 
156  //Debug message
157  TRACE_INFO("Initializing SAMA5D2 Ethernet MAC...\r\n");
158 
159  //Save underlying network interface
160  nicDriverInterface = interface;
161 
162  //Enable GMAC peripheral clock
163  PMC->PMC_PCER0 = (1 << ID_GMAC0);
164 
165  //Disable transmit and receive circuits
166  GMAC0->GMAC_NCR = 0;
167 
168  //GPIO configuration
169  sama5d2EthInitGpio(interface);
170 
171  //Configure MDC clock speed
172  GMAC0->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
173  //Enable management port (MDC and MDIO)
174  GMAC0->GMAC_NCR |= GMAC_NCR_MPE;
175 
176  //Valid Ethernet PHY or switch driver?
177  if(interface->phyDriver != NULL)
178  {
179  //Ethernet PHY initialization
180  error = interface->phyDriver->init(interface);
181  }
182  else if(interface->switchDriver != NULL)
183  {
184  //Ethernet switch initialization
185  error = interface->switchDriver->init(interface);
186  }
187  else
188  {
189  //The interface is not properly configured
190  error = ERROR_FAILURE;
191  }
192 
193  //Any error to report?
194  if(error)
195  {
196  return error;
197  }
198 
199  //Set the MAC address of the station
200  GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
201  GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
202 
203  //The MAC supports 3 additional addresses for unicast perfect filtering
204  GMAC0->GMAC_SA[1].GMAC_SAB = 0;
205  GMAC0->GMAC_SA[2].GMAC_SAB = 0;
206  GMAC0->GMAC_SA[3].GMAC_SAB = 0;
207 
208  //Initialize hash table
209  GMAC0->GMAC_HRB = 0;
210  GMAC0->GMAC_HRT = 0;
211 
212  //Configure the receive filter
213  GMAC0->GMAC_NCFGR |= GMAC_NCFGR_MAXFS | GMAC_NCFGR_MTIHEN;
214 
215  //DMA configuration
216  GMAC0->GMAC_DCFGR = GMAC_DCFGR_DRBS(SAMA5D2_ETH_RX_BUFFER_SIZE / 64) |
217  GMAC_DCFGR_TXPBMS | GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_FBLDO_INCR4;
218 
219  GMAC0->GMAC_RBSRPQ[0] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
220  GMAC0->GMAC_RBSRPQ[1] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
221 
222  //Initialize buffer descriptors
223  sama5d2EthInitBufferDesc(interface);
224 
225  //Clear transmit status register
226  GMAC0->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
227  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
228  //Clear receive status register
229  GMAC0->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
230 
231  //First disable all GMAC interrupts
232  GMAC0->GMAC_IDR = 0xFFFFFFFF;
233  GMAC0->GMAC_IDRPQ[0] = 0xFFFFFFFF;
234  GMAC0->GMAC_IDRPQ[1] = 0xFFFFFFFF;
235 
236  //Only the desired ones are enabled
237  GMAC0->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
238  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
239 
240  //Read GMAC ISR register to clear any pending interrupt
241  status = GMAC0->GMAC_ISR;
242 
243  //Register interrupt handler
244  aic_set_source_vector(ID_GMAC0, sama5d2EthIrqHandler);
245 
246  //Configure interrupt priority
247  aic_configure(ID_GMAC0, AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE |
248  AIC_SMR_PRIOR(SAMA5D2_ETH_IRQ_PRIORITY));
249 
250  //Enable the GMAC to transmit and receive data
251  GMAC0->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
252 
253  //Accept any packets from the upper layer
254  osSetEvent(&interface->nicTxEvent);
255 
256  //Successful initialization
257  return NO_ERROR;
258 }
259 
260 
261 //SAMA5D2-Xplained-Ultra evaluation board?
262 #if defined(CONFIG_BOARD_SAMA5D2_XPLAINED)
263 
264 /**
265  * @brief GPIO configuration
266  * @param[in] interface Underlying network interface
267  **/
268 
269 void sama5d2EthInitGpio(NetInterface *interface)
270 {
271  struct _pin rmiiPins[] = PINS_GMAC_RMII_IOS3;
272 
273  //Configure RMII pins
274  pio_configure(rmiiPins, arraysize(rmiiPins));
275 
276  //Select RMII operation mode
277  GMAC0->GMAC_UR = GMAC_UR_RMII;
278 }
279 
280 #endif
281 
282 
283 /**
284  * @brief Initialize buffer descriptors
285  * @param[in] interface Underlying network interface
286  **/
287 
289 {
290  uint_t i;
291  uint32_t address;
292 
293  //Initialize TX buffer descriptors
294  for(i = 0; i < SAMA5D2_ETH_TX_BUFFER_COUNT; i++)
295  {
296  //Calculate the address of the current TX buffer
297  address = (uint32_t) txBuffer[i];
298  //Write the address to the descriptor entry
299  txBufferDesc[i].address = address;
300  //Initialize status field
301  txBufferDesc[i].status = GMAC_TX_USED;
302  }
303 
304  //Mark the last descriptor entry with the wrap flag
305  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
306  //Initialize TX buffer index
307  txBufferIndex = 0;
308 
309  //Initialize RX buffer descriptors
310  for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
311  {
312  //Calculate the address of the current RX buffer
313  address = (uint32_t) rxBuffer[i];
314  //Write the address to the descriptor entry
315  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
316  //Clear status field
317  rxBufferDesc[i].status = 0;
318  }
319 
320  //Mark the last descriptor entry with the wrap flag
321  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
322  //Initialize RX buffer index
323  rxBufferIndex = 0;
324 
325  //Initialize dummy TX buffer descriptors
326  for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
327  {
328  //Calculate the address of the current TX buffer
329  address = (uint32_t) dummyTxBuffer[i];
330  //Write the address to the descriptor entry
331  dummyTxBufferDesc[i].address = address;
332  //Initialize status field
333  dummyTxBufferDesc[i].status = GMAC_TX_USED;
334  }
335 
336  //Mark the last descriptor entry with the wrap flag
337  dummyTxBufferDesc[i - 1].status |= GMAC_TX_WRAP;
338 
339  //Initialize dummy RX buffer descriptors
340  for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
341  {
342  //Calculate the address of the current RX buffer
343  address = (uint32_t) dummyRxBuffer[i];
344  //Write the address to the descriptor entry
345  dummyRxBufferDesc[i].address = (address & GMAC_RX_ADDRESS) | GMAC_RX_OWNERSHIP;
346  //Clear status field
347  dummyRxBufferDesc[i].status = 0;
348  }
349 
350  //Mark the last descriptor entry with the wrap flag
351  dummyRxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
352 
353  //Start location of the TX descriptor list
354  GMAC0->GMAC_TBQB = (uint32_t) txBufferDesc;
355  GMAC0->GMAC_TBQBAPQ[0] = (uint32_t) dummyTxBufferDesc;
356  GMAC0->GMAC_TBQBAPQ[1] = (uint32_t) dummyTxBufferDesc;
357 
358  //Start location of the RX descriptor list
359  GMAC0->GMAC_RBQB = (uint32_t) rxBufferDesc;
360  GMAC0->GMAC_RBQBAPQ[0] = (uint32_t) dummyRxBufferDesc;
361  GMAC0->GMAC_RBQBAPQ[1] = (uint32_t) dummyRxBufferDesc;
362 }
363 
364 
365 /**
366  * @brief SAMA5D2 Ethernet MAC timer handler
367  *
368  * This routine is periodically called by the TCP/IP stack to handle periodic
369  * operations such as polling the link state
370  *
371  * @param[in] interface Underlying network interface
372  **/
373 
374 void sama5d2EthTick(NetInterface *interface)
375 {
376  //Valid Ethernet PHY or switch driver?
377  if(interface->phyDriver != NULL)
378  {
379  //Handle periodic operations
380  interface->phyDriver->tick(interface);
381  }
382  else if(interface->switchDriver != NULL)
383  {
384  //Handle periodic operations
385  interface->switchDriver->tick(interface);
386  }
387  else
388  {
389  //Just for sanity
390  }
391 }
392 
393 
394 /**
395  * @brief Enable interrupts
396  * @param[in] interface Underlying network interface
397  **/
398 
400 {
401  //Enable Ethernet MAC interrupts
402  aic_enable(ID_GMAC0);
403 
404  //Valid Ethernet PHY or switch driver?
405  if(interface->phyDriver != NULL)
406  {
407  //Enable Ethernet PHY interrupts
408  interface->phyDriver->enableIrq(interface);
409  }
410  else if(interface->switchDriver != NULL)
411  {
412  //Enable Ethernet switch interrupts
413  interface->switchDriver->enableIrq(interface);
414  }
415  else
416  {
417  //Just for sanity
418  }
419 }
420 
421 
422 /**
423  * @brief Disable interrupts
424  * @param[in] interface Underlying network interface
425  **/
426 
428 {
429  //Disable Ethernet MAC interrupts
430  aic_disable(ID_GMAC0);
431 
432  //Valid Ethernet PHY or switch driver?
433  if(interface->phyDriver != NULL)
434  {
435  //Disable Ethernet PHY interrupts
436  interface->phyDriver->disableIrq(interface);
437  }
438  else if(interface->switchDriver != NULL)
439  {
440  //Disable Ethernet switch interrupts
441  interface->switchDriver->disableIrq(interface);
442  }
443  else
444  {
445  //Just for sanity
446  }
447 }
448 
449 
450 /**
451  * @brief SAMA5D2 Ethernet MAC interrupt service routine
452  **/
453 
455 {
456  bool_t flag;
457  volatile uint32_t isr;
458  volatile uint32_t tsr;
459  volatile uint32_t rsr;
460 
461  //Interrupt service routine prologue
462  osEnterIsr();
463 
464  //This flag will be set if a higher priority task must be woken
465  flag = FALSE;
466 
467  //Each time the software reads GMAC_ISR, it has to check the
468  //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
469  isr = GMAC0->GMAC_ISRPQ[0];
470  isr = GMAC0->GMAC_ISRPQ[1];
471  isr = GMAC0->GMAC_ISR;
472  tsr = GMAC0->GMAC_TSR;
473  rsr = GMAC0->GMAC_RSR;
474 
475  //Packet transmitted?
476  if((tsr & (GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
477  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR)) != 0)
478  {
479  //Only clear TSR flags that are currently set
480  GMAC0->GMAC_TSR = tsr;
481 
482  //Check whether the TX buffer is available for writing
483  if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) != 0)
484  {
485  //Notify the TCP/IP stack that the transmitter is ready to send
486  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
487  }
488  }
489 
490  //Packet received?
491  if((rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) != 0)
492  {
493  //Set event flag
494  nicDriverInterface->nicEvent = TRUE;
495  //Notify the TCP/IP stack of the event
496  flag |= osSetEventFromIsr(&netEvent);
497  }
498 
499  //Write AIC_EOICR register before exiting
500  AIC->AIC_EOICR = 0;
501 
502  //Interrupt service routine epilogue
503  osExitIsr(flag);
504 }
505 
506 
507 /**
508  * @brief SAMA5D2 Ethernet MAC event handler
509  * @param[in] interface Underlying network interface
510  **/
511 
513 {
514  error_t error;
515  uint32_t rsr;
516 
517  //Read receive status
518  rsr = GMAC0->GMAC_RSR;
519 
520  //Packet received?
521  if((rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) != 0)
522  {
523  //Only clear RSR flags that are currently set
524  GMAC0->GMAC_RSR = rsr;
525 
526  //Process all pending packets
527  do
528  {
529  //Read incoming packet
530  error = sama5d2EthReceivePacket(interface);
531 
532  //No more data in the receive buffer?
533  } while(error != ERROR_BUFFER_EMPTY);
534  }
535 }
536 
537 
538 /**
539  * @brief Send a packet
540  * @param[in] interface Underlying network interface
541  * @param[in] buffer Multi-part buffer containing the data to send
542  * @param[in] offset Offset to the first data byte
543  * @param[in] ancillary Additional options passed to the stack along with
544  * the packet
545  * @return Error code
546  **/
547 
549  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
550 {
551  size_t length;
552 
553  //Retrieve the length of the packet
554  length = netBufferGetLength(buffer) - offset;
555 
556  //Check the frame length
558  {
559  //The transmitter can accept another packet
560  osSetEvent(&interface->nicTxEvent);
561  //Report an error
562  return ERROR_INVALID_LENGTH;
563  }
564 
565  //Make sure the current buffer is available for writing
566  if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) == 0)
567  {
568  return ERROR_FAILURE;
569  }
570 
571  //Copy user data to the transmit buffer
572  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
573 
574  //Set the necessary flags in the descriptor entry
575  if(txBufferIndex < (SAMA5D2_ETH_TX_BUFFER_COUNT - 1))
576  {
577  //Write the status word
578  txBufferDesc[txBufferIndex].status = GMAC_TX_LAST |
580 
581  //Point to the next buffer
582  txBufferIndex++;
583  }
584  else
585  {
586  //Write the status word
587  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP | GMAC_TX_LAST |
589 
590  //Wrap around
591  txBufferIndex = 0;
592  }
593 
594  //Data synchronization barrier
595  __DSB();
596 
597  //Set the TSTART bit to initiate transmission
598  GMAC0->GMAC_NCR |= GMAC_NCR_TSTART;
599 
600  //Check whether the next buffer is available for writing
601  if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) != 0)
602  {
603  //The transmitter can accept another packet
604  osSetEvent(&interface->nicTxEvent);
605  }
606 
607  //Successful processing
608  return NO_ERROR;
609 }
610 
611 
612 /**
613  * @brief Receive a packet
614  * @param[in] interface Underlying network interface
615  * @return Error code
616  **/
617 
619 {
620  static uint8_t temp[ETH_MAX_FRAME_SIZE];
621  error_t error;
622  uint_t i;
623  uint_t j;
624  uint_t sofIndex;
625  uint_t eofIndex;
626  size_t n;
627  size_t size;
628  size_t length;
629 
630  //Initialize SOF and EOF indices
631  sofIndex = UINT_MAX;
632  eofIndex = UINT_MAX;
633 
634  //Search for SOF and EOF flags
635  for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
636  {
637  //Point to the current entry
638  j = rxBufferIndex + i;
639 
640  //Wrap around to the beginning of the buffer if necessary
642  {
644  }
645 
646  //No more entries to process?
647  if((rxBufferDesc[j].address & GMAC_RX_OWNERSHIP) == 0)
648  {
649  //Stop processing
650  break;
651  }
652 
653  //A valid SOF has been found?
654  if((rxBufferDesc[j].status & GMAC_RX_SOF) != 0)
655  {
656  //Save the position of the SOF
657  sofIndex = i;
658  }
659 
660  //A valid EOF has been found?
661  if((rxBufferDesc[j].status & GMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
662  {
663  //Save the position of the EOF
664  eofIndex = i;
665  //Retrieve the length of the frame
666  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
667  //Limit the number of data to read
668  size = MIN(size, ETH_MAX_FRAME_SIZE);
669  //Stop processing since we have reached the end of the frame
670  break;
671  }
672  }
673 
674  //Determine the number of entries to process
675  if(eofIndex != UINT_MAX)
676  {
677  j = eofIndex + 1;
678  }
679  else if(sofIndex != UINT_MAX)
680  {
681  j = sofIndex;
682  }
683  else
684  {
685  j = i;
686  }
687 
688  //Total number of bytes that have been copied from the receive buffer
689  length = 0;
690 
691  //Process incoming frame
692  for(i = 0; i < j; i++)
693  {
694  //Any data to copy from current buffer?
695  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
696  {
697  //Calculate the number of bytes to read at a time
699  //Copy data from receive buffer
700  osMemcpy(temp + length, rxBuffer[rxBufferIndex], n);
701  //Update byte counters
702  length += n;
703  size -= n;
704  }
705 
706  //Mark the current buffer as free
707  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
708 
709  //Point to the following entry
710  rxBufferIndex++;
711 
712  //Wrap around to the beginning of the buffer if necessary
713  if(rxBufferIndex >= SAMA5D2_ETH_RX_BUFFER_COUNT)
714  {
715  rxBufferIndex = 0;
716  }
717  }
718 
719  //Any packet to process?
720  if(length > 0)
721  {
722  NetRxAncillary ancillary;
723 
724  //Additional options can be passed to the stack along with the packet
725  ancillary = NET_DEFAULT_RX_ANCILLARY;
726 
727  //Pass the packet to the upper layer
728  nicProcessPacket(interface, temp, length, &ancillary);
729  //Valid packet received
730  error = NO_ERROR;
731  }
732  else
733  {
734  //No more data in the receive buffer
735  error = ERROR_BUFFER_EMPTY;
736  }
737 
738  //Return status code
739  return error;
740 }
741 
742 
743 /**
744  * @brief Configure MAC address filtering
745  * @param[in] interface Underlying network interface
746  * @return Error code
747  **/
748 
750 {
751  uint_t i;
752  uint_t j;
753  uint_t k;
754  uint8_t *p;
755  uint32_t hashTable[2];
756  MacAddr unicastMacAddr[3];
757  MacFilterEntry *entry;
758 
759  //Debug message
760  TRACE_DEBUG("Updating MAC filter...\r\n");
761 
762  //Set the MAC address of the station
763  GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
764  GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
765 
766  //The MAC supports 3 additional addresses for unicast perfect filtering
767  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
768  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
769  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
770 
771  //The hash table is used for multicast address filtering
772  hashTable[0] = 0;
773  hashTable[1] = 0;
774 
775  //The MAC address filter contains the list of MAC addresses to accept
776  //when receiving an Ethernet frame
777  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
778  {
779  //Point to the current entry
780  entry = &interface->macAddrFilter[i];
781 
782  //Valid entry?
783  if(entry->refCount > 0)
784  {
785  //Multicast address?
786  if(macIsMulticastAddr(&entry->addr))
787  {
788  //Point to the MAC address
789  p = entry->addr.b;
790 
791  //Apply the hash function
792  k = (p[0] >> 6) ^ p[0];
793  k ^= (p[1] >> 4) ^ (p[1] << 2);
794  k ^= (p[2] >> 2) ^ (p[2] << 4);
795  k ^= (p[3] >> 6) ^ p[3];
796  k ^= (p[4] >> 4) ^ (p[4] << 2);
797  k ^= (p[5] >> 2) ^ (p[5] << 4);
798 
799  //The hash value is reduced to a 6-bit index
800  k &= 0x3F;
801 
802  //Update hash table contents
803  hashTable[k / 32] |= (1 << (k % 32));
804  }
805  else
806  {
807  //Up to 3 additional MAC addresses can be specified
808  if(j < 3)
809  {
810  //Save the unicast address
811  unicastMacAddr[j++] = entry->addr;
812  }
813  }
814  }
815  }
816 
817  //Configure the first unicast address filter
818  if(j >= 1)
819  {
820  //The address is activated when SAT register is written
821  GMAC0->GMAC_SA[1].GMAC_SAB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
822  GMAC0->GMAC_SA[1].GMAC_SAT = unicastMacAddr[0].w[2];
823  }
824  else
825  {
826  //The address is deactivated when SAB register is written
827  GMAC0->GMAC_SA[1].GMAC_SAB = 0;
828  }
829 
830  //Configure the second unicast address filter
831  if(j >= 2)
832  {
833  //The address is activated when SAT register is written
834  GMAC0->GMAC_SA[2].GMAC_SAB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
835  GMAC0->GMAC_SA[2].GMAC_SAT = unicastMacAddr[1].w[2];
836  }
837  else
838  {
839  //The address is deactivated when SAB register is written
840  GMAC0->GMAC_SA[2].GMAC_SAB = 0;
841  }
842 
843  //Configure the third unicast address filter
844  if(j >= 3)
845  {
846  //The address is activated when SAT register is written
847  GMAC0->GMAC_SA[3].GMAC_SAB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
848  GMAC0->GMAC_SA[3].GMAC_SAT = unicastMacAddr[2].w[2];
849  }
850  else
851  {
852  //The address is deactivated when SAB register is written
853  GMAC0->GMAC_SA[3].GMAC_SAB = 0;
854  }
855 
856  //Configure the multicast address filter
857  GMAC0->GMAC_HRB = hashTable[0];
858  GMAC0->GMAC_HRT = hashTable[1];
859 
860  //Debug message
861  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC0->GMAC_HRB);
862  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC0->GMAC_HRT);
863 
864  //Successful processing
865  return NO_ERROR;
866 }
867 
868 
869 /**
870  * @brief Adjust MAC configuration parameters for proper operation
871  * @param[in] interface Underlying network interface
872  * @return Error code
873  **/
874 
876 {
877  uint32_t config;
878 
879  //Read network configuration register
880  config = GMAC0->GMAC_NCFGR;
881 
882  //10BASE-T or 100BASE-TX operation mode?
883  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
884  {
885  config |= GMAC_NCFGR_SPD;
886  }
887  else
888  {
889  config &= ~GMAC_NCFGR_SPD;
890  }
891 
892  //Half-duplex or full-duplex mode?
893  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
894  {
895  config |= GMAC_NCFGR_FD;
896  }
897  else
898  {
899  config &= ~GMAC_NCFGR_FD;
900  }
901 
902  //Write configuration value back to NCFGR register
903  GMAC0->GMAC_NCFGR = config;
904 
905  //Successful processing
906  return NO_ERROR;
907 }
908 
909 
910 /**
911  * @brief Write PHY register
912  * @param[in] opcode Access type (2 bits)
913  * @param[in] phyAddr PHY address (5 bits)
914  * @param[in] regAddr Register address (5 bits)
915  * @param[in] data Register value
916  **/
917 
918 void sama5d2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
919  uint8_t regAddr, uint16_t data)
920 {
921  uint32_t temp;
922 
923  //Valid opcode?
924  if(opcode == SMI_OPCODE_WRITE)
925  {
926  //Set up a write operation
927  temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
928  //PHY address
929  temp |= GMAC_MAN_PHYA(phyAddr);
930  //Register address
931  temp |= GMAC_MAN_REGA(regAddr);
932  //Register value
933  temp |= GMAC_MAN_DATA(data);
934 
935  //Start a write operation
936  GMAC0->GMAC_MAN = temp;
937  //Wait for the write to complete
938  while((GMAC0->GMAC_NSR & GMAC_NSR_IDLE) == 0)
939  {
940  }
941  }
942  else
943  {
944  //The MAC peripheral only supports standard Clause 22 opcodes
945  }
946 }
947 
948 
949 /**
950  * @brief Read PHY register
951  * @param[in] opcode Access type (2 bits)
952  * @param[in] phyAddr PHY address (5 bits)
953  * @param[in] regAddr Register address (5 bits)
954  * @return Register value
955  **/
956 
957 uint16_t sama5d2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
958  uint8_t regAddr)
959 {
960  uint16_t data;
961  uint32_t temp;
962 
963  //Valid opcode?
964  if(opcode == SMI_OPCODE_READ)
965  {
966  //Set up a read operation
967  temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
968  //PHY address
969  temp |= GMAC_MAN_PHYA(phyAddr);
970  //Register address
971  temp |= GMAC_MAN_REGA(regAddr);
972 
973  //Start a read operation
974  GMAC0->GMAC_MAN = temp;
975  //Wait for the read to complete
976  while((GMAC0->GMAC_NSR & GMAC_NSR_IDLE) == 0)
977  {
978  }
979 
980  //Get register value
981  data = GMAC0->GMAC_MAN & GMAC_MAN_DATA_Msk;
982  }
983  else
984  {
985  //The MAC peripheral only supports standard Clause 22 opcodes
986  data = 0;
987  }
988 
989  //Return the value of the PHY register
990  return data;
991 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
#define SAMA5D2_ETH_DUMMY_BUFFER_SIZE
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
void sama5d2EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define GMAC_TX_WRAP
uint8_t data[]
Definition: ethernet.h:209
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
Receive buffer descriptor.
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:103
__start_packed struct @5 MacAddr
MAC address.
error_t sama5d2EthReceivePacket(NetInterface *interface)
Receive a packet.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
error_t sama5d2EthInit(NetInterface *interface)
SAMA5D2 Ethernet MAC initialization.
#define GMAC_TX_LENGTH
#define GMAC_TX_LAST
void sama5d2EthEventHandler(NetInterface *interface)
SAMA5D2 Ethernet MAC event handler.
Transmit buffer descriptor.
#define GMAC_RX_WRAP
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define GMAC_RX_OWNERSHIP
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define SAMA5D2_ETH_TX_BUFFER_SIZE
#define FALSE
Definition: os_port.h:46
#define osMemcpy(dest, src, length)
Definition: os_port.h:134
SAMA5D2 Ethernet MAC driver.
error_t
Error codes.
Definition: error.h:42
void sama5d2EthTick(NetInterface *interface)
SAMA5D2 Ethernet MAC timer handler.
void sama5d2EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define GMAC_RX_SOF
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
void sama5d2EthInitGpio(NetInterface *interface)
#define GMAC_RX_EOF
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
#define SAMA5D2_ETH_RAM_SECTION
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
void sama5d2EthIrqHandler(void)
SAMA5D2 Ethernet MAC interrupt service routine.
#define GMAC_RX_LENGTH
void sama5d2EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define SAMA5D2_ETH_RX_BUFFER_SIZE
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define osEnterIsr()
#define SAMA5D2_ETH_IRQ_PRIORITY
const NicDriver sama5d2EthDriver
SAMA5D2 Ethernet MAC driver.
error_t sama5d2EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t sama5d2EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void sama5d2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t sama5d2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define GMAC_TX_USED
error_t sama5d2EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define SAMA5D2_ETH_DUMMY_BUFFER_COUNT
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
#define SAMA5D2_ETH_TX_BUFFER_COUNT
NIC driver.
Definition: nic.h:257
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
#define SAMA5D2_ETH_RX_BUFFER_COUNT
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define GMAC_RX_ADDRESS
#define arraysize(a)
Definition: os_port.h:70
Ethernet interface.
Definition: nic.h:82