sama5d2_eth_driver.c
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1 /**
2  * @file sama5d2_eth_driver.c
3  * @brief SAMA5D2 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "chip.h"
37 #include "peripherals/aic.h"
38 #include "peripherals/pio.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 8
51 #pragma location = ".region_ddr_nocache"
53 //RX buffer
54 #pragma data_alignment = 8
55 #pragma location = ".region_ddr_nocache"
57 //TX buffer descriptors
58 #pragma data_alignment = 4
59 #pragma location = ".region_ddr_nocache"
61 //RX buffer descriptors
62 #pragma data_alignment = 4
63 #pragma location = ".region_ddr_nocache"
65 
66 //Dummy TX buffer
67 #pragma data_alignment = 8
68 #pragma location = ".region_ddr_nocache"
70 //Dummy RX buffer
71 #pragma data_alignment = 8
72 #pragma location = ".region_ddr_nocache"
74 //Dummy TX buffer descriptors
75 #pragma data_alignment = 4
76 #pragma location = ".region_ddr_nocache"
77 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
78 //Dummy RX buffer descriptors
79 #pragma data_alignment = 4
80 #pragma location = ".region_ddr_nocache"
81 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
82 
83 //GCC compiler?
84 #else
85 
86 //TX buffer
88  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
89 //RX buffer
91  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
92 //TX buffer descriptors
94  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
95 //RX buffer descriptors
97  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
98 
99 //Dummy TX buffer
101  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
102 //Dummy RX buffer
104  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
105 //Dummy TX buffer descriptors
106 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
107  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
108 //Dummy RX buffer descriptors
109 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
110  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
111 
112 #endif
113 
114 //TX buffer index
115 static uint_t txBufferIndex;
116 //RX buffer index
117 static uint_t rxBufferIndex;
118 
119 
120 /**
121  * @brief SAMA5D2 Ethernet MAC driver
122  **/
123 
125 {
127  ETH_MTU,
138  TRUE,
139  TRUE,
140  TRUE,
141  FALSE
142 };
143 
144 
145 /**
146  * @brief SAMA5D2 Ethernet MAC initialization
147  * @param[in] interface Underlying network interface
148  * @return Error code
149  **/
150 
152 {
153  error_t error;
154  volatile uint32_t status;
155 
156  //Debug message
157  TRACE_INFO("Initializing SAMA5D2 Ethernet MAC...\r\n");
158 
159  //Save underlying network interface
160  nicDriverInterface = interface;
161 
162  //Enable GMAC peripheral clock
163  PMC->PMC_PCER0 = (1 << ID_GMAC0);
164 
165  //Disable transmit and receive circuits
166  GMAC0->GMAC_NCR = 0;
167 
168  //GPIO configuration
169  sama5d2EthInitGpio(interface);
170 
171  //Configure MDC clock speed
172  GMAC0->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
173  //Enable management port (MDC and MDIO)
174  GMAC0->GMAC_NCR |= GMAC_NCR_MPE;
175 
176  //PHY transceiver initialization
177  error = interface->phyDriver->init(interface);
178  //Failed to initialize PHY transceiver?
179  if(error)
180  return error;
181 
182  //Set the MAC address of the station
183  GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
184  GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
185 
186  //The MAC supports 3 additional addresses for unicast perfect filtering
187  GMAC0->GMAC_SA[1].GMAC_SAB = 0;
188  GMAC0->GMAC_SA[2].GMAC_SAB = 0;
189  GMAC0->GMAC_SA[3].GMAC_SAB = 0;
190 
191  //Initialize hash table
192  GMAC0->GMAC_HRB = 0;
193  GMAC0->GMAC_HRT = 0;
194 
195  //Configure the receive filter
196  GMAC0->GMAC_NCFGR |= GMAC_NCFGR_MAXFS | GMAC_NCFGR_MTIHEN;
197 
198  //DMA configuration
199  GMAC0->GMAC_DCFGR = GMAC_DCFGR_DRBS(SAMA5D2_ETH_RX_BUFFER_SIZE / 64) |
200  GMAC_DCFGR_TXPBMS | GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_FBLDO_INCR4;
201 
202  GMAC0->GMAC_RBSRPQ[0] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
203  GMAC0->GMAC_RBSRPQ[1] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
204 
205  //Initialize buffer descriptors
206  sama5d2EthInitBufferDesc(interface);
207 
208  //Clear transmit status register
209  GMAC0->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
210  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
211  //Clear receive status register
212  GMAC0->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
213 
214  //First disable all GMAC interrupts
215  GMAC0->GMAC_IDR = 0xFFFFFFFF;
216  GMAC0->GMAC_IDRPQ[0] = 0xFFFFFFFF;
217  GMAC0->GMAC_IDRPQ[1] = 0xFFFFFFFF;
218 
219  //Only the desired ones are enabled
220  GMAC0->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
221  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
222 
223  //Read GMAC ISR register to clear any pending interrupt
224  status = GMAC0->GMAC_ISR;
225 
226  //Register interrupt handler
227  aic_set_source_vector(ID_GMAC0, sama5d2EthIrqHandler);
228 
229  //Configure interrupt priority
230  aic_configure(ID_GMAC0, AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE |
231  AIC_SMR_PRIOR(SAMA5D2_ETH_IRQ_PRIORITY));
232 
233  //Enable the GMAC to transmit and receive data
234  GMAC0->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
235 
236  //Accept any packets from the upper layer
237  osSetEvent(&interface->nicTxEvent);
238 
239  //Successful initialization
240  return NO_ERROR;
241 }
242 
243 
244 //SAMA5D2-Xplained-Ultra evaluation board?
245 #if defined(CONFIG_BOARD_SAMA5D2_XPLAINED)
246 
247 /**
248  * @brief GPIO configuration
249  * @param[in] interface Underlying network interface
250  **/
251 
252 void sama5d2EthInitGpio(NetInterface *interface)
253 {
254  struct _pin rmiiPins[] = PINS_GMAC_RMII_IOS3;
255 
256  //Configure RMII pins
257  pio_configure(rmiiPins, arraysize(rmiiPins));
258 
259  //Select RMII operation mode
260  GMAC0->GMAC_UR = GMAC_UR_RMII;
261 }
262 
263 #endif
264 
265 
266 /**
267  * @brief Initialize buffer descriptors
268  * @param[in] interface Underlying network interface
269  **/
270 
272 {
273  uint_t i;
274  uint32_t address;
275 
276  //Initialize TX buffer descriptors
277  for(i = 0; i < SAMA5D2_ETH_TX_BUFFER_COUNT; i++)
278  {
279  //Calculate the address of the current TX buffer
280  address = (uint32_t) txBuffer[i];
281  //Write the address to the descriptor entry
282  txBufferDesc[i].address = address;
283  //Initialize status field
284  txBufferDesc[i].status = GMAC_TX_USED;
285  }
286 
287  //Mark the last descriptor entry with the wrap flag
288  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
289  //Initialize TX buffer index
290  txBufferIndex = 0;
291 
292  //Initialize RX buffer descriptors
293  for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
294  {
295  //Calculate the address of the current RX buffer
296  address = (uint32_t) rxBuffer[i];
297  //Write the address to the descriptor entry
298  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
299  //Clear status field
300  rxBufferDesc[i].status = 0;
301  }
302 
303  //Mark the last descriptor entry with the wrap flag
304  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
305  //Initialize RX buffer index
306  rxBufferIndex = 0;
307 
308  //Initialize dummy TX buffer descriptors
309  for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
310  {
311  //Calculate the address of the current TX buffer
312  address = (uint32_t) dummyTxBuffer[i];
313  //Write the address to the descriptor entry
314  dummyTxBufferDesc[i].address = address;
315  //Initialize status field
316  dummyTxBufferDesc[i].status = GMAC_TX_USED;
317  }
318 
319  //Mark the last descriptor entry with the wrap flag
320  dummyTxBufferDesc[i - 1].status |= GMAC_TX_WRAP;
321 
322  //Initialize dummy RX buffer descriptors
323  for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
324  {
325  //Calculate the address of the current RX buffer
326  address = (uint32_t) dummyRxBuffer[i];
327  //Write the address to the descriptor entry
328  dummyRxBufferDesc[i].address = (address & GMAC_RX_ADDRESS) | GMAC_RX_OWNERSHIP;
329  //Clear status field
330  dummyRxBufferDesc[i].status = 0;
331  }
332 
333  //Mark the last descriptor entry with the wrap flag
334  dummyRxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
335 
336  //Start location of the TX descriptor list
337  GMAC0->GMAC_TBQB = (uint32_t) txBufferDesc;
338  GMAC0->GMAC_TBQBAPQ[0] = (uint32_t) dummyTxBufferDesc;
339  GMAC0->GMAC_TBQBAPQ[1] = (uint32_t) dummyTxBufferDesc;
340 
341  //Start location of the RX descriptor list
342  GMAC0->GMAC_RBQB = (uint32_t) rxBufferDesc;
343  GMAC0->GMAC_RBQBAPQ[0] = (uint32_t) dummyRxBufferDesc;
344  GMAC0->GMAC_RBQBAPQ[1] = (uint32_t) dummyRxBufferDesc;
345 }
346 
347 
348 /**
349  * @brief SAMA5D2 Ethernet MAC timer handler
350  *
351  * This routine is periodically called by the TCP/IP stack to
352  * handle periodic operations such as polling the link state
353  *
354  * @param[in] interface Underlying network interface
355  **/
356 
357 void sama5d2EthTick(NetInterface *interface)
358 {
359  //Handle periodic operations
360  interface->phyDriver->tick(interface);
361 }
362 
363 
364 /**
365  * @brief Enable interrupts
366  * @param[in] interface Underlying network interface
367  **/
368 
370 {
371  //Enable Ethernet MAC interrupts
372  aic_enable(ID_GMAC0);
373  //Enable Ethernet PHY interrupts
374  interface->phyDriver->enableIrq(interface);
375 }
376 
377 
378 /**
379  * @brief Disable interrupts
380  * @param[in] interface Underlying network interface
381  **/
382 
384 {
385  //Disable Ethernet MAC interrupts
386  aic_disable(ID_GMAC0);
387  //Disable Ethernet PHY interrupts
388  interface->phyDriver->disableIrq(interface);
389 }
390 
391 
392 /**
393  * @brief SAMA5D2 Ethernet MAC interrupt service routine
394  **/
395 
397 {
398  bool_t flag;
399  volatile uint32_t isr;
400  volatile uint32_t tsr;
401  volatile uint32_t rsr;
402 
403  //Interrupt service routine prologue
404  osEnterIsr();
405 
406  //This flag will be set if a higher priority task must be woken
407  flag = FALSE;
408 
409  //Each time the software reads GMAC_ISR, it has to check the
410  //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
411  isr = GMAC0->GMAC_ISRPQ[0];
412  isr = GMAC0->GMAC_ISRPQ[1];
413  isr = GMAC0->GMAC_ISR;
414  tsr = GMAC0->GMAC_TSR;
415  rsr = GMAC0->GMAC_RSR;
416 
417  //A packet has been transmitted?
418  if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
419  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
420  {
421  //Only clear TSR flags that are currently set
422  GMAC0->GMAC_TSR = tsr;
423 
424  //Check whether the TX buffer is available for writing
425  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
426  {
427  //Notify the TCP/IP stack that the transmitter is ready to send
428  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
429  }
430  }
431 
432  //A packet has been received?
433  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
434  {
435  //Set event flag
436  nicDriverInterface->nicEvent = TRUE;
437  //Notify the TCP/IP stack of the event
438  flag |= osSetEventFromIsr(&netEvent);
439  }
440 
441  //Write AIC_EOICR register before exiting
442  AIC->AIC_EOICR = 0;
443 
444  //Interrupt service routine epilogue
445  osExitIsr(flag);
446 }
447 
448 
449 /**
450  * @brief SAMA5D2 Ethernet MAC event handler
451  * @param[in] interface Underlying network interface
452  **/
453 
455 {
456  error_t error;
457  uint32_t rsr;
458 
459  //Read receive status
460  rsr = GMAC0->GMAC_RSR;
461 
462  //Packet received?
463  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
464  {
465  //Only clear RSR flags that are currently set
466  GMAC0->GMAC_RSR = rsr;
467 
468  //Process all pending packets
469  do
470  {
471  //Read incoming packet
472  error = sama5d2EthReceivePacket(interface);
473 
474  //No more data in the receive buffer?
475  } while(error != ERROR_BUFFER_EMPTY);
476  }
477 }
478 
479 
480 /**
481  * @brief Send a packet
482  * @param[in] interface Underlying network interface
483  * @param[in] buffer Multi-part buffer containing the data to send
484  * @param[in] offset Offset to the first data byte
485  * @return Error code
486  **/
487 
489  const NetBuffer *buffer, size_t offset)
490 {
491  size_t length;
492 
493  //Retrieve the length of the packet
494  length = netBufferGetLength(buffer) - offset;
495 
496  //Check the frame length
498  {
499  //The transmitter can accept another packet
500  osSetEvent(&interface->nicTxEvent);
501  //Report an error
502  return ERROR_INVALID_LENGTH;
503  }
504 
505  //Make sure the current buffer is available for writing
506  if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
507  return ERROR_FAILURE;
508 
509  //Copy user data to the transmit buffer
510  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
511 
512  //Set the necessary flags in the descriptor entry
513  if(txBufferIndex < (SAMA5D2_ETH_TX_BUFFER_COUNT - 1))
514  {
515  //Write the status word
516  txBufferDesc[txBufferIndex].status =
518 
519  //Point to the next buffer
520  txBufferIndex++;
521  }
522  else
523  {
524  //Write the status word
525  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
527 
528  //Wrap around
529  txBufferIndex = 0;
530  }
531 
532  //Data synchronization barrier
533  __DSB();
534 
535  //Set the TSTART bit to initiate transmission
536  GMAC0->GMAC_NCR |= GMAC_NCR_TSTART;
537 
538  //Check whether the next buffer is available for writing
539  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
540  {
541  //The transmitter can accept another packet
542  osSetEvent(&interface->nicTxEvent);
543  }
544 
545  //Successful processing
546  return NO_ERROR;
547 }
548 
549 
550 /**
551  * @brief Receive a packet
552  * @param[in] interface Underlying network interface
553  * @return Error code
554  **/
555 
557 {
558  static uint8_t temp[ETH_MAX_FRAME_SIZE];
559  error_t error;
560  uint_t i;
561  uint_t j;
562  uint_t sofIndex;
563  uint_t eofIndex;
564  size_t n;
565  size_t size;
566  size_t length;
567 
568  //Initialize SOF and EOF indices
569  sofIndex = UINT_MAX;
570  eofIndex = UINT_MAX;
571 
572  //Search for SOF and EOF flags
573  for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
574  {
575  //Point to the current entry
576  j = rxBufferIndex + i;
577 
578  //Wrap around to the beginning of the buffer if necessary
581 
582  //No more entries to process?
583  if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
584  {
585  //Stop processing
586  break;
587  }
588  //A valid SOF has been found?
589  if(rxBufferDesc[j].status & GMAC_RX_SOF)
590  {
591  //Save the position of the SOF
592  sofIndex = i;
593  }
594  //A valid EOF has been found?
595  if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
596  {
597  //Save the position of the EOF
598  eofIndex = i;
599  //Retrieve the length of the frame
600  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
601  //Limit the number of data to read
602  size = MIN(size, ETH_MAX_FRAME_SIZE);
603  //Stop processing since we have reached the end of the frame
604  break;
605  }
606  }
607 
608  //Determine the number of entries to process
609  if(eofIndex != UINT_MAX)
610  j = eofIndex + 1;
611  else if(sofIndex != UINT_MAX)
612  j = sofIndex;
613  else
614  j = i;
615 
616  //Total number of bytes that have been copied from the receive buffer
617  length = 0;
618 
619  //Process incoming frame
620  for(i = 0; i < j; i++)
621  {
622  //Any data to copy from current buffer?
623  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
624  {
625  //Calculate the number of bytes to read at a time
627  //Copy data from receive buffer
628  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
629  //Update byte counters
630  length += n;
631  size -= n;
632  }
633 
634  //Mark the current buffer as free
635  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
636 
637  //Point to the following entry
638  rxBufferIndex++;
639 
640  //Wrap around to the beginning of the buffer if necessary
641  if(rxBufferIndex >= SAMA5D2_ETH_RX_BUFFER_COUNT)
642  rxBufferIndex = 0;
643  }
644 
645  //Any packet to process?
646  if(length > 0)
647  {
648  //Pass the packet to the upper layer
649  nicProcessPacket(interface, temp, length);
650  //Valid packet received
651  error = NO_ERROR;
652  }
653  else
654  {
655  //No more data in the receive buffer
656  error = ERROR_BUFFER_EMPTY;
657  }
658 
659  //Return status code
660  return error;
661 }
662 
663 
664 /**
665  * @brief Configure MAC address filtering
666  * @param[in] interface Underlying network interface
667  * @return Error code
668  **/
669 
671 {
672  uint_t i;
673  uint_t j;
674  uint_t k;
675  uint8_t *p;
676  uint32_t hashTable[2];
677  MacAddr unicastMacAddr[3];
678  MacFilterEntry *entry;
679 
680  //Debug message
681  TRACE_DEBUG("Updating MAC filter...\r\n");
682 
683  //Set the MAC address of the station
684  GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
685  GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
686 
687  //The MAC supports 3 additional addresses for unicast perfect filtering
688  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
689  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
690  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
691 
692  //The hash table is used for multicast address filtering
693  hashTable[0] = 0;
694  hashTable[1] = 0;
695 
696  //The MAC address filter contains the list of MAC addresses to accept
697  //when receiving an Ethernet frame
698  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
699  {
700  //Point to the current entry
701  entry = &interface->macAddrFilter[i];
702 
703  //Valid entry?
704  if(entry->refCount > 0)
705  {
706  //Multicast address?
707  if(macIsMulticastAddr(&entry->addr))
708  {
709  //Point to the MAC address
710  p = entry->addr.b;
711 
712  //Apply the hash function
713  k = (p[0] >> 6) ^ p[0];
714  k ^= (p[1] >> 4) ^ (p[1] << 2);
715  k ^= (p[2] >> 2) ^ (p[2] << 4);
716  k ^= (p[3] >> 6) ^ p[3];
717  k ^= (p[4] >> 4) ^ (p[4] << 2);
718  k ^= (p[5] >> 2) ^ (p[5] << 4);
719 
720  //The hash value is reduced to a 6-bit index
721  k &= 0x3F;
722 
723  //Update hash table contents
724  hashTable[k / 32] |= (1 << (k % 32));
725  }
726  else
727  {
728  //Up to 3 additional MAC addresses can be specified
729  if(j < 3)
730  {
731  //Save the unicast address
732  unicastMacAddr[j++] = entry->addr;
733  }
734  }
735  }
736  }
737 
738  //Configure the first unicast address filter
739  if(j >= 1)
740  {
741  //The address is activated when SAT register is written
742  GMAC0->GMAC_SA[1].GMAC_SAB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
743  GMAC0->GMAC_SA[1].GMAC_SAT = unicastMacAddr[0].w[2];
744  }
745  else
746  {
747  //The address is deactivated when SAB register is written
748  GMAC0->GMAC_SA[1].GMAC_SAB = 0;
749  }
750 
751  //Configure the second unicast address filter
752  if(j >= 2)
753  {
754  //The address is activated when SAT register is written
755  GMAC0->GMAC_SA[2].GMAC_SAB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
756  GMAC0->GMAC_SA[2].GMAC_SAT = unicastMacAddr[1].w[2];
757  }
758  else
759  {
760  //The address is deactivated when SAB register is written
761  GMAC0->GMAC_SA[2].GMAC_SAB = 0;
762  }
763 
764  //Configure the third unicast address filter
765  if(j >= 3)
766  {
767  //The address is activated when SAT register is written
768  GMAC0->GMAC_SA[3].GMAC_SAB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
769  GMAC0->GMAC_SA[3].GMAC_SAT = unicastMacAddr[2].w[2];
770  }
771  else
772  {
773  //The address is deactivated when SAB register is written
774  GMAC0->GMAC_SA[3].GMAC_SAB = 0;
775  }
776 
777  //Configure the multicast address filter
778  GMAC0->GMAC_HRB = hashTable[0];
779  GMAC0->GMAC_HRT = hashTable[1];
780 
781  //Debug message
782  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC0->GMAC_HRB);
783  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC0->GMAC_HRT);
784 
785  //Successful processing
786  return NO_ERROR;
787 }
788 
789 
790 /**
791  * @brief Adjust MAC configuration parameters for proper operation
792  * @param[in] interface Underlying network interface
793  * @return Error code
794  **/
795 
797 {
798  uint32_t config;
799 
800  //Read network configuration register
801  config = GMAC0->GMAC_NCFGR;
802 
803  //10BASE-T or 100BASE-TX operation mode?
804  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
805  config |= GMAC_NCFGR_SPD;
806  else
807  config &= ~GMAC_NCFGR_SPD;
808 
809  //Half-duplex or full-duplex mode?
810  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
811  config |= GMAC_NCFGR_FD;
812  else
813  config &= ~GMAC_NCFGR_FD;
814 
815  //Write configuration value back to NCFGR register
816  GMAC0->GMAC_NCFGR = config;
817 
818  //Successful processing
819  return NO_ERROR;
820 }
821 
822 
823 /**
824  * @brief Write PHY register
825  * @param[in] opcode Access type (2 bits)
826  * @param[in] phyAddr PHY address (5 bits)
827  * @param[in] regAddr Register address (5 bits)
828  * @param[in] data Register value
829  **/
830 
831 void sama5d2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
832  uint8_t regAddr, uint16_t data)
833 {
834  uint32_t temp;
835 
836  //Valid opcode?
837  if(opcode == SMI_OPCODE_WRITE)
838  {
839  //Set up a write operation
840  temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
841  //PHY address
842  temp |= GMAC_MAN_PHYA(phyAddr);
843  //Register address
844  temp |= GMAC_MAN_REGA(regAddr);
845  //Register value
846  temp |= GMAC_MAN_DATA(data);
847 
848  //Start a write operation
849  GMAC0->GMAC_MAN = temp;
850  //Wait for the write to complete
851  while(!(GMAC0->GMAC_NSR & GMAC_NSR_IDLE))
852  {
853  }
854  }
855  else
856  {
857  //The MAC peripheral only supports standard Clause 22 opcodes
858  }
859 }
860 
861 
862 /**
863  * @brief Read PHY register
864  * @param[in] opcode Access type (2 bits)
865  * @param[in] phyAddr PHY address (5 bits)
866  * @param[in] regAddr Register address (5 bits)
867  * @return Register value
868  **/
869 
870 uint16_t sama5d2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
871  uint8_t regAddr)
872 {
873  uint16_t data;
874  uint32_t temp;
875 
876  //Valid opcode?
877  if(opcode == SMI_OPCODE_READ)
878  {
879  //Set up a read operation
880  temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
881  //PHY address
882  temp |= GMAC_MAN_PHYA(phyAddr);
883  //Register address
884  temp |= GMAC_MAN_REGA(regAddr);
885 
886  //Start a read operation
887  GMAC0->GMAC_MAN = temp;
888  //Wait for the read to complete
889  while(!(GMAC0->GMAC_NSR & GMAC_NSR_IDLE))
890  {
891  }
892 
893  //Get register value
894  data = GMAC0->GMAC_MAN & GMAC_MAN_DATA_Msk;
895  }
896  else
897  {
898  //The MAC peripheral only supports standard Clause 22 opcodes
899  data = 0;
900  }
901 
902  //Return the value of the PHY register
903  return data;
904 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define SAMA5D2_ETH_DUMMY_BUFFER_SIZE
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
void sama5d2EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define GMAC_TX_WRAP
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
Receive buffer descriptor.
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
error_t sama5d2EthReceivePacket(NetInterface *interface)
Receive a packet.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
error_t sama5d2EthInit(NetInterface *interface)
SAMA5D2 Ethernet MAC initialization.
#define GMAC_TX_LENGTH
#define GMAC_TX_LAST
void sama5d2EthEventHandler(NetInterface *interface)
SAMA5D2 Ethernet MAC event handler.
Transmit buffer descriptor.
#define GMAC_RX_WRAP
#define GMAC_RX_OWNERSHIP
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define SAMA5D2_ETH_TX_BUFFER_SIZE
#define FALSE
Definition: os_port.h:46
SAMA5D2 Ethernet MAC controller.
error_t
Error codes.
Definition: error.h:42
void sama5d2EthTick(NetInterface *interface)
SAMA5D2 Ethernet MAC timer handler.
void sama5d2EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define GMAC_RX_SOF
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:222
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
void sama5d2EthInitGpio(NetInterface *interface)
#define GMAC_RX_EOF
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
error_t sama5d2EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void sama5d2EthIrqHandler(void)
SAMA5D2 Ethernet MAC interrupt service routine.
#define GMAC_RX_LENGTH
void sama5d2EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define SAMA5D2_ETH_RX_BUFFER_SIZE
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
#define osEnterIsr()
#define SAMA5D2_ETH_IRQ_PRIORITY
const NicDriver sama5d2EthDriver
SAMA5D2 Ethernet MAC driver.
error_t sama5d2EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void sama5d2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t sama5d2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
#define GMAC_TX_USED
error_t sama5d2EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define SAMA5D2_ETH_DUMMY_BUFFER_COUNT
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
#define SAMA5D2_ETH_TX_BUFFER_COUNT
NIC driver.
Definition: nic.h:179
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
#define SAMA5D2_ETH_RX_BUFFER_COUNT
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define GMAC_RX_ADDRESS
__start_packed struct @108 MacAddr
MAC address.
#define arraysize(a)
Definition: os_port.h:70
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79