sama5d2_eth_driver.c
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1 /**
2  * @file sama5d2_eth_driver.c
3  * @brief SAMA5D2 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "chip.h"
35 #include "peripherals/aic.h"
36 #include "peripherals/pio.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
49 #pragma location = ".region_ddr_nocache"
51 //RX buffer
52 #pragma data_alignment = 8
53 #pragma location = ".region_ddr_nocache"
55 //TX buffer descriptors
56 #pragma data_alignment = 4
57 #pragma location = ".region_ddr_nocache"
59 //RX buffer descriptors
60 #pragma data_alignment = 4
61 #pragma location = ".region_ddr_nocache"
63 
64 //Dummy TX buffer
65 #pragma data_alignment = 8
66 #pragma location = ".region_ddr_nocache"
68 //Dummy RX buffer
69 #pragma data_alignment = 8
70 #pragma location = ".region_ddr_nocache"
72 //Dummy TX buffer descriptors
73 #pragma data_alignment = 4
74 #pragma location = ".region_ddr_nocache"
75 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
76 //Dummy RX buffer descriptors
77 #pragma data_alignment = 4
78 #pragma location = ".region_ddr_nocache"
79 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
80 
81 //GCC compiler?
82 #else
83 
84 //TX buffer
86  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
87 //RX buffer
89  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
90 //TX buffer descriptors
92  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
93 //RX buffer descriptors
95  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
96 
97 //Dummy TX buffer
99  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
100 //Dummy RX buffer
102  __attribute__((aligned(8), __section__(".region_ddr_nocache")));
103 //Dummy TX buffer descriptors
104 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
105  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
106 //Dummy RX buffer descriptors
107 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
108  __attribute__((aligned(4), __section__(".region_ddr_nocache")));
109 
110 #endif
111 
112 //TX buffer index
113 static uint_t txBufferIndex;
114 //RX buffer index
115 static uint_t rxBufferIndex;
116 
117 
118 /**
119  * @brief SAMA5D2 Ethernet MAC driver
120  **/
121 
123 {
125  ETH_MTU,
136  TRUE,
137  TRUE,
138  TRUE,
139  FALSE
140 };
141 
142 
143 /**
144  * @brief SAMA5D2 Ethernet MAC initialization
145  * @param[in] interface Underlying network interface
146  * @return Error code
147  **/
148 
150 {
151  error_t error;
152  volatile uint32_t status;
153 
154  //Debug message
155  TRACE_INFO("Initializing SAMA5D2 Ethernet MAC...\r\n");
156 
157  //Save underlying network interface
158  nicDriverInterface = interface;
159 
160  //Enable GMAC peripheral clock
161  PMC->PMC_PCER0 = (1 << ID_GMAC0);
162 
163  //GPIO configuration
164  sama5d2EthInitGpio(interface);
165 
166  //Configure MDC clock speed
167  GMAC0->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
168  //Enable management port (MDC and MDIO)
169  GMAC0->GMAC_NCR |= GMAC_NCR_MPE;
170 
171  //PHY transceiver initialization
172  error = interface->phyDriver->init(interface);
173  //Failed to initialize PHY transceiver?
174  if(error)
175  return error;
176 
177  //Set the MAC address
178  GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
179  GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
180 
181  //Configure the receive filter
182  GMAC0->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
183 
184  //DMA configuration
185  GMAC0->GMAC_DCFGR = GMAC_DCFGR_DRBS(SAMA5D2_ETH_RX_BUFFER_SIZE / 64) |
186  GMAC_DCFGR_TXPBMS | GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_FBLDO_INCR4;
187 
188  GMAC0->GMAC_RBSRPQ[0] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
189  GMAC0->GMAC_RBSRPQ[1] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
190 
191  //Initialize hash table
192  GMAC0->GMAC_HRB = 0;
193  GMAC0->GMAC_HRT = 0;
194 
195  //Initialize buffer descriptors
196  sama5d2EthInitBufferDesc(interface);
197 
198  //Clear transmit status register
199  GMAC0->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
200  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
201  //Clear receive status register
202  GMAC0->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
203 
204  //First disable all GMAC interrupts
205  GMAC0->GMAC_IDR = 0xFFFFFFFF;
206  GMAC0->GMAC_IDRPQ[0] = 0xFFFFFFFF;
207  GMAC0->GMAC_IDRPQ[1] = 0xFFFFFFFF;
208 
209  //Only the desired ones are enabled
210  GMAC0->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
211  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
212 
213  //Read GMAC ISR register to clear any pending interrupt
214  status = GMAC0->GMAC_ISR;
215 
216  //Register interrupt handler
217  aic_set_source_vector(ID_GMAC0, sama5d2EthIrqHandler);
218 
219  //Configure interrupt priority
220  aic_configure(ID_GMAC0, AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE |
221  AIC_SMR_PRIOR(SAMA5D2_ETH_IRQ_PRIORITY));
222 
223  //Enable the GMAC to transmit and receive data
224  GMAC0->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
225 
226  //Accept any packets from the upper layer
227  osSetEvent(&interface->nicTxEvent);
228 
229  //Successful initialization
230  return NO_ERROR;
231 }
232 
233 
234 //SAMA5D2-Xplained-Ultra evaluation board?
235 #if defined(CONFIG_BOARD_SAMA5D2_XPLAINED)
236 
237 /**
238  * @brief GPIO configuration
239  * @param[in] interface Underlying network interface
240  **/
241 
242 void sama5d2EthInitGpio(NetInterface *interface)
243 {
244  struct _pin rmiiPins[] = PINS_GMAC_RMII_IOS3;
245 
246  //Configure RMII pins
247  pio_configure(rmiiPins, arraysize(rmiiPins));
248 
249  //Select RMII operation mode
250  GMAC0->GMAC_UR = GMAC_UR_RMII;
251 }
252 
253 #endif
254 
255 
256 /**
257  * @brief Initialize buffer descriptors
258  * @param[in] interface Underlying network interface
259  **/
260 
262 {
263  uint_t i;
264  uint32_t address;
265 
266  //Initialize TX buffer descriptors
267  for(i = 0; i < SAMA5D2_ETH_TX_BUFFER_COUNT; i++)
268  {
269  //Calculate the address of the current TX buffer
270  address = (uint32_t) txBuffer[i];
271  //Write the address to the descriptor entry
272  txBufferDesc[i].address = address;
273  //Initialize status field
274  txBufferDesc[i].status = GMAC_TX_USED;
275  }
276 
277  //Mark the last descriptor entry with the wrap flag
278  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
279  //Initialize TX buffer index
280  txBufferIndex = 0;
281 
282  //Initialize RX buffer descriptors
283  for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
284  {
285  //Calculate the address of the current RX buffer
286  address = (uint32_t) rxBuffer[i];
287  //Write the address to the descriptor entry
288  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
289  //Clear status field
290  rxBufferDesc[i].status = 0;
291  }
292 
293  //Mark the last descriptor entry with the wrap flag
294  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
295  //Initialize RX buffer index
296  rxBufferIndex = 0;
297 
298  //Initialize dummy TX buffer descriptors
299  for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
300  {
301  //Calculate the address of the current TX buffer
302  address = (uint32_t) dummyTxBuffer[i];
303  //Write the address to the descriptor entry
304  dummyTxBufferDesc[i].address = address;
305  //Initialize status field
306  dummyTxBufferDesc[i].status = GMAC_TX_USED;
307  }
308 
309  //Mark the last descriptor entry with the wrap flag
310  dummyTxBufferDesc[i - 1].status |= GMAC_TX_WRAP;
311 
312  //Initialize dummy RX buffer descriptors
313  for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
314  {
315  //Calculate the address of the current RX buffer
316  address = (uint32_t) dummyRxBuffer[i];
317  //Write the address to the descriptor entry
318  dummyRxBufferDesc[i].address = (address & GMAC_RX_ADDRESS) | GMAC_RX_OWNERSHIP;
319  //Clear status field
320  dummyRxBufferDesc[i].status = 0;
321  }
322 
323  //Mark the last descriptor entry with the wrap flag
324  dummyRxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
325 
326  //Start location of the TX descriptor list
327  GMAC0->GMAC_TBQB = (uint32_t) txBufferDesc;
328  GMAC0->GMAC_TBQBAPQ[0] = (uint32_t) dummyTxBufferDesc;
329  GMAC0->GMAC_TBQBAPQ[1] = (uint32_t) dummyTxBufferDesc;
330 
331  //Start location of the RX descriptor list
332  GMAC0->GMAC_RBQB = (uint32_t) rxBufferDesc;
333  GMAC0->GMAC_RBQBAPQ[0] = (uint32_t) dummyRxBufferDesc;
334  GMAC0->GMAC_RBQBAPQ[1] = (uint32_t) dummyRxBufferDesc;
335 }
336 
337 
338 /**
339  * @brief SAMA5D2 Ethernet MAC timer handler
340  *
341  * This routine is periodically called by the TCP/IP stack to
342  * handle periodic operations such as polling the link state
343  *
344  * @param[in] interface Underlying network interface
345  **/
346 
347 void sama5d2EthTick(NetInterface *interface)
348 {
349  //Handle periodic operations
350  interface->phyDriver->tick(interface);
351 }
352 
353 
354 /**
355  * @brief Enable interrupts
356  * @param[in] interface Underlying network interface
357  **/
358 
360 {
361  //Enable Ethernet MAC interrupts
362  aic_enable(ID_GMAC0);
363  //Enable Ethernet PHY interrupts
364  interface->phyDriver->enableIrq(interface);
365 }
366 
367 
368 /**
369  * @brief Disable interrupts
370  * @param[in] interface Underlying network interface
371  **/
372 
374 {
375  //Disable Ethernet MAC interrupts
376  aic_disable(ID_GMAC0);
377  //Disable Ethernet PHY interrupts
378  interface->phyDriver->disableIrq(interface);
379 }
380 
381 
382 /**
383  * @brief SAMA5D2 Ethernet MAC interrupt service routine
384  **/
385 
387 {
388  bool_t flag;
389  volatile uint32_t isr;
390  volatile uint32_t tsr;
391  volatile uint32_t rsr;
392 
393  //Enter interrupt service routine
394  osEnterIsr();
395 
396  //This flag will be set if a higher priority task must be woken
397  flag = FALSE;
398 
399  //Each time the software reads GMAC_ISR, it has to check the
400  //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
401  isr = GMAC0->GMAC_ISRPQ[0];
402  isr = GMAC0->GMAC_ISRPQ[1];
403  isr = GMAC0->GMAC_ISR;
404  tsr = GMAC0->GMAC_TSR;
405  rsr = GMAC0->GMAC_RSR;
406 
407  //A packet has been transmitted?
408  if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
409  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
410  {
411  //Only clear TSR flags that are currently set
412  GMAC0->GMAC_TSR = tsr;
413 
414  //Check whether the TX buffer is available for writing
415  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
416  {
417  //Notify the TCP/IP stack that the transmitter is ready to send
418  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
419  }
420  }
421 
422  //A packet has been received?
423  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
424  {
425  //Set event flag
426  nicDriverInterface->nicEvent = TRUE;
427  //Notify the TCP/IP stack of the event
428  flag |= osSetEventFromIsr(&netEvent);
429  }
430 
431  //Write AIC_EOICR register before exiting
432  AIC->AIC_EOICR = 0;
433 
434  //Leave interrupt service routine
435  osExitIsr(flag);
436 }
437 
438 
439 /**
440  * @brief SAMA5D2 Ethernet MAC event handler
441  * @param[in] interface Underlying network interface
442  **/
443 
445 {
446  error_t error;
447  uint32_t rsr;
448 
449  //Read receive status
450  rsr = GMAC0->GMAC_RSR;
451 
452  //Packet received?
453  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
454  {
455  //Only clear RSR flags that are currently set
456  GMAC0->GMAC_RSR = rsr;
457 
458  //Process all pending packets
459  do
460  {
461  //Read incoming packet
462  error = sama5d2EthReceivePacket(interface);
463 
464  //No more data in the receive buffer?
465  } while(error != ERROR_BUFFER_EMPTY);
466  }
467 }
468 
469 
470 /**
471  * @brief Send a packet
472  * @param[in] interface Underlying network interface
473  * @param[in] buffer Multi-part buffer containing the data to send
474  * @param[in] offset Offset to the first data byte
475  * @return Error code
476  **/
477 
479  const NetBuffer *buffer, size_t offset)
480 {
481  size_t length;
482 
483  //Retrieve the length of the packet
484  length = netBufferGetLength(buffer) - offset;
485 
486  //Check the frame length
488  {
489  //The transmitter can accept another packet
490  osSetEvent(&interface->nicTxEvent);
491  //Report an error
492  return ERROR_INVALID_LENGTH;
493  }
494 
495  //Make sure the current buffer is available for writing
496  if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
497  return ERROR_FAILURE;
498 
499  //Copy user data to the transmit buffer
500  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
501 
502  //Set the necessary flags in the descriptor entry
503  if(txBufferIndex < (SAMA5D2_ETH_TX_BUFFER_COUNT - 1))
504  {
505  //Write the status word
506  txBufferDesc[txBufferIndex].status =
508 
509  //Point to the next buffer
510  txBufferIndex++;
511  }
512  else
513  {
514  //Write the status word
515  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
517 
518  //Wrap around
519  txBufferIndex = 0;
520  }
521 
522  //Data synchronization barrier
523  __DSB();
524 
525  //Set the TSTART bit to initiate transmission
526  GMAC0->GMAC_NCR |= GMAC_NCR_TSTART;
527 
528  //Check whether the next buffer is available for writing
529  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
530  {
531  //The transmitter can accept another packet
532  osSetEvent(&interface->nicTxEvent);
533  }
534 
535  //Successful processing
536  return NO_ERROR;
537 }
538 
539 
540 /**
541  * @brief Receive a packet
542  * @param[in] interface Underlying network interface
543  * @return Error code
544  **/
545 
547 {
548  static uint8_t temp[ETH_MAX_FRAME_SIZE];
549  error_t error;
550  uint_t i;
551  uint_t j;
552  uint_t sofIndex;
553  uint_t eofIndex;
554  size_t n;
555  size_t size;
556  size_t length;
557 
558  //Initialize SOF and EOF indices
559  sofIndex = UINT_MAX;
560  eofIndex = UINT_MAX;
561 
562  //Search for SOF and EOF flags
563  for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
564  {
565  //Point to the current entry
566  j = rxBufferIndex + i;
567 
568  //Wrap around to the beginning of the buffer if necessary
571 
572  //No more entries to process?
573  if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
574  {
575  //Stop processing
576  break;
577  }
578  //A valid SOF has been found?
579  if(rxBufferDesc[j].status & GMAC_RX_SOF)
580  {
581  //Save the position of the SOF
582  sofIndex = i;
583  }
584  //A valid EOF has been found?
585  if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
586  {
587  //Save the position of the EOF
588  eofIndex = i;
589  //Retrieve the length of the frame
590  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
591  //Limit the number of data to read
592  size = MIN(size, ETH_MAX_FRAME_SIZE);
593  //Stop processing since we have reached the end of the frame
594  break;
595  }
596  }
597 
598  //Determine the number of entries to process
599  if(eofIndex != UINT_MAX)
600  j = eofIndex + 1;
601  else if(sofIndex != UINT_MAX)
602  j = sofIndex;
603  else
604  j = i;
605 
606  //Total number of bytes that have been copied from the receive buffer
607  length = 0;
608 
609  //Process incoming frame
610  for(i = 0; i < j; i++)
611  {
612  //Any data to copy from current buffer?
613  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
614  {
615  //Calculate the number of bytes to read at a time
617  //Copy data from receive buffer
618  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
619  //Update byte counters
620  length += n;
621  size -= n;
622  }
623 
624  //Mark the current buffer as free
625  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
626 
627  //Point to the following entry
628  rxBufferIndex++;
629 
630  //Wrap around to the beginning of the buffer if necessary
631  if(rxBufferIndex >= SAMA5D2_ETH_RX_BUFFER_COUNT)
632  rxBufferIndex = 0;
633  }
634 
635  //Any packet to process?
636  if(length > 0)
637  {
638  //Pass the packet to the upper layer
639  nicProcessPacket(interface, temp, length);
640  //Valid packet received
641  error = NO_ERROR;
642  }
643  else
644  {
645  //No more data in the receive buffer
646  error = ERROR_BUFFER_EMPTY;
647  }
648 
649  //Return status code
650  return error;
651 }
652 
653 
654 /**
655  * @brief Configure MAC address filtering
656  * @param[in] interface Underlying network interface
657  * @return Error code
658  **/
659 
661 {
662  uint_t i;
663  uint_t k;
664  uint8_t *p;
665  uint32_t hashTable[2];
666  MacFilterEntry *entry;
667 
668  //Debug message
669  TRACE_DEBUG("Updating SAMA5D2 hash table...\r\n");
670 
671  //Clear hash table
672  hashTable[0] = 0;
673  hashTable[1] = 0;
674 
675  //The MAC address filter contains the list of MAC addresses to accept
676  //when receiving an Ethernet frame
677  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
678  {
679  //Point to the current entry
680  entry = &interface->macAddrFilter[i];
681 
682  //Valid entry?
683  if(entry->refCount > 0)
684  {
685  //Point to the MAC address
686  p = entry->addr.b;
687 
688  //Apply the hash function
689  k = (p[0] >> 6) ^ p[0];
690  k ^= (p[1] >> 4) ^ (p[1] << 2);
691  k ^= (p[2] >> 2) ^ (p[2] << 4);
692  k ^= (p[3] >> 6) ^ p[3];
693  k ^= (p[4] >> 4) ^ (p[4] << 2);
694  k ^= (p[5] >> 2) ^ (p[5] << 4);
695 
696  //The hash value is reduced to a 6-bit index
697  k &= 0x3F;
698 
699  //Update hash table contents
700  hashTable[k / 32] |= (1 << (k % 32));
701  }
702  }
703 
704  //Write the hash table
705  GMAC0->GMAC_HRB = hashTable[0];
706  GMAC0->GMAC_HRT = hashTable[1];
707 
708  //Debug message
709  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC0->GMAC_HRB);
710  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC0->GMAC_HRT);
711 
712  //Successful processing
713  return NO_ERROR;
714 }
715 
716 
717 /**
718  * @brief Adjust MAC configuration parameters for proper operation
719  * @param[in] interface Underlying network interface
720  * @return Error code
721  **/
722 
724 {
725  uint32_t config;
726 
727  //Read network configuration register
728  config = GMAC0->GMAC_NCFGR;
729 
730  //10BASE-T or 100BASE-TX operation mode?
731  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
732  config |= GMAC_NCFGR_SPD;
733  else
734  config &= ~GMAC_NCFGR_SPD;
735 
736  //Half-duplex or full-duplex mode?
737  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
738  config |= GMAC_NCFGR_FD;
739  else
740  config &= ~GMAC_NCFGR_FD;
741 
742  //Write configuration value back to NCFGR register
743  GMAC0->GMAC_NCFGR = config;
744 
745  //Successful processing
746  return NO_ERROR;
747 }
748 
749 
750 /**
751  * @brief Write PHY register
752  * @param[in] phyAddr PHY address
753  * @param[in] regAddr Register address
754  * @param[in] data Register value
755  **/
756 
757 void sama5d2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
758 {
759  uint32_t value;
760 
761  //Set up a write operation
762  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
763  //PHY address
764  value |= GMAC_MAN_PHYA(phyAddr);
765  //Register address
766  value |= GMAC_MAN_REGA(regAddr);
767  //Register value
768  value |= GMAC_MAN_DATA(data);
769 
770  //Start a write operation
771  GMAC0->GMAC_MAN = value;
772  //Wait for the write to complete
773  while(!(GMAC0->GMAC_NSR & GMAC_NSR_IDLE));
774 }
775 
776 
777 /**
778  * @brief Read PHY register
779  * @param[in] phyAddr PHY address
780  * @param[in] regAddr Register address
781  * @return Register value
782  **/
783 
784 uint16_t sama5d2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
785 {
786  uint32_t value;
787 
788  //Set up a read operation
789  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
790  //PHY address
791  value |= GMAC_MAN_PHYA(phyAddr);
792  //Register address
793  value |= GMAC_MAN_REGA(regAddr);
794 
795  //Start a read operation
796  GMAC0->GMAC_MAN = value;
797  //Wait for the read to complete
798  while(!(GMAC0->GMAC_NSR & GMAC_NSR_IDLE));
799 
800  //Return PHY register contents
801  return GMAC0->GMAC_MAN & GMAC_MAN_DATA_Msk;
802 }
#define GMAC_RX_SOF
error_t sama5d2EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
#define SAMA5D2_ETH_RX_BUFFER_COUNT
TCP/IP stack core.
void sama5d2EthIrqHandler(void)
SAMA5D2 Ethernet MAC interrupt service routine.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define GMAC_RX_EOF
Generic error code.
Definition: error.h:43
error_t sama5d2EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define txBuffer
void sama5d2EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define SAMA5D2_ETH_TX_BUFFER_SIZE
#define SAMA5D2_ETH_IRQ_PRIORITY
const NicDriver sama5d2EthDriver
SAMA5D2 Ethernet MAC driver.
#define GMAC_TX_USED
SAMA5D2 Ethernet MAC controller.
#define GMAC_TX_WRAP
void sama5d2EthInitGpio(NetInterface *interface)
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define arraysize(a)
Definition: os_port.h:68
#define SAMA5D2_ETH_TX_BUFFER_COUNT
error_t sama5d2EthInit(NetInterface *interface)
SAMA5D2 Ethernet MAC initialization.
uint16_t sama5d2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define GMAC_TX_LAST
#define SAMA5D2_ETH_RX_BUFFER_SIZE
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define SAMA5D2_ETH_DUMMY_BUFFER_COUNT
void sama5d2EthTick(NetInterface *interface)
SAMA5D2 Ethernet MAC timer handler.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void sama5d2EthEventHandler(NetInterface *interface)
SAMA5D2 Ethernet MAC event handler.
error_t sama5d2EthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIN(a, b)
Definition: os_port.h:60
#define GMAC_RX_OWNERSHIP
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define GMAC_RX_ADDRESS
error_t sama5d2EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define GMAC_RX_WRAP
#define rxBuffer
Ipv6Addr address
void sama5d2EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
Receive buffer descriptor.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define SAMA5D2_ETH_DUMMY_BUFFER_SIZE
Transmit buffer descriptor.
#define osExitIsr(flag)
void sama5d2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define osEnterIsr()
#define GMAC_RX_LENGTH
#define GMAC_TX_LENGTH
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
void sama5d2EthEnableIrq(NetInterface *interface)
Enable interrupts.
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98