sam7x_eth_driver.c
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1 /**
2  * @file sam7x_eth_driver.c
3  * @brief AT91SAM7X Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "at91sam7x256.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
50 //RX buffer
51 #pragma data_alignment = 8
53 //TX buffer descriptors
54 #pragma data_alignment = 4
55 static Sam7xTxBufferDesc txBufferDesc[SAM7X_ETH_TX_BUFFER_COUNT];
56 //RX buffer descriptors
57 #pragma data_alignment = 4
58 static Sam7xRxBufferDesc rxBufferDesc[SAM7X_ETH_RX_BUFFER_COUNT];
59 
60 //Keil MDK-ARM or GCC compiler?
61 #else
62 
63 //TX buffer
65  __attribute__((aligned(8)));
66 //RX buffer
68  __attribute__((aligned(8)));
69 //TX buffer descriptors
71  __attribute__((aligned(4)));
72 //RX buffer descriptors
74  __attribute__((aligned(4)));
75 
76 #endif
77 
78 //TX buffer index
79 static uint_t txBufferIndex;
80 //RX buffer index
81 static uint_t rxBufferIndex;
82 
83 
84 /**
85  * @brief SAM7X Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  FALSE
106 };
107 
108 
109 /**
110  * @brief SAM7X Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118  volatile uint32_t status;
119 
120  //Debug message
121  TRACE_INFO("Initializing SAM7X Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Enable EMAC peripheral clock
127  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_EMAC);
128 
129  //Disable transmit and receive circuits
130  AT91C_BASE_EMAC->EMAC_NCR = 0;
131 
132  //GPIO configuration
133  sam7xEthInitGpio(interface);
134 
135  //Configure MDC clock speed
136  AT91C_BASE_EMAC->EMAC_NCFGR = AT91C_EMAC_CLK_HCLK_32;
137  //Enable management port (MDC and MDIO)
138  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
139 
140  //Valid Ethernet PHY or switch driver?
141  if(interface->phyDriver != NULL)
142  {
143  //Ethernet PHY initialization
144  error = interface->phyDriver->init(interface);
145  }
146  else if(interface->switchDriver != NULL)
147  {
148  //Ethernet switch initialization
149  error = interface->switchDriver->init(interface);
150  }
151  else
152  {
153  //The interface is not properly configured
154  error = ERROR_FAILURE;
155  }
156 
157  //Any error to report?
158  if(error)
159  {
160  return error;
161  }
162 
163  //Set the MAC address of the station
164  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
165  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
166 
167  //The MAC supports 3 additional addresses for unicast perfect filtering
168  AT91C_BASE_EMAC->EMAC_SA2L = 0;
169  AT91C_BASE_EMAC->EMAC_SA3L = 0;
170  AT91C_BASE_EMAC->EMAC_SA4L = 0;
171 
172  //Initialize hash table
173  AT91C_BASE_EMAC->EMAC_HRB = 0;
174  AT91C_BASE_EMAC->EMAC_HRT = 0;
175 
176  //Configure the receive filter
177  AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_BIG | AT91C_EMAC_MTI;
178 
179  //Initialize buffer descriptors
180  sam7xEthInitBufferDesc(interface);
181 
182  //Clear transmit status register
183  AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_UND | AT91C_EMAC_COMP |
184  AT91C_EMAC_BEX | AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL |
185  AT91C_EMAC_UBR;
186 
187  //Clear receive status register
188  AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | AT91C_EMAC_REC |
189  AT91C_EMAC_BNA;
190 
191  //First disable all EMAC interrupts
192  AT91C_BASE_EMAC->EMAC_IDR = 0xFFFFFFFF;
193 
194  //Only the desired ones are enabled
195  AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_ROVR | AT91C_EMAC_TCOMP |
196  AT91C_EMAC_TXERR | AT91C_EMAC_RLEX | AT91C_EMAC_TUNDR |
197  AT91C_EMAC_RXUBR | AT91C_EMAC_RCOMP;
198 
199  //Read EMAC_ISR register to clear any pending interrupt
200  status = AT91C_BASE_EMAC->EMAC_ISR;
201  (void) status;
202 
203  //Configure interrupt controller
204  AT91C_BASE_AIC->AIC_SMR[AT91C_ID_EMAC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
205  AT91C_BASE_AIC->AIC_SVR[AT91C_ID_EMAC] = (uint32_t) emacIrqWrapper;
206 
207  //Clear EMAC interrupt flag
208  AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_EMAC);
209 
210  //Enable the EMAC to transmit and receive data
211  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE;
212 
213  //Accept any packets from the upper layer
214  osSetEvent(&interface->nicTxEvent);
215 
216  //Successful initialization
217  return NO_ERROR;
218 }
219 
220 
221 /**
222  * @brief GPIO configuration
223  * @param[in] interface Underlying network interface
224  **/
225 
226 __weak_func void sam7xEthInitGpio(NetInterface *interface)
227 {
228 //SAM7-EX256 evaluation board?
229 #if defined(USE_SAM7_EX256)
230  //Enable PIO peripheral clock
231  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOB);
232 
233  //Disable pull-up resistors on MII pins
234  AT91C_BASE_PIOB->PIO_PPUDR = AT91C_EMAC_MII_MASK;
235  //Disable interrupts-on-change
236  AT91C_BASE_PIOB->PIO_IDR = AT91C_EMAC_MII_MASK;
237  //Assign MII pins to peripheral A function
238  AT91C_BASE_PIOB->PIO_ASR = AT91C_EMAC_MII_MASK;
239  //Disable the PIO from controlling the corresponding pins
240  AT91C_BASE_PIOB->PIO_PDR = AT91C_EMAC_MII_MASK;
241 
242  //Select MII operation mode and enable transceiver clock
243  AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;
244 #endif
245 }
246 
247 
248 /**
249  * @brief Initialize buffer descriptors
250  * @param[in] interface Underlying network interface
251  **/
252 
254 {
255  uint_t i;
256  uint32_t address;
257 
258  //Initialize TX buffer descriptors
259  for(i = 0; i < SAM7X_ETH_TX_BUFFER_COUNT; i++)
260  {
261  //Calculate the address of the current TX buffer
262  address = (uint32_t) txBuffer[i];
263  //Write the address to the descriptor entry
264  txBufferDesc[i].address = address;
265  //Initialize status field
266  txBufferDesc[i].status = AT91C_EMAC_TX_USED;
267  }
268 
269  //Mark the last descriptor entry with the wrap flag
270  txBufferDesc[i - 1].status |= AT91C_EMAC_TX_WRAP;
271  //Initialize TX buffer index
272  txBufferIndex = 0;
273 
274  //Initialize RX buffer descriptors
275  for(i = 0; i < SAM7X_ETH_RX_BUFFER_COUNT; i++)
276  {
277  //Calculate the address of the current RX buffer
278  address = (uint32_t) rxBuffer[i];
279  //Write the address to the descriptor entry
280  rxBufferDesc[i].address = address & AT91C_EMAC_RX_ADDRESS;
281  //Clear status field
282  rxBufferDesc[i].status = 0;
283  }
284 
285  //Mark the last descriptor entry with the wrap flag
286  rxBufferDesc[i - 1].address |= AT91C_EMAC_RX_WRAP;
287  //Initialize RX buffer index
288  rxBufferIndex = 0;
289 
290  //Start location of the TX descriptor list
291  AT91C_BASE_EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
292  //Start location of the RX descriptor list
293  AT91C_BASE_EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
294 }
295 
296 
297 /**
298  * @brief SAM7X Ethernet MAC timer handler
299  *
300  * This routine is periodically called by the TCP/IP stack to handle periodic
301  * operations such as polling the link state
302  *
303  * @param[in] interface Underlying network interface
304  **/
305 
306 void sam7xEthTick(NetInterface *interface)
307 {
308  //Valid Ethernet PHY or switch driver?
309  if(interface->phyDriver != NULL)
310  {
311  //Handle periodic operations
312  interface->phyDriver->tick(interface);
313  }
314  else if(interface->switchDriver != NULL)
315  {
316  //Handle periodic operations
317  interface->switchDriver->tick(interface);
318  }
319  else
320  {
321  //Just for sanity
322  }
323 }
324 
325 
326 /**
327  * @brief Enable interrupts
328  * @param[in] interface Underlying network interface
329  **/
330 
332 {
333  //Enable Ethernet MAC interrupts
334  AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_EMAC);
335 
336  //Valid Ethernet PHY or switch driver?
337  if(interface->phyDriver != NULL)
338  {
339  //Enable Ethernet PHY interrupts
340  interface->phyDriver->enableIrq(interface);
341  }
342  else if(interface->switchDriver != NULL)
343  {
344  //Enable Ethernet switch interrupts
345  interface->switchDriver->enableIrq(interface);
346  }
347  else
348  {
349  //Just for sanity
350  }
351 }
352 
353 
354 /**
355  * @brief Disable interrupts
356  * @param[in] interface Underlying network interface
357  **/
358 
360 {
361  //Disable Ethernet MAC interrupts
362  AT91C_BASE_AIC->AIC_IDCR = (1 << AT91C_ID_EMAC);
363 
364  //Valid Ethernet PHY or switch driver?
365  if(interface->phyDriver != NULL)
366  {
367  //Disable Ethernet PHY interrupts
368  interface->phyDriver->disableIrq(interface);
369  }
370  else if(interface->switchDriver != NULL)
371  {
372  //Disable Ethernet switch interrupts
373  interface->switchDriver->disableIrq(interface);
374  }
375  else
376  {
377  //Just for sanity
378  }
379 }
380 
381 
382 /**
383  * @brief SAM7X Ethernet MAC interrupt service routine
384  **/
385 
387 {
388  bool_t flag;
389  volatile uint32_t isr;
390  volatile uint32_t tsr;
391  volatile uint32_t rsr;
392 
393  //Interrupt service routine prologue
394  osEnterIsr();
395 
396  //This flag will be set if a higher priority task must be woken
397  flag = FALSE;
398 
399  //Each time the software reads EMAC_ISR, it has to check the contents of
400  //EMAC_TSR, EMAC_RSR and EMAC_NSR (see SAM7X errata 41.3.3.2)
401  isr = AT91C_BASE_EMAC->EMAC_ISR;
402  tsr = AT91C_BASE_EMAC->EMAC_TSR;
403  rsr = AT91C_BASE_EMAC->EMAC_RSR;
404  (void) isr;
405 
406  //Packet transmitted?
407  if((tsr & (AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
408  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR)) != 0)
409  {
410  //Only clear TSR flags that are currently set
411  AT91C_BASE_EMAC->EMAC_TSR = tsr;
412 
413  //Check whether the TX buffer is available for writing
414  if((txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED) != 0)
415  {
416  //Notify the TCP/IP stack that the transmitter is ready to send
417  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
418  }
419  }
420 
421  //Packet received?
422  if((rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA)) != 0)
423  {
424  //Set event flag
425  nicDriverInterface->nicEvent = TRUE;
426  //Notify the TCP/IP stack of the event
427  flag |= osSetEventFromIsr(&netEvent);
428  }
429 
430  //Write AIC_EOICR register before exiting
431  AT91C_BASE_AIC->AIC_EOICR = 0;
432 
433  //Interrupt service routine epilogue
434  osExitIsr(flag);
435 }
436 
437 
438 /**
439  * @brief SAM7X Ethernet MAC event handler
440  * @param[in] interface Underlying network interface
441  **/
442 
444 {
445  error_t error;
446  uint32_t rsr;
447 
448  //Read receive status
449  rsr = AT91C_BASE_EMAC->EMAC_RSR;
450 
451  //Packet received?
452  if((rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA)) != 0)
453  {
454  //Only clear RSR flags that are currently set
455  AT91C_BASE_EMAC->EMAC_RSR = rsr;
456 
457  //Process all pending packets
458  do
459  {
460  //Read incoming packet
461  error = sam7xEthReceivePacket(interface);
462 
463  //No more data in the receive buffer?
464  } while(error != ERROR_BUFFER_EMPTY);
465  }
466 }
467 
468 
469 /**
470  * @brief Send a packet
471  * @param[in] interface Underlying network interface
472  * @param[in] buffer Multi-part buffer containing the data to send
473  * @param[in] offset Offset to the first data byte
474  * @param[in] ancillary Additional options passed to the stack along with
475  * the packet
476  * @return Error code
477  **/
478 
480  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
481 {
482  size_t length;
483 
484  //Retrieve the length of the packet
485  length = netBufferGetLength(buffer) - offset;
486 
487  //Check the frame length
489  {
490  //The transmitter can accept another packet
491  osSetEvent(&interface->nicTxEvent);
492  //Report an error
493  return ERROR_INVALID_LENGTH;
494  }
495 
496  //Make sure the current buffer is available for writing
497  if((txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED) == 0)
498  {
499  return ERROR_FAILURE;
500  }
501 
502  //Copy user data to the transmit buffer
503  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
504 
505  //Set the necessary flags in the descriptor entry
506  if(txBufferIndex < (SAM7X_ETH_TX_BUFFER_COUNT - 1))
507  {
508  //Write the status word
509  txBufferDesc[txBufferIndex].status = AT91C_EMAC_TX_LAST |
511 
512  //Point to the next buffer
513  txBufferIndex++;
514  }
515  else
516  {
517  //Write the status word
518  txBufferDesc[txBufferIndex].status = AT91C_EMAC_TX_WRAP |
520 
521  //Wrap around
522  txBufferIndex = 0;
523  }
524 
525  //Set the TSTART bit to initiate transmission
526  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
527 
528  //Check whether the next buffer is available for writing
529  if((txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED) != 0)
530  {
531  //The transmitter can accept another packet
532  osSetEvent(&interface->nicTxEvent);
533  }
534 
535  //Successful processing
536  return NO_ERROR;
537 }
538 
539 
540 /**
541  * @brief Receive a packet
542  * @param[in] interface Underlying network interface
543  * @return Error code
544  **/
545 
547 {
548  static uint32_t temp[ETH_MAX_FRAME_SIZE / 4];
549  error_t error;
550  uint_t i;
551  uint_t j;
552  uint_t sofIndex;
553  uint_t eofIndex;
554  size_t n;
555  size_t size;
556  size_t length;
557 
558  //Initialize variables
559  size = 0;
560  sofIndex = UINT_MAX;
561  eofIndex = UINT_MAX;
562 
563  //Search for SOF and EOF flags
564  for(i = 0; i < SAM7X_ETH_RX_BUFFER_COUNT; i++)
565  {
566  //Point to the current entry
567  j = rxBufferIndex + i;
568 
569  //Wrap around to the beginning of the buffer if necessary
571  {
573  }
574 
575  //No more entries to process?
576  if((rxBufferDesc[j].address & AT91C_EMAC_RX_OWNERSHIP) == 0)
577  {
578  //Stop processing
579  break;
580  }
581 
582  //A valid SOF has been found?
583  if((rxBufferDesc[j].status & AT91C_EMAC_RX_SOF) != 0)
584  {
585  //Save the position of the SOF
586  sofIndex = i;
587  }
588 
589  //A valid EOF has been found?
590  if((rxBufferDesc[j].status & AT91C_EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
591  {
592  //Save the position of the EOF
593  eofIndex = i;
594  //Retrieve the length of the frame
595  size = rxBufferDesc[j].status & AT91C_EMAC_RX_LENGTH;
596  //Limit the number of data to read
597  size = MIN(size, ETH_MAX_FRAME_SIZE);
598  //Stop processing since we have reached the end of the frame
599  break;
600  }
601  }
602 
603  //Determine the number of entries to process
604  if(eofIndex != UINT_MAX)
605  {
606  j = eofIndex + 1;
607  }
608  else if(sofIndex != UINT_MAX)
609  {
610  j = sofIndex;
611  }
612  else
613  {
614  j = i;
615  }
616 
617  //Total number of bytes that have been copied from the receive buffer
618  length = 0;
619 
620  //Process incoming frame
621  for(i = 0; i < j; i++)
622  {
623  //Any data to copy from current buffer?
624  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
625  {
626  //Calculate the number of bytes to read at a time
627  n = MIN(size, SAM7X_ETH_RX_BUFFER_SIZE);
628  //Copy data from receive buffer
629  osMemcpy((uint8_t *) temp + length, rxBuffer[rxBufferIndex], n);
630  //Update byte counters
631  length += n;
632  size -= n;
633  }
634 
635  //Mark the current buffer as free
636  rxBufferDesc[rxBufferIndex].address &= ~AT91C_EMAC_RX_OWNERSHIP;
637 
638  //Point to the following entry
639  rxBufferIndex++;
640 
641  //Wrap around to the beginning of the buffer if necessary
642  if(rxBufferIndex >= SAM7X_ETH_RX_BUFFER_COUNT)
643  {
644  rxBufferIndex = 0;
645  }
646  }
647 
648  //Any packet to process?
649  if(length > 0)
650  {
651  NetRxAncillary ancillary;
652 
653  //Additional options can be passed to the stack along with the packet
654  ancillary = NET_DEFAULT_RX_ANCILLARY;
655 
656  //Pass the packet to the upper layer
657  nicProcessPacket(interface, (uint8_t *) temp, length, &ancillary);
658  //Valid packet received
659  error = NO_ERROR;
660  }
661  else
662  {
663  //No more data in the receive buffer
664  error = ERROR_BUFFER_EMPTY;
665  }
666 
667  //Return status code
668  return error;
669 }
670 
671 
672 /**
673  * @brief Configure MAC address filtering
674  * @param[in] interface Underlying network interface
675  * @return Error code
676  **/
677 
679 {
680  uint_t i;
681  uint_t j;
682  uint_t k;
683  uint8_t *p;
684  uint32_t hashTable[2];
685  MacAddr unicastMacAddr[3];
686  MacFilterEntry *entry;
687 
688  //Debug message
689  TRACE_DEBUG("Updating MAC filter...\r\n");
690 
691  //Set the MAC address of the station
692  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
693  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
694 
695  //The MAC supports 3 additional addresses for unicast perfect filtering
696  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
697  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
698  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
699 
700  //The hash table is used for multicast address filtering
701  hashTable[0] = 0;
702  hashTable[1] = 0;
703 
704  //The MAC address filter contains the list of MAC addresses to accept
705  //when receiving an Ethernet frame
706  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
707  {
708  //Point to the current entry
709  entry = &interface->macAddrFilter[i];
710 
711  //Valid entry?
712  if(entry->refCount > 0)
713  {
714  //Multicast address?
715  if(macIsMulticastAddr(&entry->addr))
716  {
717  //Point to the MAC address
718  p = entry->addr.b;
719 
720  //Apply the hash function
721  k = (p[0] >> 6) ^ p[0];
722  k ^= (p[1] >> 4) ^ (p[1] << 2);
723  k ^= (p[2] >> 2) ^ (p[2] << 4);
724  k ^= (p[3] >> 6) ^ p[3];
725  k ^= (p[4] >> 4) ^ (p[4] << 2);
726  k ^= (p[5] >> 2) ^ (p[5] << 4);
727 
728  //The hash value is reduced to a 6-bit index
729  k &= 0x3F;
730 
731  //Update hash table contents
732  hashTable[k / 32] |= (1 << (k % 32));
733  }
734  else
735  {
736  //Up to 3 additional MAC addresses can be specified
737  if(j < 3)
738  {
739  //Save the unicast address
740  unicastMacAddr[j++] = entry->addr;
741  }
742  }
743  }
744  }
745 
746  //Configure the first unicast address filter
747  if(j >= 1)
748  {
749  //The address is activated when SAH register is written
750  AT91C_BASE_EMAC->EMAC_SA2L = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
751  AT91C_BASE_EMAC->EMAC_SA2H = unicastMacAddr[0].w[2];
752  }
753  else
754  {
755  //The address is deactivated when SAL register is written
756  AT91C_BASE_EMAC->EMAC_SA2L = 0;
757  }
758 
759  //Configure the second unicast address filter
760  if(j >= 2)
761  {
762  //The address is activated when SAH register is written
763  AT91C_BASE_EMAC->EMAC_SA3L = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
764  AT91C_BASE_EMAC->EMAC_SA3H = unicastMacAddr[1].w[2];
765  }
766  else
767  {
768  //The address is deactivated when SAL register is written
769  AT91C_BASE_EMAC->EMAC_SA3L = 0;
770  }
771 
772  //Configure the third unicast address filter
773  if(j >= 3)
774  {
775  //The address is activated when SAH register is written
776  AT91C_BASE_EMAC->EMAC_SA4L = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
777  AT91C_BASE_EMAC->EMAC_SA4H = unicastMacAddr[2].w[2];
778  }
779  else
780  {
781  //The address is deactivated when SAL register is written
782  AT91C_BASE_EMAC->EMAC_SA4L = 0;
783  }
784 
785  //Configure the multicast hash table
786  AT91C_BASE_EMAC->EMAC_HRB = hashTable[0];
787  AT91C_BASE_EMAC->EMAC_HRT = hashTable[1];
788 
789  //Debug message
790  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRB);
791  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRT);
792 
793  //Successful processing
794  return NO_ERROR;
795 }
796 
797 
798 /**
799  * @brief Adjust MAC configuration parameters for proper operation
800  * @param[in] interface Underlying network interface
801  * @return Error code
802  **/
803 
805 {
806  uint32_t config;
807 
808  //Read network configuration register
809  config = AT91C_BASE_EMAC->EMAC_NCFGR;
810 
811  //10BASE-T or 100BASE-TX operation mode?
812  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
813  {
814  config |= AT91C_EMAC_SPD;
815  }
816  else
817  {
818  config &= ~AT91C_EMAC_SPD;
819  }
820 
821  //Half-duplex or full-duplex mode?
822  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
823  {
824  config |= AT91C_EMAC_FD;
825  }
826  else
827  {
828  config &= ~AT91C_EMAC_FD;
829  }
830 
831  //Write configuration value back to NCFGR register
832  AT91C_BASE_EMAC->EMAC_NCFGR = config;
833 
834  //Successful processing
835  return NO_ERROR;
836 }
837 
838 
839 /**
840  * @brief Write PHY register
841  * @param[in] opcode Access type (2 bits)
842  * @param[in] phyAddr PHY address (5 bits)
843  * @param[in] regAddr Register address (5 bits)
844  * @param[in] data Register value
845  **/
846 
847 void sam7xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
848  uint8_t regAddr, uint16_t data)
849 {
850  uint32_t temp;
851 
852  //Valid opcode?
853  if(opcode == SMI_OPCODE_WRITE)
854  {
855  //Set up a write operation
857  //PHY address
858  temp |= (phyAddr << 23) & AT91C_EMAC_PHYA;
859  //Register address
860  temp |= (regAddr << 18) & AT91C_EMAC_REGA;
861  //Register value
862  temp |= data & AT91C_EMAC_DATA;
863 
864  //Start a write operation
865  AT91C_BASE_EMAC->EMAC_MAN = temp;
866  //Wait for the write to complete
867  while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0)
868  {
869  }
870  }
871  else
872  {
873  //The MAC peripheral only supports standard Clause 22 opcodes
874  }
875 }
876 
877 
878 /**
879  * @brief Read PHY register
880  * @param[in] opcode Access type (2 bits)
881  * @param[in] phyAddr PHY address (5 bits)
882  * @param[in] regAddr Register address (5 bits)
883  * @return Register value
884  **/
885 
886 uint16_t sam7xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
887  uint8_t regAddr)
888 {
889  uint16_t data;
890  uint32_t temp;
891 
892  //Valid opcode?
893  if(opcode == SMI_OPCODE_READ)
894  {
895  //Set up a read operation
897  //PHY address
898  temp |= (phyAddr << 23) & AT91C_EMAC_PHYA;
899  //Register address
900  temp |= (regAddr << 18) & AT91C_EMAC_REGA;
901 
902  //Start a read operation
903  AT91C_BASE_EMAC->EMAC_MAN = temp;
904  //Wait for the read to complete
905  while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0)
906  {
907  }
908 
909  //Get register value
910  data = AT91C_BASE_EMAC->EMAC_MAN & AT91C_EMAC_DATA;
911  }
912  else
913  {
914  //The MAC peripheral only supports standard Clause 22 opcodes
915  data = 0;
916  }
917 
918  //Return the value of the PHY register
919  return data;
920 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemcpy(dest, src, length)
Definition: os_port.h:141
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
void sam7xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void sam7xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void sam7xEthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t sam7xEthReceivePacket(NetInterface *interface)
Receive a packet.
void sam7xEthEnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t sam7xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
__weak_func void sam7xEthInitGpio(NetInterface *interface)
GPIO configuration.
void sam7xEthIrqHandler(void)
SAM7X Ethernet MAC interrupt service routine.
error_t sam7xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t sam7xEthInit(NetInterface *interface)
SAM7X Ethernet MAC initialization.
error_t sam7xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
const NicDriver sam7xEthDriver
SAM7X Ethernet MAC driver.
error_t sam7xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void sam7xEthTick(NetInterface *interface)
SAM7X Ethernet MAC timer handler.
void sam7xEthEventHandler(NetInterface *interface)
SAM7X Ethernet MAC event handler.
AT91SAM7X Ethernet MAC driver.
#define AT91C_EMAC_RX_EOF
#define AT91C_EMAC_SOF_01
#define AT91C_EMAC_TX_WRAP
#define SAM7X_ETH_RX_BUFFER_COUNT
#define AT91C_EMAC_RW_10
#define AT91C_EMAC_RX_OWNERSHIP
#define AT91C_EMAC_TX_USED
#define AT91C_EMAC_TX_LENGTH
#define AT91C_EMAC_RX_WRAP
#define AT91C_EMAC_RX_SOF
#define AT91C_EMAC_RW_01
void emacIrqWrapper(void)
#define AT91C_EMAC_CODE_10
#define SAM7X_ETH_TX_BUFFER_SIZE
#define AT91C_EMAC_RX_LENGTH
#define SAM7X_ETH_RX_BUFFER_SIZE
#define AT91C_EMAC_TX_LAST
#define AT91C_EMAC_RX_ADDRESS
#define SAM7X_ETH_TX_BUFFER_COUNT
#define AT91C_EMAC_MII_MASK
#define AT91C_BASE_EMAC
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive buffer descriptor.
Transmit buffer descriptor.
uint8_t length
Definition: tcp.h:368