sam7x_eth_driver.c
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1 /**
2  * @file sam7x_eth_driver.c
3  * @brief AT91SAM7X Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "at91sam7x256.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
50 //RX buffer
51 #pragma data_alignment = 8
53 //TX buffer descriptors
54 #pragma data_alignment = 4
55 static Sam7xTxBufferDesc txBufferDesc[SAM7X_ETH_TX_BUFFER_COUNT];
56 //RX buffer descriptors
57 #pragma data_alignment = 4
58 static Sam7xRxBufferDesc rxBufferDesc[SAM7X_ETH_RX_BUFFER_COUNT];
59 
60 //Keil MDK-ARM or GCC compiler?
61 #else
62 
63 //TX buffer
65  __attribute__((aligned(8)));
66 //RX buffer
68  __attribute__((aligned(8)));
69 //TX buffer descriptors
71  __attribute__((aligned(4)));
72 //RX buffer descriptors
74  __attribute__((aligned(4)));
75 
76 #endif
77 
78 //TX buffer index
79 static uint_t txBufferIndex;
80 //RX buffer index
81 static uint_t rxBufferIndex;
82 
83 
84 /**
85  * @brief SAM7X Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  FALSE
106 };
107 
108 
109 /**
110  * @brief SAM7X Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118  volatile uint32_t status;
119 
120  //Debug message
121  TRACE_INFO("Initializing SAM7X Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Enable EMAC peripheral clock
127  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_EMAC);
128 
129  //Disable transmit and receive circuits
130  AT91C_BASE_EMAC->EMAC_NCR = 0;
131 
132  //GPIO configuration
133  sam7xEthInitGpio(interface);
134 
135  //Configure MDC clock speed
136  AT91C_BASE_EMAC->EMAC_NCFGR = AT91C_EMAC_CLK_HCLK_32;
137  //Enable management port (MDC and MDIO)
138  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
139 
140  //PHY transceiver initialization
141  error = interface->phyDriver->init(interface);
142  //Failed to initialize PHY transceiver?
143  if(error)
144  return error;
145 
146  //Set the MAC address of the station
147  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
148  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
149 
150  //The MAC supports 3 additional addresses for unicast perfect filtering
151  AT91C_BASE_EMAC->EMAC_SA2L = 0;
152  AT91C_BASE_EMAC->EMAC_SA3L = 0;
153  AT91C_BASE_EMAC->EMAC_SA4L = 0;
154 
155  //Initialize hash table
156  AT91C_BASE_EMAC->EMAC_HRB = 0;
157  AT91C_BASE_EMAC->EMAC_HRT = 0;
158 
159  //Configure the receive filter
160  AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_BIG | AT91C_EMAC_MTI;
161 
162  //Initialize buffer descriptors
163  sam7xEthInitBufferDesc(interface);
164 
165  //Clear transmit status register
166  AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
167  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR;
168  //Clear receive status register
169  AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA;
170 
171  //First disable all EMAC interrupts
172  AT91C_BASE_EMAC->EMAC_IDR = 0xFFFFFFFF;
173  //Only the desired ones are enabled
174  AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_ROVR | AT91C_EMAC_TCOMP | AT91C_EMAC_TXERR |
175  AT91C_EMAC_RLEX | AT91C_EMAC_TUNDR | AT91C_EMAC_RXUBR | AT91C_EMAC_RCOMP;
176 
177  //Read EMAC ISR register to clear any pending interrupt
178  status = AT91C_BASE_EMAC->EMAC_ISR;
179 
180  //Configure interrupt controller
181  AT91C_BASE_AIC->AIC_SMR[AT91C_ID_EMAC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
182  AT91C_BASE_AIC->AIC_SVR[AT91C_ID_EMAC] = (uint32_t) emacIrqWrapper;
183 
184  //Clear EMAC interrupt flag
185  AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_EMAC);
186 
187  //Enable the EMAC to transmit and receive data
188  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE;
189 
190  //Accept any packets from the upper layer
191  osSetEvent(&interface->nicTxEvent);
192 
193  //Successful initialization
194  return NO_ERROR;
195 }
196 
197 
198 //SAM7-EX256 evaluation board?
199 #if defined(USE_SAM7_EX256)
200 
201 /**
202  * @brief GPIO configuration
203  * @param[in] interface Underlying network interface
204  **/
205 
206 void sam7xEthInitGpio(NetInterface *interface)
207 {
208  //Enable PIO peripheral clock
209  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOB);
210 
211  //Disable pull-up resistors on MII pins
212  AT91C_BASE_PIOB->PIO_PPUDR = AT91C_EMAC_MII_MASK;
213  //Disable interrupts-on-change
214  AT91C_BASE_PIOB->PIO_IDR = AT91C_EMAC_MII_MASK;
215  //Assign MII pins to peripheral A function
216  AT91C_BASE_PIOB->PIO_ASR = AT91C_EMAC_MII_MASK;
217  //Disable the PIO from controlling the corresponding pins
218  AT91C_BASE_PIOB->PIO_PDR = AT91C_EMAC_MII_MASK;
219 
220  //Select MII operation mode and enable transceiver clock
221  AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;
222 }
223 
224 #endif
225 
226 
227 /**
228  * @brief Initialize buffer descriptors
229  * @param[in] interface Underlying network interface
230  **/
231 
233 {
234  uint_t i;
235  uint32_t address;
236 
237  //Initialize TX buffer descriptors
238  for(i = 0; i < SAM7X_ETH_TX_BUFFER_COUNT; i++)
239  {
240  //Calculate the address of the current TX buffer
241  address = (uint32_t) txBuffer[i];
242  //Write the address to the descriptor entry
243  txBufferDesc[i].address = address;
244  //Initialize status field
245  txBufferDesc[i].status = AT91C_EMAC_TX_USED;
246  }
247 
248  //Mark the last descriptor entry with the wrap flag
249  txBufferDesc[i - 1].status |= AT91C_EMAC_TX_WRAP;
250  //Initialize TX buffer index
251  txBufferIndex = 0;
252 
253  //Initialize RX buffer descriptors
254  for(i = 0; i < SAM7X_ETH_RX_BUFFER_COUNT; i++)
255  {
256  //Calculate the address of the current RX buffer
257  address = (uint32_t) rxBuffer[i];
258  //Write the address to the descriptor entry
259  rxBufferDesc[i].address = address & AT91C_EMAC_RX_ADDRESS;
260  //Clear status field
261  rxBufferDesc[i].status = 0;
262  }
263 
264  //Mark the last descriptor entry with the wrap flag
265  rxBufferDesc[i - 1].address |= AT91C_EMAC_RX_WRAP;
266  //Initialize RX buffer index
267  rxBufferIndex = 0;
268 
269  //Start location of the TX descriptor list
270  AT91C_BASE_EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
271  //Start location of the RX descriptor list
272  AT91C_BASE_EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
273 }
274 
275 
276 /**
277  * @brief SAM7X Ethernet MAC timer handler
278  *
279  * This routine is periodically called by the TCP/IP stack to
280  * handle periodic operations such as polling the link state
281  *
282  * @param[in] interface Underlying network interface
283  **/
284 
285 void sam7xEthTick(NetInterface *interface)
286 {
287  //Handle periodic operations
288  interface->phyDriver->tick(interface);
289 }
290 
291 
292 /**
293  * @brief Enable interrupts
294  * @param[in] interface Underlying network interface
295  **/
296 
298 {
299  //Enable Ethernet MAC interrupts
300  AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_EMAC);
301  //Enable Ethernet PHY interrupts
302  interface->phyDriver->enableIrq(interface);
303 }
304 
305 
306 /**
307  * @brief Disable interrupts
308  * @param[in] interface Underlying network interface
309  **/
310 
312 {
313  //Disable Ethernet MAC interrupts
314  AT91C_BASE_AIC->AIC_IDCR = (1 << AT91C_ID_EMAC);
315  //Disable Ethernet PHY interrupts
316  interface->phyDriver->disableIrq(interface);
317 }
318 
319 
320 /**
321  * @brief SAM7X Ethernet MAC interrupt service routine
322  **/
323 
325 {
326  bool_t flag;
327  volatile uint32_t isr;
328  volatile uint32_t tsr;
329  volatile uint32_t rsr;
330 
331  //Interrupt service routine prologue
332  osEnterIsr();
333 
334  //This flag will be set if a higher priority task must be woken
335  flag = FALSE;
336 
337  //Each time the software reads EMAC_ISR, it has to check the contents of
338  //EMAC_TSR, EMAC_RSR and EMAC_NSR (see SAM7X errata 41.3.3.2)
339  isr = AT91C_BASE_EMAC->EMAC_ISR;
340  tsr = AT91C_BASE_EMAC->EMAC_TSR;
341  rsr = AT91C_BASE_EMAC->EMAC_RSR;
342 
343  //A packet has been transmitted?
344  if(tsr & (AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
345  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR))
346  {
347  //Only clear TSR flags that are currently set
348  AT91C_BASE_EMAC->EMAC_TSR = tsr;
349 
350  //Check whether the TX buffer is available for writing
351  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
352  {
353  //Notify the TCP/IP stack that the transmitter is ready to send
354  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
355  }
356  }
357 
358  //A packet has been received?
359  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
360  {
361  //Set event flag
362  nicDriverInterface->nicEvent = TRUE;
363  //Notify the TCP/IP stack of the event
364  flag |= osSetEventFromIsr(&netEvent);
365  }
366 
367  //Write AIC_EOICR register before exiting
368  AT91C_BASE_AIC->AIC_EOICR = 0;
369 
370  //Interrupt service routine epilogue
371  osExitIsr(flag);
372 }
373 
374 
375 /**
376  * @brief SAM7X Ethernet MAC event handler
377  * @param[in] interface Underlying network interface
378  **/
379 
381 {
382  error_t error;
383  uint32_t rsr;
384 
385  //Read receive status
386  rsr = AT91C_BASE_EMAC->EMAC_RSR;
387 
388  //Packet received?
389  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
390  {
391  //Only clear RSR flags that are currently set
392  AT91C_BASE_EMAC->EMAC_RSR = rsr;
393 
394  //Process all pending packets
395  do
396  {
397  //Read incoming packet
398  error = sam7xEthReceivePacket(interface);
399 
400  //No more data in the receive buffer?
401  } while(error != ERROR_BUFFER_EMPTY);
402  }
403 }
404 
405 
406 /**
407  * @brief Send a packet
408  * @param[in] interface Underlying network interface
409  * @param[in] buffer Multi-part buffer containing the data to send
410  * @param[in] offset Offset to the first data byte
411  * @return Error code
412  **/
413 
415  const NetBuffer *buffer, size_t offset)
416 {
417  size_t length;
418 
419  //Retrieve the length of the packet
420  length = netBufferGetLength(buffer) - offset;
421 
422  //Check the frame length
424  {
425  //The transmitter can accept another packet
426  osSetEvent(&interface->nicTxEvent);
427  //Report an error
428  return ERROR_INVALID_LENGTH;
429  }
430 
431  //Make sure the current buffer is available for writing
432  if(!(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED))
433  return ERROR_FAILURE;
434 
435  //Copy user data to the transmit buffer
436  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
437 
438  //Set the necessary flags in the descriptor entry
439  if(txBufferIndex < (SAM7X_ETH_TX_BUFFER_COUNT - 1))
440  {
441  //Write the status word
442  txBufferDesc[txBufferIndex].status =
444 
445  //Point to the next buffer
446  txBufferIndex++;
447  }
448  else
449  {
450  //Write the status word
451  txBufferDesc[txBufferIndex].status = AT91C_EMAC_TX_WRAP |
453 
454  //Wrap around
455  txBufferIndex = 0;
456  }
457 
458  //Set the TSTART bit to initiate transmission
459  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
460 
461  //Check whether the next buffer is available for writing
462  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
463  {
464  //The transmitter can accept another packet
465  osSetEvent(&interface->nicTxEvent);
466  }
467 
468  //Successful processing
469  return NO_ERROR;
470 }
471 
472 
473 /**
474  * @brief Receive a packet
475  * @param[in] interface Underlying network interface
476  * @return Error code
477  **/
478 
480 {
481  static uint8_t temp[ETH_MAX_FRAME_SIZE];
482  error_t error;
483  uint_t i;
484  uint_t j;
485  uint_t sofIndex;
486  uint_t eofIndex;
487  size_t n;
488  size_t size;
489  size_t length;
490 
491  //Initialize SOF and EOF indices
492  sofIndex = UINT_MAX;
493  eofIndex = UINT_MAX;
494 
495  //Search for SOF and EOF flags
496  for(i = 0; i < SAM7X_ETH_RX_BUFFER_COUNT; i++)
497  {
498  //Point to the current entry
499  j = rxBufferIndex + i;
500 
501  //Wrap around to the beginning of the buffer if necessary
504 
505  //No more entries to process?
506  if(!(rxBufferDesc[j].address & AT91C_EMAC_RX_OWNERSHIP))
507  {
508  //Stop processing
509  break;
510  }
511  //A valid SOF has been found?
512  if(rxBufferDesc[j].status & AT91C_EMAC_RX_SOF)
513  {
514  //Save the position of the SOF
515  sofIndex = i;
516  }
517  //A valid EOF has been found?
518  if((rxBufferDesc[j].status & AT91C_EMAC_RX_EOF) && sofIndex != UINT_MAX)
519  {
520  //Save the position of the EOF
521  eofIndex = i;
522  //Retrieve the length of the frame
523  size = rxBufferDesc[j].status & AT91C_EMAC_RX_LENGTH;
524  //Limit the number of data to read
525  size = MIN(size, ETH_MAX_FRAME_SIZE);
526  //Stop processing since we have reached the end of the frame
527  break;
528  }
529  }
530 
531  //Determine the number of entries to process
532  if(eofIndex != UINT_MAX)
533  j = eofIndex + 1;
534  else if(sofIndex != UINT_MAX)
535  j = sofIndex;
536  else
537  j = i;
538 
539  //Total number of bytes that have been copied from the receive buffer
540  length = 0;
541 
542  //Process incoming frame
543  for(i = 0; i < j; i++)
544  {
545  //Any data to copy from current buffer?
546  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
547  {
548  //Calculate the number of bytes to read at a time
549  n = MIN(size, SAM7X_ETH_RX_BUFFER_SIZE);
550  //Copy data from receive buffer
551  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
552  //Update byte counters
553  length += n;
554  size -= n;
555  }
556 
557  //Mark the current buffer as free
558  rxBufferDesc[rxBufferIndex].address &= ~AT91C_EMAC_RX_OWNERSHIP;
559 
560  //Point to the following entry
561  rxBufferIndex++;
562 
563  //Wrap around to the beginning of the buffer if necessary
564  if(rxBufferIndex >= SAM7X_ETH_RX_BUFFER_COUNT)
565  rxBufferIndex = 0;
566  }
567 
568  //Any packet to process?
569  if(length > 0)
570  {
571  //Pass the packet to the upper layer
572  nicProcessPacket(interface, temp, length);
573  //Valid packet received
574  error = NO_ERROR;
575  }
576  else
577  {
578  //No more data in the receive buffer
579  error = ERROR_BUFFER_EMPTY;
580  }
581 
582  //Return status code
583  return error;
584 }
585 
586 
587 /**
588  * @brief Configure MAC address filtering
589  * @param[in] interface Underlying network interface
590  * @return Error code
591  **/
592 
594 {
595  uint_t i;
596  uint_t j;
597  uint_t k;
598  uint8_t *p;
599  uint32_t hashTable[2];
600  MacAddr unicastMacAddr[3];
601  MacFilterEntry *entry;
602 
603  //Debug message
604  TRACE_DEBUG("Updating MAC filter...\r\n");
605 
606  //Set the MAC address of the station
607  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
608  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
609 
610  //The MAC supports 3 additional addresses for unicast perfect filtering
611  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
612  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
613  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
614 
615  //The hash table is used for multicast address filtering
616  hashTable[0] = 0;
617  hashTable[1] = 0;
618 
619  //The MAC address filter contains the list of MAC addresses to accept
620  //when receiving an Ethernet frame
621  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
622  {
623  //Point to the current entry
624  entry = &interface->macAddrFilter[i];
625 
626  //Valid entry?
627  if(entry->refCount > 0)
628  {
629  //Multicast address?
630  if(macIsMulticastAddr(&entry->addr))
631  {
632  //Point to the MAC address
633  p = entry->addr.b;
634 
635  //Apply the hash function
636  k = (p[0] >> 6) ^ p[0];
637  k ^= (p[1] >> 4) ^ (p[1] << 2);
638  k ^= (p[2] >> 2) ^ (p[2] << 4);
639  k ^= (p[3] >> 6) ^ p[3];
640  k ^= (p[4] >> 4) ^ (p[4] << 2);
641  k ^= (p[5] >> 2) ^ (p[5] << 4);
642 
643  //The hash value is reduced to a 6-bit index
644  k &= 0x3F;
645 
646  //Update hash table contents
647  hashTable[k / 32] |= (1 << (k % 32));
648  }
649  else
650  {
651  //Up to 3 additional MAC addresses can be specified
652  if(j < 3)
653  {
654  //Save the unicast address
655  unicastMacAddr[j++] = entry->addr;
656  }
657  }
658  }
659  }
660 
661  //Configure the first unicast address filter
662  if(j >= 1)
663  {
664  //The address is activated when SAH register is written
665  AT91C_BASE_EMAC->EMAC_SA2L = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
666  AT91C_BASE_EMAC->EMAC_SA2H = unicastMacAddr[0].w[2];
667  }
668  else
669  {
670  //The address is deactivated when SAL register is written
671  AT91C_BASE_EMAC->EMAC_SA2L = 0;
672  }
673 
674  //Configure the second unicast address filter
675  if(j >= 2)
676  {
677  //The address is activated when SAH register is written
678  AT91C_BASE_EMAC->EMAC_SA3L = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
679  AT91C_BASE_EMAC->EMAC_SA3H = unicastMacAddr[1].w[2];
680  }
681  else
682  {
683  //The address is deactivated when SAL register is written
684  AT91C_BASE_EMAC->EMAC_SA3L = 0;
685  }
686 
687  //Configure the third unicast address filter
688  if(j >= 3)
689  {
690  //The address is activated when SAH register is written
691  AT91C_BASE_EMAC->EMAC_SA4L = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
692  AT91C_BASE_EMAC->EMAC_SA4H = unicastMacAddr[2].w[2];
693  }
694  else
695  {
696  //The address is deactivated when SAL register is written
697  AT91C_BASE_EMAC->EMAC_SA4L = 0;
698  }
699 
700  //Configure the multicast address filter
701  AT91C_BASE_EMAC->EMAC_HRB = hashTable[0];
702  AT91C_BASE_EMAC->EMAC_HRT = hashTable[1];
703 
704  //Debug message
705  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRB);
706  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRT);
707 
708  //Successful processing
709  return NO_ERROR;
710 }
711 
712 
713 /**
714  * @brief Adjust MAC configuration parameters for proper operation
715  * @param[in] interface Underlying network interface
716  * @return Error code
717  **/
718 
720 {
721  uint32_t config;
722 
723  //Read network configuration register
724  config = AT91C_BASE_EMAC->EMAC_NCFGR;
725 
726  //10BASE-T or 100BASE-TX operation mode?
727  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
728  config |= AT91C_EMAC_SPD;
729  else
730  config &= ~AT91C_EMAC_SPD;
731 
732  //Half-duplex or full-duplex mode?
733  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
734  config |= AT91C_EMAC_FD;
735  else
736  config &= ~AT91C_EMAC_FD;
737 
738  //Write configuration value back to NCFGR register
739  AT91C_BASE_EMAC->EMAC_NCFGR = config;
740 
741  //Successful processing
742  return NO_ERROR;
743 }
744 
745 
746 /**
747  * @brief Write PHY register
748  * @param[in] opcode Access type (2 bits)
749  * @param[in] phyAddr PHY address (5 bits)
750  * @param[in] regAddr Register address (5 bits)
751  * @param[in] data Register value
752  **/
753 
754 void sam7xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
755  uint8_t regAddr, uint16_t data)
756 {
757  uint32_t temp;
758 
759  //Valid opcode?
760  if(opcode == SMI_OPCODE_WRITE)
761  {
762  //Set up a write operation
764  //PHY address
765  temp |= (phyAddr << 23) & AT91C_EMAC_PHYA;
766  //Register address
767  temp |= (regAddr << 18) & AT91C_EMAC_REGA;
768  //Register value
769  temp |= data & AT91C_EMAC_DATA;
770 
771  //Start a write operation
772  AT91C_BASE_EMAC->EMAC_MAN = temp;
773  //Wait for the write to complete
774  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
775  {
776  }
777  }
778  else
779  {
780  //The MAC peripheral only supports standard Clause 22 opcodes
781  }
782 }
783 
784 
785 /**
786  * @brief Read PHY register
787  * @param[in] opcode Access type (2 bits)
788  * @param[in] phyAddr PHY address (5 bits)
789  * @param[in] regAddr Register address (5 bits)
790  * @return Register value
791  **/
792 
793 uint16_t sam7xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
794  uint8_t regAddr)
795 {
796  uint16_t data;
797  uint32_t temp;
798 
799  //Valid opcode?
800  if(opcode == SMI_OPCODE_READ)
801  {
802  //Set up a read operation
804  //PHY address
805  temp |= (phyAddr << 23) & AT91C_EMAC_PHYA;
806  //Register address
807  temp |= (regAddr << 18) & AT91C_EMAC_REGA;
808 
809  //Start a read operation
810  AT91C_BASE_EMAC->EMAC_MAN = temp;
811  //Wait for the read to complete
812  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
813  {
814  }
815 
816  //Get register value
817  data = AT91C_BASE_EMAC->EMAC_MAN & AT91C_EMAC_DATA;
818  }
819  else
820  {
821  //The MAC peripheral only supports standard Clause 22 opcodes
822  data = 0;
823  }
824 
825  //Return the value of the PHY register
826  return data;
827 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void sam7xEthEventHandler(NetInterface *interface)
SAM7X Ethernet MAC event handler.
uint8_t length
Definition: dtls_misc.h:149
AT91SAM7X Ethernet MAC controller.
error_t sam7xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define AT91C_EMAC_CODE_10
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define SAM7X_ETH_TX_BUFFER_COUNT
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define AT91C_EMAC_RX_OWNERSHIP
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define AT91C_EMAC_RW_10
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define AT91C_EMAC_RX_WRAP
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
#define AT91C_EMAC_RX_EOF
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
void emacIrqWrapper(void)
#define SAM7X_ETH_TX_BUFFER_SIZE
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define osExitIsr(flag)
#define SAM7X_ETH_RX_BUFFER_SIZE
void sam7xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define AT91C_EMAC_RW_01
void sam7xEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define FALSE
Definition: os_port.h:46
#define AT91C_EMAC_RX_LENGTH
error_t
Error codes.
Definition: error.h:42
Transmit buffer descriptor.
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
error_t sam7xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define txBuffer
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:222
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
Receive buffer descriptor.
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define AT91C_EMAC_TX_LENGTH
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
void sam7xEthInitGpio(NetInterface *interface)
#define rxBuffer
#define AT91C_EMAC_SOF_01
#define SAM7X_ETH_RX_BUFFER_COUNT
#define AT91C_EMAC_RX_SOF
error_t sam7xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define TRACE_DEBUG(...)
Definition: debug.h:106
error_t sam7xEthInit(NetInterface *interface)
SAM7X Ethernet MAC initialization.
uint16_t regAddr
void sam7xEthTick(NetInterface *interface)
SAM7X Ethernet MAC timer handler.
void sam7xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
void sam7xEthIrqHandler(void)
SAM7X Ethernet MAC interrupt service routine.
uint16_t sam7xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define osEnterIsr()
error_t sam7xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define AT91C_EMAC_TX_LAST
#define AT91C_EMAC_RX_ADDRESS
#define AT91C_EMAC_TX_USED
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void sam7xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
unsigned int uint_t
Definition: compiler_port.h:45
#define AT91C_BASE_EMAC
TCP/IP stack core.
const NicDriver sam7xEthDriver
SAM7X Ethernet MAC driver.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
#define AT91C_EMAC_TX_WRAP
#define AT91C_EMAC_MII_MASK
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
__start_packed struct @108 MacAddr
MAC address.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79