sam7x_eth_driver.c
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1 /**
2  * @file sam7x_eth_driver.c
3  * @brief AT91SAM7X Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "at91sam7x256.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
48 //RX buffer
49 #pragma data_alignment = 8
51 //TX buffer descriptors
52 #pragma data_alignment = 4
53 static Sam7xTxBufferDesc txBufferDesc[SAM7X_ETH_TX_BUFFER_COUNT];
54 //RX buffer descriptors
55 #pragma data_alignment = 4
56 static Sam7xRxBufferDesc rxBufferDesc[SAM7X_ETH_RX_BUFFER_COUNT];
57 
58 //Keil MDK-ARM or GCC compiler?
59 #else
60 
61 //TX buffer
63  __attribute__((aligned(8)));
64 //RX buffer
66  __attribute__((aligned(8)));
67 //TX buffer descriptors
69  __attribute__((aligned(4)));
70 //RX buffer descriptors
72  __attribute__((aligned(4)));
73 
74 #endif
75 
76 //TX buffer index
77 static uint_t txBufferIndex;
78 //RX buffer index
79 static uint_t rxBufferIndex;
80 
81 
82 /**
83  * @brief SAM7X Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  FALSE
104 };
105 
106 
107 /**
108  * @brief SAM7X Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116  volatile uint32_t status;
117 
118  //Debug message
119  TRACE_INFO("Initializing SAM7X Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable EMAC peripheral clock
125  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_EMAC);
126 
127  //GPIO configuration
128  sam7xEthInitGpio(interface);
129 
130  //Configure MDC clock speed
131  AT91C_BASE_EMAC->EMAC_NCFGR = AT91C_EMAC_CLK_HCLK_32;
132  //Enable management port (MDC and MDIO)
133  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
134 
135  //PHY transceiver initialization
136  error = interface->phyDriver->init(interface);
137  //Failed to initialize PHY transceiver?
138  if(error)
139  return error;
140 
141  //Set the MAC address
142  AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
143  AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
144 
145  //Configure the receive filter
146  AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_UNI | AT91C_EMAC_MTI;
147 
148  //Initialize hash table
149  AT91C_BASE_EMAC->EMAC_HRB = 0;
150  AT91C_BASE_EMAC->EMAC_HRT = 0;
151 
152  //Initialize buffer descriptors
153  sam7xEthInitBufferDesc(interface);
154 
155  //Clear transmit status register
156  AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
157  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR;
158  //Clear receive status register
159  AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA;
160 
161  //First disable all EMAC interrupts
162  AT91C_BASE_EMAC->EMAC_IDR = 0xFFFFFFFF;
163  //Only the desired ones are enabled
164  AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_ROVR | AT91C_EMAC_TCOMP | AT91C_EMAC_TXERR |
165  AT91C_EMAC_RLEX | AT91C_EMAC_TUNDR | AT91C_EMAC_RXUBR | AT91C_EMAC_RCOMP;
166 
167  //Read EMAC ISR register to clear any pending interrupt
168  status = AT91C_BASE_EMAC->EMAC_ISR;
169 
170  //Configure interrupt controller
171  AT91C_BASE_AIC->AIC_SMR[AT91C_ID_EMAC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
172  AT91C_BASE_AIC->AIC_SVR[AT91C_ID_EMAC] = (uint32_t) emacIrqWrapper;
173 
174  //Clear EMAC interrupt flag
175  AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_EMAC);
176 
177  //Enable the EMAC to transmit and receive data
178  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE;
179 
180  //Accept any packets from the upper layer
181  osSetEvent(&interface->nicTxEvent);
182 
183  //Successful initialization
184  return NO_ERROR;
185 }
186 
187 
188 //SAM7-EX256 evaluation board?
189 #if defined(USE_SAM7_EX256)
190 
191 /**
192  * @brief GPIO configuration
193  * @param[in] interface Underlying network interface
194  **/
195 
196 void sam7xEthInitGpio(NetInterface *interface)
197 {
198  //Enable PIO peripheral clock
199  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOB);
200 
201  //Disable pull-up resistors on MII pins
202  AT91C_BASE_PIOB->PIO_PPUDR = AT91C_EMAC_MII_MASK;
203  //Disable interrupts-on-change
204  AT91C_BASE_PIOB->PIO_IDR = AT91C_EMAC_MII_MASK;
205  //Assign MII pins to peripheral A function
206  AT91C_BASE_PIOB->PIO_ASR = AT91C_EMAC_MII_MASK;
207  //Disable the PIO from controlling the corresponding pins
208  AT91C_BASE_PIOB->PIO_PDR = AT91C_EMAC_MII_MASK;
209 
210  //Select MII operation mode and enable transceiver clock
211  AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;
212 }
213 
214 #endif
215 
216 
217 /**
218  * @brief Initialize buffer descriptors
219  * @param[in] interface Underlying network interface
220  **/
221 
223 {
224  uint_t i;
225  uint32_t address;
226 
227  //Initialize TX buffer descriptors
228  for(i = 0; i < SAM7X_ETH_TX_BUFFER_COUNT; i++)
229  {
230  //Calculate the address of the current TX buffer
231  address = (uint32_t) txBuffer[i];
232  //Write the address to the descriptor entry
233  txBufferDesc[i].address = address;
234  //Initialize status field
235  txBufferDesc[i].status = AT91C_EMAC_TX_USED;
236  }
237 
238  //Mark the last descriptor entry with the wrap flag
239  txBufferDesc[i - 1].status |= AT91C_EMAC_TX_WRAP;
240  //Initialize TX buffer index
241  txBufferIndex = 0;
242 
243  //Initialize RX buffer descriptors
244  for(i = 0; i < SAM7X_ETH_RX_BUFFER_COUNT; i++)
245  {
246  //Calculate the address of the current RX buffer
247  address = (uint32_t) rxBuffer[i];
248  //Write the address to the descriptor entry
249  rxBufferDesc[i].address = address & AT91C_EMAC_RX_ADDRESS;
250  //Clear status field
251  rxBufferDesc[i].status = 0;
252  }
253 
254  //Mark the last descriptor entry with the wrap flag
255  rxBufferDesc[i - 1].address |= AT91C_EMAC_RX_WRAP;
256  //Initialize RX buffer index
257  rxBufferIndex = 0;
258 
259  //Start location of the TX descriptor list
260  AT91C_BASE_EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
261  //Start location of the RX descriptor list
262  AT91C_BASE_EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
263 }
264 
265 
266 /**
267  * @brief SAM7X Ethernet MAC timer handler
268  *
269  * This routine is periodically called by the TCP/IP stack to
270  * handle periodic operations such as polling the link state
271  *
272  * @param[in] interface Underlying network interface
273  **/
274 
275 void sam7xEthTick(NetInterface *interface)
276 {
277  //Handle periodic operations
278  interface->phyDriver->tick(interface);
279 }
280 
281 
282 /**
283  * @brief Enable interrupts
284  * @param[in] interface Underlying network interface
285  **/
286 
288 {
289  //Enable Ethernet MAC interrupts
290  AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_EMAC);
291  //Enable Ethernet PHY interrupts
292  interface->phyDriver->enableIrq(interface);
293 }
294 
295 
296 /**
297  * @brief Disable interrupts
298  * @param[in] interface Underlying network interface
299  **/
300 
302 {
303  //Disable Ethernet MAC interrupts
304  AT91C_BASE_AIC->AIC_IDCR = (1 << AT91C_ID_EMAC);
305  //Disable Ethernet PHY interrupts
306  interface->phyDriver->disableIrq(interface);
307 }
308 
309 
310 /**
311  * @brief SAM7X Ethernet MAC interrupt service routine
312  **/
313 
315 {
316  bool_t flag;
317  volatile uint32_t isr;
318  volatile uint32_t tsr;
319  volatile uint32_t rsr;
320 
321  //Enter interrupt service routine
322  osEnterIsr();
323 
324  //This flag will be set if a higher priority task must be woken
325  flag = FALSE;
326 
327  //Each time the software reads EMAC_ISR, it has to check the contents of
328  //EMAC_TSR, EMAC_RSR and EMAC_NSR (see SAM7X errata 41.3.3.2)
329  isr = AT91C_BASE_EMAC->EMAC_ISR;
330  tsr = AT91C_BASE_EMAC->EMAC_TSR;
331  rsr = AT91C_BASE_EMAC->EMAC_RSR;
332 
333  //A packet has been transmitted?
334  if(tsr & (AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
335  AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR))
336  {
337  //Only clear TSR flags that are currently set
338  AT91C_BASE_EMAC->EMAC_TSR = tsr;
339 
340  //Check whether the TX buffer is available for writing
341  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
342  {
343  //Notify the TCP/IP stack that the transmitter is ready to send
344  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
345  }
346  }
347 
348  //A packet has been received?
349  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
350  {
351  //Set event flag
352  nicDriverInterface->nicEvent = TRUE;
353  //Notify the TCP/IP stack of the event
354  flag |= osSetEventFromIsr(&netEvent);
355  }
356 
357  //Write AIC_EOICR register before exiting
358  AT91C_BASE_AIC->AIC_EOICR = 0;
359 
360  //Leave interrupt service routine
361  osExitIsr(flag);
362 }
363 
364 
365 /**
366  * @brief SAM7X Ethernet MAC event handler
367  * @param[in] interface Underlying network interface
368  **/
369 
371 {
372  error_t error;
373  uint32_t rsr;
374 
375  //Read receive status
376  rsr = AT91C_BASE_EMAC->EMAC_RSR;
377 
378  //Packet received?
379  if(rsr & (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA))
380  {
381  //Only clear RSR flags that are currently set
382  AT91C_BASE_EMAC->EMAC_RSR = rsr;
383 
384  //Process all pending packets
385  do
386  {
387  //Read incoming packet
388  error = sam7xEthReceivePacket(interface);
389 
390  //No more data in the receive buffer?
391  } while(error != ERROR_BUFFER_EMPTY);
392  }
393 }
394 
395 
396 /**
397  * @brief Send a packet
398  * @param[in] interface Underlying network interface
399  * @param[in] buffer Multi-part buffer containing the data to send
400  * @param[in] offset Offset to the first data byte
401  * @return Error code
402  **/
403 
405  const NetBuffer *buffer, size_t offset)
406 {
407  size_t length;
408 
409  //Retrieve the length of the packet
410  length = netBufferGetLength(buffer) - offset;
411 
412  //Check the frame length
414  {
415  //The transmitter can accept another packet
416  osSetEvent(&interface->nicTxEvent);
417  //Report an error
418  return ERROR_INVALID_LENGTH;
419  }
420 
421  //Make sure the current buffer is available for writing
422  if(!(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED))
423  return ERROR_FAILURE;
424 
425  //Copy user data to the transmit buffer
426  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
427 
428  //Set the necessary flags in the descriptor entry
429  if(txBufferIndex < (SAM7X_ETH_TX_BUFFER_COUNT - 1))
430  {
431  //Write the status word
432  txBufferDesc[txBufferIndex].status =
434 
435  //Point to the next buffer
436  txBufferIndex++;
437  }
438  else
439  {
440  //Write the status word
441  txBufferDesc[txBufferIndex].status = AT91C_EMAC_TX_WRAP |
443 
444  //Wrap around
445  txBufferIndex = 0;
446  }
447 
448  //Set the TSTART bit to initiate transmission
449  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
450 
451  //Check whether the next buffer is available for writing
452  if(txBufferDesc[txBufferIndex].status & AT91C_EMAC_TX_USED)
453  {
454  //The transmitter can accept another packet
455  osSetEvent(&interface->nicTxEvent);
456  }
457 
458  //Successful processing
459  return NO_ERROR;
460 }
461 
462 
463 /**
464  * @brief Receive a packet
465  * @param[in] interface Underlying network interface
466  * @return Error code
467  **/
468 
470 {
471  static uint8_t temp[ETH_MAX_FRAME_SIZE];
472  error_t error;
473  uint_t i;
474  uint_t j;
475  uint_t sofIndex;
476  uint_t eofIndex;
477  size_t n;
478  size_t size;
479  size_t length;
480 
481  //Initialize SOF and EOF indices
482  sofIndex = UINT_MAX;
483  eofIndex = UINT_MAX;
484 
485  //Search for SOF and EOF flags
486  for(i = 0; i < SAM7X_ETH_RX_BUFFER_COUNT; i++)
487  {
488  //Point to the current entry
489  j = rxBufferIndex + i;
490 
491  //Wrap around to the beginning of the buffer if necessary
494 
495  //No more entries to process?
496  if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
497  {
498  //Stop processing
499  break;
500  }
501  //A valid SOF has been found?
502  if(rxBufferDesc[j].status & EMAC_RX_SOF)
503  {
504  //Save the position of the SOF
505  sofIndex = i;
506  }
507  //A valid EOF has been found?
508  if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
509  {
510  //Save the position of the EOF
511  eofIndex = i;
512  //Retrieve the length of the frame
513  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
514  //Limit the number of data to read
515  size = MIN(size, ETH_MAX_FRAME_SIZE);
516  //Stop processing since we have reached the end of the frame
517  break;
518  }
519  }
520 
521  //Determine the number of entries to process
522  if(eofIndex != UINT_MAX)
523  j = eofIndex + 1;
524  else if(sofIndex != UINT_MAX)
525  j = sofIndex;
526  else
527  j = i;
528 
529  //Total number of bytes that have been copied from the receive buffer
530  length = 0;
531 
532  //Process incoming frame
533  for(i = 0; i < j; i++)
534  {
535  //Any data to copy from current buffer?
536  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
537  {
538  //Calculate the number of bytes to read at a time
539  n = MIN(size, SAM7X_ETH_RX_BUFFER_SIZE);
540  //Copy data from receive buffer
541  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
542  //Update byte counters
543  length += n;
544  size -= n;
545  }
546 
547  //Mark the current buffer as free
548  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
549 
550  //Point to the following entry
551  rxBufferIndex++;
552 
553  //Wrap around to the beginning of the buffer if necessary
554  if(rxBufferIndex >= SAM7X_ETH_RX_BUFFER_COUNT)
555  rxBufferIndex = 0;
556  }
557 
558  //Any packet to process?
559  if(length > 0)
560  {
561  //Pass the packet to the upper layer
562  nicProcessPacket(interface, temp, length);
563  //Valid packet received
564  error = NO_ERROR;
565  }
566  else
567  {
568  //No more data in the receive buffer
569  error = ERROR_BUFFER_EMPTY;
570  }
571 
572  //Return status code
573  return error;
574 }
575 
576 
577 /**
578  * @brief Configure MAC address filtering
579  * @param[in] interface Underlying network interface
580  * @return Error code
581  **/
582 
584 {
585  uint_t i;
586  uint_t k;
587  uint8_t *p;
588  uint32_t hashTable[2];
589  MacFilterEntry *entry;
590 
591  //Debug message
592  TRACE_DEBUG("Updating SAM7X hash table...\r\n");
593 
594  //Clear hash table
595  hashTable[0] = 0;
596  hashTable[1] = 0;
597 
598  //The MAC address filter contains the list of MAC addresses to accept
599  //when receiving an Ethernet frame
600  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
601  {
602  //Point to the current entry
603  entry = &interface->macAddrFilter[i];
604 
605  //Valid entry?
606  if(entry->refCount > 0)
607  {
608  //Point to the MAC address
609  p = entry->addr.b;
610 
611  //Apply the hash function
612  k = (p[0] >> 6) ^ p[0];
613  k ^= (p[1] >> 4) ^ (p[1] << 2);
614  k ^= (p[2] >> 2) ^ (p[2] << 4);
615  k ^= (p[3] >> 6) ^ p[3];
616  k ^= (p[4] >> 4) ^ (p[4] << 2);
617  k ^= (p[5] >> 2) ^ (p[5] << 4);
618 
619  //The hash value is reduced to a 6-bit index
620  k &= 0x3F;
621 
622  //Update hash table contents
623  hashTable[k / 32] |= (1 << (k % 32));
624  }
625  }
626 
627  //Write the hash table
628  AT91C_BASE_EMAC->EMAC_HRB = hashTable[0];
629  AT91C_BASE_EMAC->EMAC_HRT = hashTable[1];
630 
631  //Debug message
632  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRB);
633  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AT91C_BASE_EMAC->EMAC_HRT);
634 
635  //Successful processing
636  return NO_ERROR;
637 }
638 
639 
640 /**
641  * @brief Adjust MAC configuration parameters for proper operation
642  * @param[in] interface Underlying network interface
643  * @return Error code
644  **/
645 
647 {
648  uint32_t config;
649 
650  //Read network configuration register
651  config = AT91C_BASE_EMAC->EMAC_NCFGR;
652 
653  //10BASE-T or 100BASE-TX operation mode?
654  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
655  config |= AT91C_EMAC_SPD;
656  else
657  config &= ~AT91C_EMAC_SPD;
658 
659  //Half-duplex or full-duplex mode?
660  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
661  config |= AT91C_EMAC_FD;
662  else
663  config &= ~AT91C_EMAC_FD;
664 
665  //Write configuration value back to NCFGR register
666  AT91C_BASE_EMAC->EMAC_NCFGR = config;
667 
668  //Successful processing
669  return NO_ERROR;
670 }
671 
672 
673 /**
674  * @brief Write PHY register
675  * @param[in] phyAddr PHY address
676  * @param[in] regAddr Register address
677  * @param[in] data Register value
678  **/
679 
680 void sam7xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
681 {
682  uint32_t value;
683 
684  //Set up a write operation
686  //PHY address
687  value |= (phyAddr << 23) & AT91C_EMAC_PHYA;
688  //Register address
689  value |= (regAddr << 18) & AT91C_EMAC_REGA;
690  //Register value
691  value |= data & AT91C_EMAC_DATA;
692 
693  //Start a write operation
694  AT91C_BASE_EMAC->EMAC_MAN = value;
695  //Wait for the write to complete
696  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
697 }
698 
699 
700 /**
701  * @brief Read PHY register
702  * @param[in] phyAddr PHY address
703  * @param[in] regAddr Register address
704  * @return Register value
705  **/
706 
707 uint16_t sam7xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
708 {
709  uint32_t value;
710 
711  //Set up a read operation
713  //PHY address
714  value |= (phyAddr << 23) & AT91C_EMAC_PHYA;
715  //Register address
716  value |= (regAddr << 18) & AT91C_EMAC_REGA;
717 
718  //Start a read operation
719  AT91C_BASE_EMAC->EMAC_MAN = value;
720  //Wait for the read to complete
721  while(!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
722 
723  //Return PHY register contents
724  return AT91C_BASE_EMAC->EMAC_MAN & AT91C_EMAC_DATA;
725 }
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
TCP/IP stack core.
error_t sam7xEthReceivePacket(NetInterface *interface)
Receive a packet.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define AT91C_EMAC_TX_USED
#define EMAC_RX_SOF
const NicDriver sam7xEthDriver
SAM7X Ethernet MAC driver.
Generic error code.
Definition: error.h:43
#define txBuffer
Transmit buffer descriptor.
#define AT91C_BASE_EMAC
error_t sam7xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive buffer descriptor.
#define AT91C_EMAC_TX_WRAP
#define SAM7X_ETH_TX_BUFFER_COUNT
void sam7xEthInitGpio(NetInterface *interface)
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
void sam7xEthEventHandler(NetInterface *interface)
SAM7X Ethernet MAC event handler.
#define AT91C_EMAC_RW_10
#define AT91C_EMAC_CODE_10
#define AT91C_EMAC_RX_WRAP
#define AT91C_EMAC_TX_LAST
#define AT91C_EMAC_RX_ADDRESS
#define EMAC_RX_EOF
void sam7xEthIrqHandler(void)
SAM7X Ethernet MAC interrupt service routine.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
void emacIrqWrapper(void)
NIC driver.
Definition: nic.h:161
#define EMAC_RX_LENGTH
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void sam7xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MIN(a, b)
Definition: os_port.h:60
#define AT91C_EMAC_RW_01
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void sam7xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void sam7xEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define SAM7X_ETH_TX_BUFFER_SIZE
#define SAM7X_ETH_RX_BUFFER_SIZE
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
Ipv6Addr address
error_t sam7xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define AT91C_EMAC_MII_MASK
error_t sam7xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
AT91SAM7X Ethernet MAC controller.
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define AT91C_EMAC_TX_LENGTH
#define osExitIsr(flag)
#define EMAC_RX_OWNERSHIP
#define osEnterIsr()
uint16_t sam7xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
error_t sam7xEthInit(NetInterface *interface)
SAM7X Ethernet MAC initialization.
#define AT91C_EMAC_SOF_01
int bool_t
Definition: compiler_port.h:47
void sam7xEthTick(NetInterface *interface)
SAM7X Ethernet MAC timer handler.
void sam7xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define SAM7X_ETH_RX_BUFFER_COUNT
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98