sama5d3_eth_driver.c
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1 /**
2  * @file sama5d3_eth_driver.c
3  * @brief SAMA5D3 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "sama5d3x.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
49 #pragma location = SAMA5D3_ETH_RAM_SECTION
51 //RX buffer
52 #pragma data_alignment = 8
53 #pragma location = SAMA5D3_ETH_RAM_SECTION
55 //TX buffer descriptors
56 #pragma data_alignment = 8
57 #pragma location = SAMA5D3_ETH_RAM_SECTION
59 //RX buffer descriptors
60 #pragma data_alignment = 8
61 #pragma location = SAMA5D3_ETH_RAM_SECTION
63 
64 //GCC compiler?
65 #else
66 
67 //TX buffer
69  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
70 //RX buffer
72  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
73 //TX buffer descriptors
75  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
76 //RX buffer descriptors
78  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
79 
80 #endif
81 
82 //TX buffer index
83 static uint_t txBufferIndex;
84 //RX buffer index
85 static uint_t rxBufferIndex;
86 
87 
88 /**
89  * @brief SAMA5D3 Ethernet MAC driver
90  **/
91 
93 {
95  ETH_MTU,
106  TRUE,
107  TRUE,
108  TRUE,
109  FALSE
110 };
111 
112 
113 /**
114  * @brief SAMA5D3 Ethernet MAC initialization
115  * @param[in] interface Underlying network interface
116  * @return Error code
117  **/
118 
120 {
121  error_t error;
122  volatile uint32_t status;
123 
124  //Debug message
125  TRACE_INFO("Initializing SAMA5D3 Ethernet MAC...\r\n");
126 
127  //Save underlying network interface
128  nicDriverInterface = interface;
129 
130  //Enable EMAC peripheral clock
131  PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
132  //Enable IRQ controller peripheral clock
133  PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
134 
135  //Disable transmit and receive circuits
136  EMAC->EMAC_NCR = 0;
137 
138  //GPIO configuration
139  sama5d3EthInitGpio(interface);
140 
141  //Configure MDC clock speed
142  EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
143  //Enable management port (MDC and MDIO)
144  EMAC->EMAC_NCR |= EMAC_NCR_MPE;
145 
146  //Valid Ethernet PHY or switch driver?
147  if(interface->phyDriver != NULL)
148  {
149  //Ethernet PHY initialization
150  error = interface->phyDriver->init(interface);
151  }
152  else if(interface->switchDriver != NULL)
153  {
154  //Ethernet switch initialization
155  error = interface->switchDriver->init(interface);
156  }
157  else
158  {
159  //The interface is not properly configured
160  error = ERROR_FAILURE;
161  }
162 
163  //Any error to report?
164  if(error)
165  {
166  return error;
167  }
168 
169  //Set the MAC address of the station
170  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
172 
173  //The MAC supports 3 additional addresses for unicast perfect filtering
174  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
175  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
176  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
177 
178  //Initialize hash table
179  EMAC->EMAC_HRB = 0;
180  EMAC->EMAC_HRT = 0;
181 
182  //Configure the receive filter
183  EMAC->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
184 
185  //Initialize buffer descriptors
186  sama5d3EthInitBufferDesc(interface);
187 
188  //Clear transmit status register
189  EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
190  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
191  //Clear receive status register
192  EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
193 
194  //First disable all EMAC interrupts
195  EMAC->EMAC_IDR = 0xFFFFFFFF;
196  //Only the desired ones are enabled
197  EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
198  EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
199 
200  //Read EMAC ISR register to clear any pending interrupt
201  status = EMAC->EMAC_ISR;
202 
203  //Configure interrupt controller
204  AIC->AIC_SSR = ID_EMAC;
205  AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_ETH_IRQ_PRIORITY);
206  AIC->AIC_SVR = (uint32_t) sama5d3EthIrqHandler;
207 
208  //Enable the EMAC to transmit and receive data
209  EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
210 
211  //Accept any packets from the upper layer
212  osSetEvent(&interface->nicTxEvent);
213 
214  //Successful initialization
215  return NO_ERROR;
216 }
217 
218 
219 //SAMA5D3-Xplained or SAMA5D3-EDS evaluation board?
220 #if defined(USE_SAMA5D3_XPLAINED) || defined(USE_SAMA5D3_EDS)
221 
222 /**
223  * @brief GPIO configuration
224  * @param[in] interface Underlying network interface
225  **/
226 
227 void sama5d3EthInitGpio(NetInterface *interface)
228 {
229  //Enable PIO peripheral clock
230  PMC->PMC_PCER0 = (1 << ID_PIOC);
231 
232  //Disable pull-up resistors on RMII pins
233  PIOC->PIO_PUDR = EMAC_RMII_MASK;
234  //Disable interrupts-on-change
235  PIOC->PIO_IDR = EMAC_RMII_MASK;
236  //Assign RMII pins to peripheral A function
237  PIOC->PIO_ABCDSR[0] &= ~EMAC_RMII_MASK;
238  PIOC->PIO_ABCDSR[1] &= ~EMAC_RMII_MASK;
239  //Disable the PIO from controlling the corresponding pins
240  PIOC->PIO_PDR = EMAC_RMII_MASK;
241 
242  //Select RMII operation mode and enable transceiver clock
243  EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
244 }
245 
246 #endif
247 
248 
249 /**
250  * @brief Initialize buffer descriptors
251  * @param[in] interface Underlying network interface
252  **/
253 
255 {
256  uint_t i;
257  uint32_t address;
258 
259  //Initialize TX buffer descriptors
260  for(i = 0; i < SAMA5D3_ETH_TX_BUFFER_COUNT; i++)
261  {
262  //Calculate the address of the current TX buffer
263  address = (uint32_t) txBuffer[i];
264  //Write the address to the descriptor entry
265  txBufferDesc[i].address = address;
266  //Initialize status field
267  txBufferDesc[i].status = EMAC_TX_USED;
268  }
269 
270  //Mark the last descriptor entry with the wrap flag
271  txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
272  //Initialize TX buffer index
273  txBufferIndex = 0;
274 
275  //Initialize RX buffer descriptors
276  for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
277  {
278  //Calculate the address of the current RX buffer
279  address = (uint32_t) rxBuffer[i];
280  //Write the address to the descriptor entry
281  rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
282  //Clear status field
283  rxBufferDesc[i].status = 0;
284  }
285 
286  //Mark the last descriptor entry with the wrap flag
287  rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
288  //Initialize RX buffer index
289  rxBufferIndex = 0;
290 
291  //Start location of the TX descriptor list
292  EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
293  //Start location of the RX descriptor list
294  EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
295 }
296 
297 
298 /**
299  * @brief SAMA5D3 Ethernet MAC timer handler
300  *
301  * This routine is periodically called by the TCP/IP stack to handle periodic
302  * operations such as polling the link state
303  *
304  * @param[in] interface Underlying network interface
305  **/
306 
307 void sama5d3EthTick(NetInterface *interface)
308 {
309  //Valid Ethernet PHY or switch driver?
310  if(interface->phyDriver != NULL)
311  {
312  //Handle periodic operations
313  interface->phyDriver->tick(interface);
314  }
315  else if(interface->switchDriver != NULL)
316  {
317  //Handle periodic operations
318  interface->switchDriver->tick(interface);
319  }
320  else
321  {
322  //Just for sanity
323  }
324 }
325 
326 
327 /**
328  * @brief Enable interrupts
329  * @param[in] interface Underlying network interface
330  **/
331 
333 {
334  //Enable Ethernet MAC interrupts
335  AIC->AIC_SSR = ID_EMAC;
336  AIC->AIC_IECR = AIC_IECR_INTEN;
337 
338 
339  //Valid Ethernet PHY or switch driver?
340  if(interface->phyDriver != NULL)
341  {
342  //Enable Ethernet PHY interrupts
343  interface->phyDriver->enableIrq(interface);
344  }
345  else if(interface->switchDriver != NULL)
346  {
347  //Enable Ethernet switch interrupts
348  interface->switchDriver->enableIrq(interface);
349  }
350  else
351  {
352  //Just for sanity
353  }
354 }
355 
356 
357 /**
358  * @brief Disable interrupts
359  * @param[in] interface Underlying network interface
360  **/
361 
363 {
364  //Disable Ethernet MAC interrupts
365  AIC->AIC_SSR = ID_EMAC;
366  AIC->AIC_IDCR = AIC_IDCR_INTD;
367 
368 
369  //Valid Ethernet PHY or switch driver?
370  if(interface->phyDriver != NULL)
371  {
372  //Disable Ethernet PHY interrupts
373  interface->phyDriver->disableIrq(interface);
374  }
375  else if(interface->switchDriver != NULL)
376  {
377  //Disable Ethernet switch interrupts
378  interface->switchDriver->disableIrq(interface);
379  }
380  else
381  {
382  //Just for sanity
383  }
384 }
385 
386 
387 /**
388  * @brief SAMA5D3 Ethernet MAC interrupt service routine
389  **/
390 
392 {
393  bool_t flag;
394  volatile uint32_t isr;
395  volatile uint32_t tsr;
396  volatile uint32_t rsr;
397 
398  //Interrupt service routine prologue
399  osEnterIsr();
400 
401  //This flag will be set if a higher priority task must be woken
402  flag = FALSE;
403 
404  //Each time the software reads EMAC_ISR, it has to check the
405  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
406  isr = EMAC->EMAC_ISR;
407  tsr = EMAC->EMAC_TSR;
408  rsr = EMAC->EMAC_RSR;
409 
410  //Packet transmitted?
411  if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
412  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
413  {
414  //Only clear TSR flags that are currently set
415  EMAC->EMAC_TSR = tsr;
416 
417  //Check whether the TX buffer is available for writing
418  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
419  {
420  //Notify the TCP/IP stack that the transmitter is ready to send
421  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
422  }
423  }
424 
425  //Packet received?
426  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
427  {
428  //Set event flag
429  nicDriverInterface->nicEvent = TRUE;
430  //Notify the TCP/IP stack of the event
431  flag |= osSetEventFromIsr(&netEvent);
432  }
433 
434  //Write AIC_EOICR register before exiting
435  AIC->AIC_EOICR = 0;
436 
437  //Interrupt service routine epilogue
438  osExitIsr(flag);
439 }
440 
441 
442 /**
443  * @brief SAMA5D3 Ethernet MAC event handler
444  * @param[in] interface Underlying network interface
445  **/
446 
448 {
449  error_t error;
450  uint32_t rsr;
451 
452  //Read receive status
453  rsr = EMAC->EMAC_RSR;
454 
455  //Packet received?
456  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
457  {
458  //Only clear RSR flags that are currently set
459  EMAC->EMAC_RSR = rsr;
460 
461  //Process all pending packets
462  do
463  {
464  //Read incoming packet
465  error = sama5d3EthReceivePacket(interface);
466 
467  //No more data in the receive buffer?
468  } while(error != ERROR_BUFFER_EMPTY);
469  }
470 }
471 
472 
473 /**
474  * @brief Send a packet
475  * @param[in] interface Underlying network interface
476  * @param[in] buffer Multi-part buffer containing the data to send
477  * @param[in] offset Offset to the first data byte
478  * @param[in] ancillary Additional options passed to the stack along with
479  * the packet
480  * @return Error code
481  **/
482 
484  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
485 {
486  size_t length;
487 
488  //Retrieve the length of the packet
489  length = netBufferGetLength(buffer) - offset;
490 
491  //Check the frame length
493  {
494  //The transmitter can accept another packet
495  osSetEvent(&interface->nicTxEvent);
496  //Report an error
497  return ERROR_INVALID_LENGTH;
498  }
499 
500  //Make sure the current buffer is available for writing
501  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) == 0)
502  {
503  return ERROR_FAILURE;
504  }
505 
506  //Copy user data to the transmit buffer
507  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
508 
509  //Set the necessary flags in the descriptor entry
510  if(txBufferIndex < (SAMA5D3_ETH_TX_BUFFER_COUNT - 1))
511  {
512  //Write the status word
513  txBufferDesc[txBufferIndex].status = EMAC_TX_LAST |
515 
516  //Point to the next buffer
517  txBufferIndex++;
518  }
519  else
520  {
521  //Write the status word
522  txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP | EMAC_TX_LAST |
524 
525  //Wrap around
526  txBufferIndex = 0;
527  }
528 
529  //Set the TSTART bit to initiate transmission
530  EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
531 
532  //Check whether the next buffer is available for writing
533  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
534  {
535  //The transmitter can accept another packet
536  osSetEvent(&interface->nicTxEvent);
537  }
538 
539  //Successful processing
540  return NO_ERROR;
541 }
542 
543 
544 /**
545  * @brief Receive a packet
546  * @param[in] interface Underlying network interface
547  * @return Error code
548  **/
549 
551 {
552  static uint8_t temp[ETH_MAX_FRAME_SIZE];
553  error_t error;
554  uint_t i;
555  uint_t j;
556  uint_t sofIndex;
557  uint_t eofIndex;
558  size_t n;
559  size_t size;
560  size_t length;
561 
562  //Initialize SOF and EOF indices
563  sofIndex = UINT_MAX;
564  eofIndex = UINT_MAX;
565 
566  //Search for SOF and EOF flags
567  for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
568  {
569  //Point to the current entry
570  j = rxBufferIndex + i;
571 
572  //Wrap around to the beginning of the buffer if necessary
574  {
576  }
577 
578  //No more entries to process?
579  if((rxBufferDesc[j].address & EMAC_RX_OWNERSHIP) == 0)
580  {
581  //Stop processing
582  break;
583  }
584 
585  //A valid SOF has been found?
586  if((rxBufferDesc[j].status & EMAC_RX_SOF) != 0)
587  {
588  //Save the position of the SOF
589  sofIndex = i;
590  }
591 
592  //A valid EOF has been found?
593  if((rxBufferDesc[j].status & EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
594  {
595  //Save the position of the EOF
596  eofIndex = i;
597  //Retrieve the length of the frame
598  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
599  //Limit the number of data to read
600  size = MIN(size, ETH_MAX_FRAME_SIZE);
601  //Stop processing since we have reached the end of the frame
602  break;
603  }
604  }
605 
606  //Determine the number of entries to process
607  if(eofIndex != UINT_MAX)
608  {
609  j = eofIndex + 1;
610  }
611  else if(sofIndex != UINT_MAX)
612  {
613  j = sofIndex;
614  }
615  else
616  {
617  j = i;
618  }
619 
620  //Total number of bytes that have been copied from the receive buffer
621  length = 0;
622 
623  //Process incoming frame
624  for(i = 0; i < j; i++)
625  {
626  //Any data to copy from current buffer?
627  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
628  {
629  //Calculate the number of bytes to read at a time
631  //Copy data from receive buffer
632  osMemcpy(temp + length, rxBuffer[rxBufferIndex], n);
633  //Update byte counters
634  length += n;
635  size -= n;
636  }
637 
638  //Mark the current buffer as free
639  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
640 
641  //Point to the following entry
642  rxBufferIndex++;
643 
644  //Wrap around to the beginning of the buffer if necessary
645  if(rxBufferIndex >= SAMA5D3_ETH_RX_BUFFER_COUNT)
646  {
647  rxBufferIndex = 0;
648  }
649  }
650 
651  //Any packet to process?
652  if(length > 0)
653  {
654  NetRxAncillary ancillary;
655 
656  //Additional options can be passed to the stack along with the packet
657  ancillary = NET_DEFAULT_RX_ANCILLARY;
658 
659  //Pass the packet to the upper layer
660  nicProcessPacket(interface, temp, length, &ancillary);
661  //Valid packet received
662  error = NO_ERROR;
663  }
664  else
665  {
666  //No more data in the receive buffer
667  error = ERROR_BUFFER_EMPTY;
668  }
669 
670  //Return status code
671  return error;
672 }
673 
674 
675 /**
676  * @brief Configure MAC address filtering
677  * @param[in] interface Underlying network interface
678  * @return Error code
679  **/
680 
682 {
683  uint_t i;
684  uint_t j;
685  uint_t k;
686  uint8_t *p;
687  uint32_t hashTable[2];
688  MacAddr unicastMacAddr[3];
689  MacFilterEntry *entry;
690 
691  //Debug message
692  TRACE_DEBUG("Updating MAC filter...\r\n");
693 
694  //Set the MAC address of the station
695  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
696  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
697 
698  //The MAC supports 3 additional addresses for unicast perfect filtering
699  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
700  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
701  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
702 
703  //The hash table is used for multicast address filtering
704  hashTable[0] = 0;
705  hashTable[1] = 0;
706 
707  //The MAC address filter contains the list of MAC addresses to accept
708  //when receiving an Ethernet frame
709  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
710  {
711  //Point to the current entry
712  entry = &interface->macAddrFilter[i];
713 
714  //Valid entry?
715  if(entry->refCount > 0)
716  {
717  //Multicast address?
718  if(macIsMulticastAddr(&entry->addr))
719  {
720  //Point to the MAC address
721  p = entry->addr.b;
722 
723  //Apply the hash function
724  k = (p[0] >> 6) ^ p[0];
725  k ^= (p[1] >> 4) ^ (p[1] << 2);
726  k ^= (p[2] >> 2) ^ (p[2] << 4);
727  k ^= (p[3] >> 6) ^ p[3];
728  k ^= (p[4] >> 4) ^ (p[4] << 2);
729  k ^= (p[5] >> 2) ^ (p[5] << 4);
730 
731  //The hash value is reduced to a 6-bit index
732  k &= 0x3F;
733 
734  //Update hash table contents
735  hashTable[k / 32] |= (1 << (k % 32));
736  }
737  else
738  {
739  //Up to 3 additional MAC addresses can be specified
740  if(j < 3)
741  {
742  //Save the unicast address
743  unicastMacAddr[j] = entry->addr;
744  }
745  else
746  {
747  //Point to the MAC address
748  p = entry->addr.b;
749 
750  //Apply the hash function
751  k = (p[0] >> 6) ^ p[0];
752  k ^= (p[1] >> 4) ^ (p[1] << 2);
753  k ^= (p[2] >> 2) ^ (p[2] << 4);
754  k ^= (p[3] >> 6) ^ p[3];
755  k ^= (p[4] >> 4) ^ (p[4] << 2);
756  k ^= (p[5] >> 2) ^ (p[5] << 4);
757 
758  //The hash value is reduced to a 6-bit index
759  k &= 0x3F;
760 
761  //Update hash table contents
762  hashTable[k / 32] |= (1 << (k % 32));
763  }
764 
765  //Increment the number of unicast addresses
766  j++;
767  }
768  }
769  }
770 
771  //Configure the first unicast address filter
772  if(j >= 1)
773  {
774  //The address is activated when SAT register is written
775  EMAC->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
776  EMAC->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
777  }
778  else
779  {
780  //The address is deactivated when SAB register is written
781  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
782  }
783 
784  //Configure the second unicast address filter
785  if(j >= 2)
786  {
787  //The address is activated when SAT register is written
788  EMAC->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
789  EMAC->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
790  }
791  else
792  {
793  //The address is deactivated when SAB register is written
794  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
795  }
796 
797  //Configure the third unicast address filter
798  if(j >= 3)
799  {
800  //The address is activated when SAT register is written
801  EMAC->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
802  EMAC->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
803  }
804  else
805  {
806  //The address is deactivated when SAB register is written
807  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
808  }
809 
810  //The perfect MAC filter supports only 3 unicast addresses
811  if(j >= 4)
812  {
813  EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI;
814  }
815  else
816  {
817  EMAC->EMAC_NCFGR &= ~EMAC_NCFGR_UNI;
818  }
819 
820  //Configure the multicast address filter
821  EMAC->EMAC_HRB = hashTable[0];
822  EMAC->EMAC_HRT = hashTable[1];
823 
824  //Debug message
825  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
826  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
827 
828  //Successful processing
829  return NO_ERROR;
830 }
831 
832 
833 /**
834  * @brief Adjust MAC configuration parameters for proper operation
835  * @param[in] interface Underlying network interface
836  * @return Error code
837  **/
838 
840 {
841  uint32_t config;
842 
843  //Read network configuration register
844  config = EMAC->EMAC_NCFGR;
845 
846  //10BASE-T or 100BASE-TX operation mode?
847  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
848  {
849  config |= EMAC_NCFGR_SPD;
850  }
851  else
852  {
853  config &= ~EMAC_NCFGR_SPD;
854  }
855 
856  //Half-duplex or full-duplex mode?
857  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
858  {
859  config |= EMAC_NCFGR_FD;
860  }
861  else
862  {
863  config &= ~EMAC_NCFGR_FD;
864  }
865 
866  //Write configuration value back to NCFGR register
867  EMAC->EMAC_NCFGR = config;
868 
869  //Successful processing
870  return NO_ERROR;
871 }
872 
873 
874 /**
875  * @brief Write PHY register
876  * @param[in] opcode Access type (2 bits)
877  * @param[in] phyAddr PHY address (5 bits)
878  * @param[in] regAddr Register address (5 bits)
879  * @param[in] data Register value
880  **/
881 
882 void sama5d3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
883  uint8_t regAddr, uint16_t data)
884 {
885  uint32_t temp;
886 
887  //Valid opcode?
888  if(opcode == SMI_OPCODE_WRITE)
889  {
890  //Set up a write operation
891  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
892  //PHY address
893  temp |= EMAC_MAN_PHYA(phyAddr);
894  //Register address
895  temp |= EMAC_MAN_REGA(regAddr);
896  //Register value
897  temp |= EMAC_MAN_DATA(data);
898 
899  //Start a write operation
900  EMAC->EMAC_MAN = temp;
901  //Wait for the write to complete
902  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
903  {
904  }
905  }
906  else
907  {
908  //The MAC peripheral only supports standard Clause 22 opcodes
909  }
910 }
911 
912 
913 /**
914  * @brief Read PHY register
915  * @param[in] opcode Access type (2 bits)
916  * @param[in] phyAddr PHY address (5 bits)
917  * @param[in] regAddr Register address (5 bits)
918  * @return Register value
919  **/
920 
921 uint16_t sama5d3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
922  uint8_t regAddr)
923 {
924  uint16_t data;
925  uint32_t temp;
926 
927  //Valid opcode?
928  if(opcode == SMI_OPCODE_READ)
929  {
930  //Set up a read operation
931  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
932  //PHY address
933  temp |= EMAC_MAN_PHYA(phyAddr);
934  //Register address
935  temp |= EMAC_MAN_REGA(regAddr);
936 
937  //Start a read operation
938  EMAC->EMAC_MAN = temp;
939  //Wait for the read to complete
940  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
941  {
942  }
943 
944  //Get register value
945  data = EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
946  }
947  else
948  {
949  //The MAC peripheral only supports standard Clause 22 opcodes
950  data = 0;
951  }
952 
953  //Return the value of the PHY register
954  return data;
955 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
error_t sama5d3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t sama5d3EthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void sama5d3EthEventHandler(NetInterface *interface)
SAMA5D3 Ethernet MAC event handler.
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define EMAC_RX_WRAP
#define TRUE
Definition: os_port.h:50
error_t sama5d3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:103
__start_packed struct @5 MacAddr
MAC address.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define EMAC_RX_EOF
#define EMAC_RX_OWNERSHIP
#define SAMA5D3_ETH_RX_BUFFER_COUNT
#define SAMA5D3_ETH_RAM_SECTION
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:124
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define EMAC_RX_LENGTH
#define SAMA5D3_ETH_TX_BUFFER_SIZE
void sama5d3EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define SAMA5D3_ETH_TX_BUFFER_COUNT
#define FALSE
Definition: os_port.h:46
void sama5d3EthTick(NetInterface *interface)
SAMA5D3 Ethernet MAC timer handler.
#define osMemcpy(dest, src, length)
Definition: os_port.h:134
#define EMAC_TX_LENGTH
uint16_t sama5d3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t
Error codes.
Definition: error.h:42
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
void sama5d3EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
const NicDriver sama5d3EthDriver
SAMA5D3 Ethernet MAC driver.
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
#define EMAC_RMII_MASK
#define TRACE_DEBUG(...)
Definition: debug.h:107
error_t sama5d3EthInit(NetInterface *interface)
SAMA5D3 Ethernet MAC initialization.
uint16_t regAddr
#define EMAC_TX_USED
#define ETH_MTU
Definition: ethernet.h:105
error_t sama5d3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define SAMA5D3_ETH_IRQ_PRIORITY
#define osEnterIsr()
#define EMAC_RX_ADDRESS
void sama5d3EthInitGpio(NetInterface *interface)
#define EMAC_TX_WRAP
#define EMAC_RX_SOF
#define SAMA5D3_ETH_RX_BUFFER_SIZE
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void sama5d3EthEnableIrq(NetInterface *interface)
Enable interrupts.
Transmit buffer descriptor.
SAMA5D3 Ethernet MAC driver.
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
void sama5d3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Receive buffer descriptor.
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:56
void sama5d3EthIrqHandler(void)
SAMA5D3 Ethernet MAC interrupt service routine.
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define EMAC_TX_LAST
Ethernet interface.
Definition: nic.h:82