sama5d3_eth_driver.c
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1 /**
2  * @file sama5d3_eth_driver.c
3  * @brief SAMA5D3 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "sama5d3x.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
47 #pragma location = ".ram_no_cache"
49 //RX buffer
50 #pragma data_alignment = 8
51 #pragma location = ".ram_no_cache"
53 //TX buffer descriptors
54 #pragma data_alignment = 8
55 #pragma location = ".ram_no_cache"
57 //RX buffer descriptors
58 #pragma data_alignment = 8
59 #pragma location = ".ram_no_cache"
61 
62 //GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(8), __section__(".ram_no_cache")));
68 //RX buffer
70  __attribute__((aligned(8), __section__(".ram_no_cache")));
71 //TX buffer descriptors
73  __attribute__((aligned(8), __section__(".ram_no_cache")));
74 //RX buffer descriptors
76  __attribute__((aligned(8), __section__(".ram_no_cache")));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief SAMA5D3 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief SAMA5D3 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing SAMA5D3 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Enable EMAC peripheral clock
129  PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
130  //Enable IRQ controller peripheral clock
131  PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
132 
133  //GPIO configuration
134  sama5d3EthInitGpio(interface);
135 
136  //Configure MDC clock speed
137  EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
138  //Enable management port (MDC and MDIO)
139  EMAC->EMAC_NCR |= EMAC_NCR_MPE;
140 
141  //PHY transceiver initialization
142  error = interface->phyDriver->init(interface);
143  //Failed to initialize PHY transceiver?
144  if(error)
145  return error;
146 
147  //Set the MAC address
148  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
149  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
150 
151  //Configure the receive filter
152  EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI | EMAC_NCFGR_MTI;
153 
154  //Initialize hash table
155  EMAC->EMAC_HRB = 0;
156  EMAC->EMAC_HRT = 0;
157 
158  //Initialize buffer descriptors
159  sama5d3EthInitBufferDesc(interface);
160 
161  //Clear transmit status register
162  EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
163  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
164  //Clear receive status register
165  EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
166 
167  //First disable all EMAC interrupts
168  EMAC->EMAC_IDR = 0xFFFFFFFF;
169  //Only the desired ones are enabled
170  EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
171  EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
172 
173  //Read EMAC ISR register to clear any pending interrupt
174  status = EMAC->EMAC_ISR;
175 
176  //Configure interrupt controller
177  AIC->AIC_SSR = ID_EMAC;
178  AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_ETH_IRQ_PRIORITY);
179  AIC->AIC_SVR = (uint32_t) sama5d3EthIrqHandler;
180 
181  //Enable the EMAC to transmit and receive data
182  EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
183 
184  //Accept any packets from the upper layer
185  osSetEvent(&interface->nicTxEvent);
186 
187  //Successful initialization
188  return NO_ERROR;
189 }
190 
191 
192 //SAMA5D3-Xplained evaluation board?
193 #if defined(USE_SAMA5D3_XPLAINED)
194 
195 /**
196  * @brief GPIO configuration
197  * @param[in] interface Underlying network interface
198  **/
199 
200 void sama5d3EthInitGpio(NetInterface *interface)
201 {
202  //Enable PIO peripheral clock
203  PMC->PMC_PCER0 = (1 << ID_PIOC);
204 
205  //Disable pull-up resistors on RMII pins
206  PIOC->PIO_PUDR = EMAC_RMII_MASK;
207  //Disable interrupts-on-change
208  PIOC->PIO_IDR = EMAC_RMII_MASK;
209  //Assign RMII pins to peripheral A function
210  PIOC->PIO_ABCDSR[0] &= ~EMAC_RMII_MASK;
211  PIOC->PIO_ABCDSR[1] &= ~EMAC_RMII_MASK;
212  //Disable the PIO from controlling the corresponding pins
213  PIOC->PIO_PDR = EMAC_RMII_MASK;
214 
215  //Select RMII operation mode and enable transceiver clock
216  EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
217 }
218 
219 #endif
220 
221 
222 /**
223  * @brief Initialize buffer descriptors
224  * @param[in] interface Underlying network interface
225  **/
226 
228 {
229  uint_t i;
230  uint32_t address;
231 
232  //Initialize TX buffer descriptors
233  for(i = 0; i < SAMA5D3_ETH_TX_BUFFER_COUNT; i++)
234  {
235  //Calculate the address of the current TX buffer
236  address = (uint32_t) txBuffer[i];
237  //Write the address to the descriptor entry
238  txBufferDesc[i].address = address;
239  //Initialize status field
240  txBufferDesc[i].status = EMAC_TX_USED;
241  }
242 
243  //Mark the last descriptor entry with the wrap flag
244  txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
245  //Initialize TX buffer index
246  txBufferIndex = 0;
247 
248  //Initialize RX buffer descriptors
249  for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
250  {
251  //Calculate the address of the current RX buffer
252  address = (uint32_t) rxBuffer[i];
253  //Write the address to the descriptor entry
254  rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
255  //Clear status field
256  rxBufferDesc[i].status = 0;
257  }
258 
259  //Mark the last descriptor entry with the wrap flag
260  rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
261  //Initialize RX buffer index
262  rxBufferIndex = 0;
263 
264  //Start location of the TX descriptor list
265  EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
266  //Start location of the RX descriptor list
267  EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
268 }
269 
270 
271 /**
272  * @brief SAMA5D3 Ethernet MAC timer handler
273  *
274  * This routine is periodically called by the TCP/IP stack to
275  * handle periodic operations such as polling the link state
276  *
277  * @param[in] interface Underlying network interface
278  **/
279 
280 void sama5d3EthTick(NetInterface *interface)
281 {
282  //Handle periodic operations
283  interface->phyDriver->tick(interface);
284 }
285 
286 
287 /**
288  * @brief Enable interrupts
289  * @param[in] interface Underlying network interface
290  **/
291 
293 {
294  //Enable Ethernet MAC interrupts
295  AIC->AIC_SSR = ID_EMAC;
296  AIC->AIC_IECR = AIC_IECR_INTEN;
297 
298  //Enable Ethernet PHY interrupts
299  interface->phyDriver->enableIrq(interface);
300 }
301 
302 
303 /**
304  * @brief Disable interrupts
305  * @param[in] interface Underlying network interface
306  **/
307 
309 {
310  //Disable Ethernet MAC interrupts
311  AIC->AIC_SSR = ID_EMAC;
312  AIC->AIC_IDCR = AIC_IDCR_INTD;
313 
314  //Disable Ethernet PHY interrupts
315  interface->phyDriver->disableIrq(interface);
316 }
317 
318 
319 /**
320  * @brief SAMA5D3 Ethernet MAC interrupt service routine
321  **/
322 
324 {
325  bool_t flag;
326  volatile uint32_t isr;
327  volatile uint32_t tsr;
328  volatile uint32_t rsr;
329 
330  //Enter interrupt service routine
331  osEnterIsr();
332 
333  //This flag will be set if a higher priority task must be woken
334  flag = FALSE;
335 
336  //Each time the software reads EMAC_ISR, it has to check the
337  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
338  isr = EMAC->EMAC_ISR;
339  tsr = EMAC->EMAC_TSR;
340  rsr = EMAC->EMAC_RSR;
341 
342  //A packet has been transmitted?
343  if(tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
344  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR))
345  {
346  //Only clear TSR flags that are currently set
347  EMAC->EMAC_TSR = tsr;
348 
349  //Check whether the TX buffer is available for writing
350  if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
351  {
352  //Notify the TCP/IP stack that the transmitter is ready to send
353  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
354  }
355  }
356 
357  //A packet has been received?
358  if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
359  {
360  //Set event flag
361  nicDriverInterface->nicEvent = TRUE;
362  //Notify the TCP/IP stack of the event
363  flag |= osSetEventFromIsr(&netEvent);
364  }
365 
366  //Write AIC_EOICR register before exiting
367  AIC->AIC_EOICR = 0;
368 
369  //Leave interrupt service routine
370  osExitIsr(flag);
371 }
372 
373 
374 /**
375  * @brief SAMA5D3 Ethernet MAC event handler
376  * @param[in] interface Underlying network interface
377  **/
378 
380 {
381  error_t error;
382  uint32_t rsr;
383 
384  //Read receive status
385  rsr = EMAC->EMAC_RSR;
386 
387  //Packet received?
388  if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
389  {
390  //Only clear RSR flags that are currently set
391  EMAC->EMAC_RSR = rsr;
392 
393  //Process all pending packets
394  do
395  {
396  //Read incoming packet
397  error = sama5d3EthReceivePacket(interface);
398 
399  //No more data in the receive buffer?
400  } while(error != ERROR_BUFFER_EMPTY);
401  }
402 }
403 
404 
405 /**
406  * @brief Send a packet
407  * @param[in] interface Underlying network interface
408  * @param[in] buffer Multi-part buffer containing the data to send
409  * @param[in] offset Offset to the first data byte
410  * @return Error code
411  **/
412 
414  const NetBuffer *buffer, size_t offset)
415 {
416  size_t length;
417 
418  //Retrieve the length of the packet
419  length = netBufferGetLength(buffer) - offset;
420 
421  //Check the frame length
423  {
424  //The transmitter can accept another packet
425  osSetEvent(&interface->nicTxEvent);
426  //Report an error
427  return ERROR_INVALID_LENGTH;
428  }
429 
430  //Make sure the current buffer is available for writing
431  if(!(txBufferDesc[txBufferIndex].status & EMAC_TX_USED))
432  return ERROR_FAILURE;
433 
434  //Copy user data to the transmit buffer
435  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
436 
437  //Set the necessary flags in the descriptor entry
438  if(txBufferIndex < (SAMA5D3_ETH_TX_BUFFER_COUNT - 1))
439  {
440  //Write the status word
441  txBufferDesc[txBufferIndex].status =
443 
444  //Point to the next buffer
445  txBufferIndex++;
446  }
447  else
448  {
449  //Write the status word
450  txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP |
452 
453  //Wrap around
454  txBufferIndex = 0;
455  }
456 
457  //Set the TSTART bit to initiate transmission
458  EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
459 
460  //Check whether the next buffer is available for writing
461  if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
462  {
463  //The transmitter can accept another packet
464  osSetEvent(&interface->nicTxEvent);
465  }
466 
467  //Successful processing
468  return NO_ERROR;
469 }
470 
471 
472 /**
473  * @brief Receive a packet
474  * @param[in] interface Underlying network interface
475  * @return Error code
476  **/
477 
479 {
480  static uint8_t temp[ETH_MAX_FRAME_SIZE];
481  error_t error;
482  uint_t i;
483  uint_t j;
484  uint_t sofIndex;
485  uint_t eofIndex;
486  size_t n;
487  size_t size;
488  size_t length;
489 
490  //Initialize SOF and EOF indices
491  sofIndex = UINT_MAX;
492  eofIndex = UINT_MAX;
493 
494  //Search for SOF and EOF flags
495  for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
496  {
497  //Point to the current entry
498  j = rxBufferIndex + i;
499 
500  //Wrap around to the beginning of the buffer if necessary
503 
504  //No more entries to process?
505  if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
506  {
507  //Stop processing
508  break;
509  }
510  //A valid SOF has been found?
511  if(rxBufferDesc[j].status & EMAC_RX_SOF)
512  {
513  //Save the position of the SOF
514  sofIndex = i;
515  }
516  //A valid EOF has been found?
517  if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
518  {
519  //Save the position of the EOF
520  eofIndex = i;
521  //Retrieve the length of the frame
522  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
523  //Limit the number of data to read
524  size = MIN(size, ETH_MAX_FRAME_SIZE);
525  //Stop processing since we have reached the end of the frame
526  break;
527  }
528  }
529 
530  //Determine the number of entries to process
531  if(eofIndex != UINT_MAX)
532  j = eofIndex + 1;
533  else if(sofIndex != UINT_MAX)
534  j = sofIndex;
535  else
536  j = i;
537 
538  //Total number of bytes that have been copied from the receive buffer
539  length = 0;
540 
541  //Process incoming frame
542  for(i = 0; i < j; i++)
543  {
544  //Any data to copy from current buffer?
545  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
546  {
547  //Calculate the number of bytes to read at a time
549  //Copy data from receive buffer
550  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
551  //Update byte counters
552  length += n;
553  size -= n;
554  }
555 
556  //Mark the current buffer as free
557  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
558 
559  //Point to the following entry
560  rxBufferIndex++;
561 
562  //Wrap around to the beginning of the buffer if necessary
563  if(rxBufferIndex >= SAMA5D3_ETH_RX_BUFFER_COUNT)
564  rxBufferIndex = 0;
565  }
566 
567  //Any packet to process?
568  if(length > 0)
569  {
570  //Pass the packet to the upper layer
571  nicProcessPacket(interface, temp, length);
572  //Valid packet received
573  error = NO_ERROR;
574  }
575  else
576  {
577  //No more data in the receive buffer
578  error = ERROR_BUFFER_EMPTY;
579  }
580 
581  //Return status code
582  return error;
583 }
584 
585 
586 /**
587  * @brief Configure MAC address filtering
588  * @param[in] interface Underlying network interface
589  * @return Error code
590  **/
591 
593 {
594  uint_t i;
595  uint_t k;
596  uint8_t *p;
597  uint32_t hashTable[2];
598  MacFilterEntry *entry;
599 
600  //Debug message
601  TRACE_DEBUG("Updating SAMA5D3 hash table...\r\n");
602 
603  //Clear hash table
604  hashTable[0] = 0;
605  hashTable[1] = 0;
606 
607  //The MAC address filter contains the list of MAC addresses to accept
608  //when receiving an Ethernet frame
609  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
610  {
611  //Point to the current entry
612  entry = &interface->macAddrFilter[i];
613 
614  //Valid entry?
615  if(entry->refCount > 0)
616  {
617  //Point to the MAC address
618  p = entry->addr.b;
619 
620  //Apply the hash function
621  k = (p[0] >> 6) ^ p[0];
622  k ^= (p[1] >> 4) ^ (p[1] << 2);
623  k ^= (p[2] >> 2) ^ (p[2] << 4);
624  k ^= (p[3] >> 6) ^ p[3];
625  k ^= (p[4] >> 4) ^ (p[4] << 2);
626  k ^= (p[5] >> 2) ^ (p[5] << 4);
627 
628  //The hash value is reduced to a 6-bit index
629  k &= 0x3F;
630 
631  //Update hash table contents
632  hashTable[k / 32] |= (1 << (k % 32));
633  }
634  }
635 
636  //Write the hash table
637  EMAC->EMAC_HRB = hashTable[0];
638  EMAC->EMAC_HRT = hashTable[1];
639 
640  //Debug message
641  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
642  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
643 
644  //Successful processing
645  return NO_ERROR;
646 }
647 
648 
649 /**
650  * @brief Adjust MAC configuration parameters for proper operation
651  * @param[in] interface Underlying network interface
652  * @return Error code
653  **/
654 
656 {
657  uint32_t config;
658 
659  //Read network configuration register
660  config = EMAC->EMAC_NCFGR;
661 
662  //10BASE-T or 100BASE-TX operation mode?
663  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
664  config |= EMAC_NCFGR_SPD;
665  else
666  config &= ~EMAC_NCFGR_SPD;
667 
668  //Half-duplex or full-duplex mode?
669  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
670  config |= EMAC_NCFGR_FD;
671  else
672  config &= ~EMAC_NCFGR_FD;
673 
674  //Write configuration value back to NCFGR register
675  EMAC->EMAC_NCFGR = config;
676 
677  //Successful processing
678  return NO_ERROR;
679 }
680 
681 
682 /**
683  * @brief Write PHY register
684  * @param[in] phyAddr PHY address
685  * @param[in] regAddr Register address
686  * @param[in] data Register value
687  **/
688 
689 void sama5d3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
690 {
691  uint32_t value;
692 
693  //Set up a write operation
694  value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
695  //PHY address
696  value |= EMAC_MAN_PHYA(phyAddr);
697  //Register address
698  value |= EMAC_MAN_REGA(regAddr);
699  //Register value
700  value |= EMAC_MAN_DATA(data);
701 
702  //Start a write operation
703  EMAC->EMAC_MAN = value;
704  //Wait for the write to complete
705  while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
706 }
707 
708 
709 /**
710  * @brief Read PHY register
711  * @param[in] phyAddr PHY address
712  * @param[in] regAddr Register address
713  * @return Register value
714  **/
715 
716 uint16_t sama5d3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
717 {
718  uint32_t value;
719 
720  //Set up a read operation
721  value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
722  //PHY address
723  value |= EMAC_MAN_PHYA(phyAddr);
724  //Register address
725  value |= EMAC_MAN_REGA(regAddr);
726 
727  //Start a read operation
728  EMAC->EMAC_MAN = value;
729  //Wait for the read to complete
730  while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
731 
732  //Return PHY register contents
733  return EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
734 }
#define SAMA5D3_ETH_TX_BUFFER_COUNT
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
error_t sama5d3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define EMAC_RX_ADDRESS
error_t sama5d3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define SAMA5D3_ETH_IRQ_PRIORITY
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
#define EMAC_TX_WRAP
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define EMAC_RX_SOF
Generic error code.
Definition: error.h:43
#define SAMA5D3_ETH_RX_BUFFER_SIZE
#define txBuffer
void sama5d3EthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver sama5d3EthDriver
SAMA5D3 Ethernet MAC driver.
void sama5d3EthTick(NetInterface *interface)
SAMA5D3 Ethernet MAC timer handler.
#define SAMA5D3_ETH_RX_BUFFER_COUNT
error_t sama5d3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define EMAC_TX_USED
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
Receive buffer descriptor.
#define EMAC_RX_EOF
Transmit buffer descriptor.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
uint16_t sama5d3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
NIC driver.
Definition: nic.h:161
#define EMAC_RX_LENGTH
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void sama5d3EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void sama5d3EthDisableIrq(NetInterface *interface)
Disable interrupts.
void sama5d3EthInitGpio(NetInterface *interface)
#define EMAC_TX_LAST
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
Ipv6Addr address
void sama5d3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
void sama5d3EthIrqHandler(void)
SAMA5D3 Ethernet MAC interrupt service routine.
void sama5d3EthEventHandler(NetInterface *interface)
SAMA5D3 Ethernet MAC event handler.
unsigned int uint_t
Definition: compiler_port.h:43
#define EMAC_TX_LENGTH
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
#define SAMA5D3_ETH_TX_BUFFER_SIZE
error_t sama5d3EthReceivePacket(NetInterface *interface)
Receive a packet.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
SAMA5D3 Ethernet MAC controller.
error_t sama5d3EthInit(NetInterface *interface)
SAMA5D3 Ethernet MAC initialization.
#define osExitIsr(flag)
#define EMAC_RX_OWNERSHIP
#define EMAC_RMII_MASK
#define EMAC_RX_WRAP
#define osEnterIsr()
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98