32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "stm32h5xx.h"
36 #include "stm32h5xx_hal.h"
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 4
49 #pragma location = STM32H5XX_ETH_RAM_SECTION
52 #pragma data_alignment = 4
53 #pragma location = STM32H5XX_ETH_RAM_SECTION
56 #pragma data_alignment = 4
57 #pragma location = STM32H5XX_ETH_RAM_SECTION
60 #pragma data_alignment = 4
61 #pragma location = STM32H5XX_ETH_RAM_SECTION
125 TRACE_INFO(
"Initializing STM32H5 Ethernet MAC...\r\n");
128 nicDriverInterface = interface;
134 __HAL_RCC_ETH_CLK_ENABLE();
135 __HAL_RCC_ETHTX_CLK_ENABLE();
136 __HAL_RCC_ETHRX_CLK_ENABLE();
139 __HAL_RCC_ETH_FORCE_RESET();
140 __HAL_RCC_ETH_RELEASE_RESET();
143 ETH->DMAMR |= ETH_DMAMR_SWR;
145 while((ETH->DMAMR & ETH_DMAMR_SWR) != 0)
150 ETH->MACMDIOAR = ETH_MACMDIOAR_CR_DIV124;
153 if(interface->phyDriver != NULL)
156 error = interface->phyDriver->init(interface);
158 else if(interface->switchDriver != NULL)
161 error = interface->switchDriver->init(interface);
179 temp = ETH->MACECR & ~ETH_MACECR_GPSL;
190 ETH->DMAMR = ETH_DMAMR_INTM_0 | ETH_DMAMR_PR_1_1;
192 ETH->DMASBMR |= ETH_DMASBMR_AAL;
194 ETH->DMACCR = ETH_DMACCR_DSL_0BIT;
197 ETH->DMACTCR = ETH_DMACTCR_TPBL_32PBL;
200 ETH->DMACRCR = ETH_DMACRCR_RPBL_32PBL;
204 ETH->MTLTQOMR |= ETH_MTLTQOMR_TSF;
205 ETH->MTLRQOMR |= ETH_MTLRQOMR_RSF;
223 ETH->DMACIER = ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE;
233 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
236 ETH->DMACTCR |= ETH_DMACTCR_ST;
237 ETH->DMACRCR |= ETH_DMACRCR_SR;
255 #if defined(USE_STM32H573I_DK)
256 GPIO_InitTypeDef GPIO_InitStructure;
259 __HAL_RCC_SBS_CLK_ENABLE();
262 __HAL_RCC_GPIOA_CLK_ENABLE();
263 __HAL_RCC_GPIOC_CLK_ENABLE();
264 __HAL_RCC_GPIOG_CLK_ENABLE();
267 HAL_SBS_ETHInterfaceSelect(SBS_ETH_RMII);
270 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
271 GPIO_InitStructure.Pull = GPIO_NOPULL;
272 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
273 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
276 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
277 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
280 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
281 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
284 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
285 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
288 #elif defined(USE_STM32H5XX_NUCLEO)
289 GPIO_InitTypeDef GPIO_InitStructure;
292 __HAL_RCC_SBS_CLK_ENABLE();
295 __HAL_RCC_GPIOA_CLK_ENABLE();
296 __HAL_RCC_GPIOB_CLK_ENABLE();
297 __HAL_RCC_GPIOC_CLK_ENABLE();
298 __HAL_RCC_GPIOG_CLK_ENABLE();
301 HAL_SBS_ETHInterfaceSelect(SBS_ETH_RMII);
304 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
305 GPIO_InitStructure.Pull = GPIO_NOPULL;
306 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
307 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
310 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
311 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
314 GPIO_InitStructure.Pin = GPIO_PIN_15;
315 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
318 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
319 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
322 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
323 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
364 ETH->DMACTDLAR = (uint32_t) &
txDmaDesc[0];
369 ETH->DMACRDLAR = (uint32_t) &
rxDmaDesc[0];
387 if(interface->phyDriver != NULL)
390 interface->phyDriver->tick(interface);
392 else if(interface->switchDriver != NULL)
395 interface->switchDriver->tick(interface);
412 NVIC_EnableIRQ(ETH_IRQn);
415 if(interface->phyDriver != NULL)
418 interface->phyDriver->enableIrq(interface);
420 else if(interface->switchDriver != NULL)
423 interface->switchDriver->enableIrq(interface);
440 NVIC_DisableIRQ(ETH_IRQn);
443 if(interface->phyDriver != NULL)
446 interface->phyDriver->disableIrq(interface);
448 else if(interface->switchDriver != NULL)
451 interface->switchDriver->disableIrq(interface);
476 status = ETH->DMACSR;
479 if((status & ETH_DMACSR_TI) != 0)
482 ETH->DMACSR = ETH_DMACSR_TI;
493 if((status & ETH_DMACSR_RI) != 0)
496 ETH->DMACSR = ETH_DMACSR_RI;
499 nicDriverInterface->nicEvent =
TRUE;
505 ETH->DMACSR = ETH_DMACSR_NIS;
579 ETH->DMACSR = ETH_DMACSR_TBU;
626 if((SBS->PMCR & SBS_PMCR_ETH_SEL_PHY) != SBS_ETH_MII)
678 ETH->DMACSR = ETH_DMACSR_RBU;
699 uint32_t hashTable[2];
707 if(interface->promiscuous)
710 ETH->MACPFR = ETH_MACPFR_PR;
715 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
716 ETH->MACA0HR = interface->macAddr.w[2];
732 entry = &interface->macAddrFilter[i];
745 k = (crc >> 26) & 0x3F;
748 hashTable[k / 32] |= (1 << (k % 32));
756 unicastMacAddr[j++] = entry->
addr;
766 ETH->MACA1LR = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
767 ETH->MACA1HR = unicastMacAddr[0].w[2] | ETH_MACAHR_AE;
780 ETH->MACA2LR = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
781 ETH->MACA2HR = unicastMacAddr[1].w[2] | ETH_MACAHR_AE;
794 ETH->MACA3LR = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
795 ETH->MACA3HR = unicastMacAddr[2].w[2] | ETH_MACAHR_AE;
806 if(interface->acceptAllMulticast)
809 ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_PM;
814 ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
817 ETH->MACHT0R = hashTable[0];
818 ETH->MACHT1R = hashTable[1];
821 TRACE_DEBUG(
" MACHT0R = %08" PRIX32
"\r\n", ETH->MACHT0R);
822 TRACE_DEBUG(
" MACHT1R = %08" PRIX32
"\r\n", ETH->MACHT1R);
847 config |= ETH_MACCR_FES;
851 config &= ~ETH_MACCR_FES;
857 config |= ETH_MACCR_DM;
861 config &= ~ETH_MACCR_DM;
889 temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
891 temp |= ETH_MACMDIOAR_MOC_WR | ETH_MACMDIOAR_MB;
893 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
895 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
898 ETH->MACMDIODR =
data & ETH_MACMDIODR_MD;
901 ETH->MACMDIOAR = temp;
903 while((ETH->MACMDIOAR & ETH_MACMDIOAR_MB) != 0)
932 temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
934 temp |= ETH_MACMDIOAR_MOC_RD | ETH_MACMDIOAR_MB;
936 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
938 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
941 ETH->MACMDIOAR = temp;
943 while((ETH->MACMDIOAR & ETH_MACMDIOAR_MB) != 0)
948 data = ETH->MACMDIODR & ETH_MACMDIODR_MD;
976 p = (uint8_t *)
data;
981 for(i = 0; i <
length; i++)
984 for(j = 0; j < 8; j++)
987 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
989 crc = (crc << 1) ^ 0x04C11DB7;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define ETH_MACCR_RESERVED15
error_t stm32h5xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void stm32h5xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
void stm32h5xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver stm32h5xxEthDriver
STM32H5 Ethernet MAC driver.
error_t stm32h5xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t stm32h5xxEthInit(NetInterface *interface)
STM32H5 Ethernet MAC initialization.
void stm32h5xxEthEventHandler(NetInterface *interface)
STM32H5 Ethernet MAC event handler.
uint16_t stm32h5xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t stm32h5xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
__weak_func void stm32h5xxEthInitGpio(NetInterface *interface)
GPIO configuration.
void ETH_IRQHandler(void)
STM32H5 Ethernet MAC interrupt service routine.
uint32_t stm32h5xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
void stm32h5xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void stm32h5xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t stm32h5xxEthReceivePacket(NetInterface *interface)
Receive a packet.
void stm32h5xxEthTick(NetInterface *interface)
STM32H5 Ethernet MAC timer handler.
STM32H5 Ethernet MAC driver.
#define STM32H5XX_ETH_RX_BUFFER_COUNT
#define ETH_MMCTIMR_TXLPIUSCIM
#define STM32H5XX_ETH_IRQ_PRIORITY_GROUPING
#define ETH_MMCTIMR_TXSCOLGPIM
#define STM32H5XX_ETH_TX_BUFFER_COUNT
#define ETH_MMCTIMR_TXLPITRCIM
#define STM32H5XX_ETH_RX_BUFFER_SIZE
#define ETH_MMCTIMR_TXMCOLGPIM
#define STM32H5XX_ETH_TX_BUFFER_SIZE
#define ETH_MMCRIMR_RXUCGPIM
#define ETH_MMCTIMR_TXGPKTIM
#define ETH_MMCRIMR_RXALGNERPIM
#define STM32H5XX_ETH_RAM_SECTION
#define STM32H5XX_ETH_IRQ_SUB_PRIORITY
#define STM32H5XX_ETH_IRQ_GROUP_PRIORITY
#define ETH_MMCRIMR_RXLPIUSCIM
#define ETH_MMCRIMR_RXLPITRCIM
#define ETH_MMCRIMR_RXCRCERPIM
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.